JPH03203868A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To avoid the occurrence of foreign sounds to muffle sounds with a simple constitution by generating a muting signal on demand in each circuit block and synthesizing the generated muting signal to generate a synthesized muting signal. CONSTITUTION:An error detecting and correcting circuit 56 is provided which performs the error detection and correction processing of reproduced audio data DPB based on recording information DPB, and a reproduced signal processing circuit 58, the error detecting and correcting circuit 56, a data output circuit 52, and/or a control circuit (data input/output circuit) 40 generates a muting signal DM4 based on control data DCONT, recording information DPB, and/or the processing result of the error detection and correction processing, and a muting signal synthesizing circuit 53 synthesizes this generated muting signal DM4 to generate a synthesized muting signal MT. Thus, the occurrence of foreign sounds is avoided to muffle a monitor being in course of reproducing.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A: Industrial field of application B: Outline of the invention C: Conventional technology: Problems to be solved by the invention E: Means for solving the problem (Figs. 1 to 3) F Effects (Figs. 1 to 3) Figure) G Embodiment (Figures 1 to 3) (G1) First Embodiment (G2) Other Embodiments H Effects of the Invention A Industrial Application Field The present invention relates to a digital signal processing circuit, for example It can be applied to a digital audio recorder that records and plays back audio signals.

B Summary of the Invention The present invention has a simple configuration in which a mute signal is generated in each circuit block as necessary in a digital signal processing circuit, and the generated mute signals are synthesized to generate a composite mute signal. The generation of abnormal noise can be effectively avoided and silenced.

C. Prior Art Conventionally, some magnetic recording and reproducing apparatuses (hereinafter referred to as digital audio tape recorders) are capable of recording and reproducing digital audio signals using a rotating drum.

That is, during recording, after converting an audio signal into a digital signal, it is divided into blocks at each predetermined interleaving period, and interleaving processing is performed for each block.

Furthermore, after generating inner and outer codes for error detection and correction on a block-by-block basis, the interleaved digital signal is converted into a recording signal and output to the magnetic head.

On the other hand, during reproduction, the reproduced signal is demodulated by a demodulation circuit, and the resulting reproduced data is error-corrected by an error detection and correction circuit.

Furthermore, the error-corrected reproduced data is subjected to deinterleave processing in an output circuit, converted into an analog signal, and output.

In this way, audio signals consisting of analog signals can be converted into digital signals and recorded and reproduced, so that deterioration in sound quality can be effectively avoided and audio signals can be recorded and reproduced at high density.

Problems to be Solved by the Invention Incidentally, this type of digital audio recorder has the characteristic that the overall configuration is unavoidably complicated because the audio signal is converted into a digital signal and processed. .

Therefore, if circuit blocks such as digital signal processing circuits and servo circuits are integrated into integrated circuits, the overall configuration can be simplified accordingly.

Furthermore, at this time, if the tracking servo disturbance, which was conventionally detected by the system control circuit, can be detected by an integrated digital signal processing circuit, the digital signal processing circuit can force the reproduced data to have a value of 0. (hereinafter referred to as playback data muting), the signal level of the playback audio signal output from the digital audio tape recorder can be maintained at a constant value.

Therefore, the connection between the system control circuit and the digital signal processing circuit can be simplified compared to the conventional system, and the reproduced audio signal can be easily muted when the tracking servo is disturbed.

Similarly, if the digital signal processing circuit could independently detect the recording format of a magnetic tape, which was conventionally detected by the system control circuit, it would be possible to independently detect the format switching of the magnetic tape being played, for example. can be detected and the operation of the digital signal processing circuit can be switched in response.

If the digital signal processing circuit forcibly mutes the reproduced data during the period during which the operation is switched at this time, the reproduced audio signal can be muted with a simple configuration when the format is switched.

However, when the reproduced audio signal is muted by muting the reproduced data in this manner, there is a risk that abnormal noise may be generated during muting due to the influence of the offset voltage of the digital-to-analog conversion circuit.

The present invention has been made in consideration of the above points, and even when the digital signal processing circuit independently mutes the reproduced data, it is possible to effectively avoid the generation of abnormal noise and reliably mute the reproduced audio signal. The purpose of this paper is to propose a digital signal processing circuit that can perform the following tasks.

E Means for Solving the Problem In order to solve this problem, the first invention includes a memory circuit 44 that stores the reproduced audio data DPl, and a memory circuit 44 that stores the reproduced audio data DPl, and demodulates the reproduced signal SRF to store the reproduced audio data D□.
and a reproduction signal processing circuit 58 that obtains recording information D□ and stores reproduction audio data DPI in the memory circuit 44 based on the recording information DPI;
An error detection and correction circuit 56 that performs error detection and correction processing on the reproduced audio data D□, and a data output circuit 52 that converts the reproduced audio data DPIl stored in the memory circuit 44 into a reproduced digital audio signal DADT based on the recorded information D□. and a control circuit 4 that switches the operations of the reproduced signal processing circuit 58, error detection and correction circuit 56, and data output circuit 52 based on predetermined control data I)coNt.
0, a mute signal synthesis circuit 52 that synthesizes and sends a synthesized mute signal MT, and a reproduced data mute circuit 54 and 55 that mutes and transmits a reproduced digital audio signal DADT based on the synthesized mute signal MT, The reproduced signal processing circuit 58, the error detection and correction circuit 56, the data output circuit 52, and/or the control circuit 40 outputs control data D. The mute signal DP14 is generated based on the recorded information DPI and/or the processing result of the error detection and correction process, and the mute signal synthesis circuit 53 generates the mute signal DP14.
, the error detection and correction circuit 56, the data output circuit 52, and/or the control circuit 40 are combined to generate a composite mute signal MT.

Furthermore, in the second invention, the memory circuit 44 stores input audio data and error detection and correction codes, and the memory circuit 44 converts the input digital audio signals ADDT and RX into input audio data based on the control data DCONT. a data input/output circuit 52 that outputs a digital audio signal DADT for monitoring the input digital audio signals ADDT and RX;
．． 46, and an error detection and correction circuit 56 that generates an error detection and correction code for the input audio data stored in the memory circuit 44 based on the control data I)coat and stores the error detection and correction code in the memory circuit 44. , control data D
,. Based on the input audio data and the error detection and correction code stored in the memory circuit 44, the recording signal S
It includes a recording signal generation circuit 60 that converts to REC, a mute signal synthesis circuit 53 that synthesizes and sends out a composite mute signal MT, and a data mute circuit 54 and 55 that mutes and sends out a monitor digital audio signal DADT, Data input/output circuit 52, error detection and correction circuit 56
and/or the recording signal generation circuit 60 generates control data DCON
? and/or input digital audio signal ADDT,R
Generate a mute signal Dnt%Di based on X,
The mute signal synthesis circuit 53 includes a data input/output circuit 52,
The mute signal DM generated by the error detection and correction circuit 56 and/or the recording signal generation circuit 60! ,D,43 are synthesized,
A composite mute signal MT is generated.

F action control data DcoNy, recording information @DP! The mute signal I) t4 generated based on the processing result of the error detection and correction process is synthesized to obtain a synthesized mute signal MT, and the reproduced digital audio signal DADT is muted with the synthesized mute signal MT, and the synthesized By outputting the mute signal MT, it is possible to mute the line as necessary, effectively avoiding the occurrence of abnormal noise, and muting the monitor during playback.

Furthermore, control data D,. NT and/or the mute signals D□, DM3 generated based on the input digital audio signals ADDT, RX are synthesized to generate a composite mute signal MT.
If the synthesized mute signal MT is used to mute the monitor digital audio signal DADT and the synthesized mute signal MT is output, line muting can be performed as necessary, and recording can be performed while effectively avoiding the occurrence of abnormal noise. The monitor inside can be muted.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) First Embodiment In FIG. 1, l indicates a digital audio tape recorder as a whole, and the audio signal SIN% 5o
Record and play back ot.

That is, in the digital audio tape recorder 1, the input display circuit 2 having an arithmetic processing circuit configuration outputs the operation data D sou in response to the operation of the operator.
The display on the display panel is switched based on predetermined control data.

As a result, in the digital audio tape recorder 1, the operating mode can be switched in response to the operation of the operator, and the operating state can be confirmed through the display on the display panel.

The system control circuit 6 receives the operation data D,. Based on the digital audio tape 1, control data and the like are generated, thereby controlling the operation of the digital audio tape 1.

That is, when the recording operator is operated, the system control circuit 6 sets the operation mode of the digital audio tape recorder 1 to the recording mode.

At this time, the system control circuit 6 adds predetermined data to the control data output to the digital signal processing circuit 8, thereby recording the digital audio signal in a recording format determined by the status byte of the control data and recording the monitor signal S. . It is designed to output ut.

In contrast, when the playback operator is operated, the operation mode of the digital audio tape recorder 1 is set to playback mode.

At this time, when the mute operator is turned on, the system control circuit 6 sends a mute signal to the digital signal processing circuit 8. 1, thereby muting the monitor signal and reproduced audio signal 5ovt output from the digital audio tape recorder 1.

The mechanical control circuit 10 drives and controls a tape cassette loading/unloading mechanism, a magnetic tape loading mechanism, etc. based on control data.

The servo circuit 12 drives the reel motor 16 based on the control data, thereby rotating the reel of a magnetic tape cassette (not shown) at a predetermined speed.

Further, the servo circuit 12 generates a switching pulse signal SWP whose signal level changes at the start of scanning of the magnetic head during recording and reproduction, so that the switching pulse signal SWP has a predetermined phase with respect to the rotating drum reference signal DREF. The drum motor 22 is driven.

As a result, the servo circuit 12 controls the drum motor 22 so that the rotating drum 20 rotates once in one interleaving cycle.
to drive.

Furthermore, the servo circuit 12 drives the capstan motor 26 so that the magnetic tape 15 travels two track pitches in one interleave period, thereby sequentially recording data in a format standardized for the digital audio tape recorder. form a track.

Furthermore, during reproduction, the servo circuit 12 performs tracking control on the capstan motor 26 based on the tracking error signal output from the tracking control circuit 24.

Note that the rotating drum reference signal DREF is
60 (w+sec) and 3 in P mode (consisting of long time recording mode and standard time recording mode respectively)
It is a reference signal with a duty ratio of 50 (%) that repeats at an interleave period of 0 (*5 ec).

As shown in FIG. 2, during recording, the audio signal conversion circuit 30 provides an input audio signal SIN to an analog-to-digital conversion circuit (A/D) 31B via a low-pass filter circuit (LPF) 31A. The input audio signal SIN is converted to the digital audio signal ADDT.
and outputs it to the digital signal processing circuit 8.

Furthermore, the audio signal conversion circuit 30 outputs the digital audio signal signal DADT output from the digital signal processing circuit 8 via the digital-to-analog conversion circuit 32A and the low-pass filter circuit 32B, thereby converting the digital audio signal signal DADT into an analog signal. S. . Convert to 7.

As a result, the digital audio tape recorder 1
In this case, the input audio signal S0 or the digital audio signal RX is monitored during recording, while the reproduced audio signal S reproduced from the magnetic tape 15 is monitored during playback. It is possible to monitor □.

Furthermore, the audio signal conversion circuit 30 receives the composite mute signal MT output from the digital signal processing circuit 8 in the drive circuit 32, and when the composite mute signal MT rises, drives the relay 33 to turn on the switch circuit 34.

As a result, when the composite mute signal MT rises, the audio signal conversion circuit 30 converts the low-pass filter circuit 32 into
The output signal of B is lowered to O level, and the monitor signal and reproduced audio signals S and JT are muted (hereinafter referred to as line mute).

Thus, the reciprocating audio signal S. Since the output line of the UT is directly lowered to the O level, abnormal noise can be effectively avoided and muffled.

As shown in FIG. 3, the digital signal processing circuit 8 is entirely integrated into an integrated circuit, thereby simplifying the overall configuration of the digital audio tape recorder 1.

Further, in the digital signal processing circuit 8, the data input/output circuit 40 receives the control data DCo1a output from the system control circuit 6, and outputs the control data DCON.
? is stored in a predetermined area of the memory circuit 44° via the memory interface circuit 42, thereby controlling the control data D,. The digital signal processing circuit 8 based on N7
It is designed to switch the operation.

The input/output circuit 46 receives an AES/EBU format digital audio signal RX output from an external device of the digital audio tape recorder 1, and outputs a P
A clock signal is extracted by a clock signal extraction circuit having a phase 1 locked 1 loop (LL) circuit configuration.

Further, the input/output circuit 46 separates the audio data DAD from the digital audio signal RX using the clock signal as a reference, and outputs the separated audio data DAD to the digital signal input/output circuit 52.

As a result, the digital audio tape recorder 1
, the input audio signal S is an analog signal.
Instead of IN, a digital audio signal RX in AES/EBU format can be recorded.

At this time, the input/output circuit 46 outputs a mute signal 42 whose signal level rises when the clock signal extraction circuit is out of synchronization. Monitor signal S. The UT is muted.

Further, the input/output circuit 46 includes the digital signal input/output circuit 5
The digital audio signal D0 output from AE
Digital audio signal T in S/EBU format
The reproduced audio signal S is thereby converted into an analog signal. AES/EBU in addition to UT
The digital audio signal TX of this format can be output and monitored.

The digital signal input/output circuit 52 receives control data D, which is output from the memory circuit 44 to the data bus DTmus. N
7 and switches the operation based on the control data D_CONT.

The digital signal input/output circuit 52 selectively inputs the digital audio signal RX or ADDT, and outputs the selected input signal as a monitor signal to the input/output circuit 46 and the audio signal conversion circuit 30. It is possible to monitor digital audio signals.

Furthermore, the digital signal input/output circuit 52 sequentially counts predetermined clock signals and outputs the rotating drum reference signal DRE.
The digital signal processing circuit 8 operates based on the rotating drum reference signal DREF.

Furthermore, at this time, the digital signal input/output circuit 52 blocks the selectively inputted digital audio signal at an interleaving period based on the count value of the counter circuit during recording.

Further, the digital signal input/output circuit 52 sequentially outputs digital audio signals to the memory interface circuit 42 based on the count value of the counter circuit,
Thereby, the digital audio signal is interleaved for each block to generate input audio data.

On the other hand, during playback, the digital signal input/output circuit 52 sequentially outputs predetermined address data and sequentially inputs the playback audio data stored in the memory circuit 44 via the memory interface circuit 42. By sequentially inputting the reproduced audio data based on the count value of , the reproduced audio data is deinterleaved and converted into a digital audio signal, and then outputted to the input/output circuit 46 and the audio signal conversion circuit 30.

Furthermore, during playback, the digital signal input/output circuit 52 outputs mute signals output from the system control circuit 6, the input/output circuit 46, the recording signal generation circuit 60, and the playback signal processing circuit 58. circuit 53
This gives a mute signal to D□, D 3,
A composite mute signal MT is generated by combining the DMAs (FIG. 2).

Further, the digital signal input/output circuit 52 supplies the reproduced audio signal DADT to the AND circuit 54, and obtains the logical product of the inverted signal of the composite mute signal MT output from the inverter circuit 55 and the reproduced audio signal DADT, thereby generating the mute signal. Back to D! %I) M3, Dxa
When any one of them rises, the playback audio signal DADT
mute and output.

In this way, the reproduced audio signal DADT is muted and outputted by the digital signal processing circuit 8, and then line-muted by the digital signal conversion circuit 30 based on the composite mute signal MT, thereby effectively avoiding the occurrence of abnormal noise. to ensure that the sound is muted.

At this time, in the digital signal input/output circuit 52, the mute signal D□ generated in response to the operation of the operator,
By generating the composite mute signal MT based on the mute signal Dtt generated in response to the digital audio signal, when the user operates the mute operator, the audio data cannot be separated from the digital audio signal RX. Then, line muting can be performed, and the reproduced audio signal can be muted as necessary with a simple configuration in which only one composite mute signal MT is output from the digital signal processing circuit 8.

The error detection and correction circuit 56 receives control data DCON? from the memory circuit 44. is loaded at an interleave period, and the operation is switched according to the control data D coMt.

That is, during recording, the error detection and correction circuit 56 sequentially loads the input audio data stored in the memory circuit 44, generates inner codes and outer codes for error detection and correction in units of blocks, and stores them in the memory circuit 44.

On the other hand, during reproduction, the error detection and correction circuit 56 performs error correction processing on the reproduced data D□ stored in the memory circuit 44 using an inner code and an outer code.

At this time, the error detection and correction circuit 56 sequentially outputs predetermined address data and sends the error detection result detected by the reproduction signal processing circuit 58 to the memory circuit 44 along with the reproduction data D□.
, and repeat the error correction process using the error detection result.

The recording signal generation circuit 60 is a digital signal input/output circuit 5
2, the operation is switched according to the control data DcONT, and the operation is stopped during reproduction.

On the other hand, during recording, the recording signal generation circuit 60 sequentially loads the input audio data, inner code, etc. stored in the memory circuit 44 and generates the recording signal 5IItc.

Furthermore, at this time, the recording signal generation circuit 60 generates the control data D.
,. Switch the recording format based on HT and record the LP
mode, the transmission rate is 4.075 (Mbps
), whereas in the SP mode, a recording signal SllEC with a transmission rate of 9.408 [Mbps] is generated, thereby producing digital audio according to the format standardized for the digital audio tape recorder. Record the signal.

Furthermore, when switching the recording format, the recording signal generation circuit 60 outputs a mute signal DN3 whose logic level rises during the switching period to the digital signal input/output circuit 52, thereby causing the monitor signal S to be output during the switching period. tl? line mute to effectively avoid the occurrence of abnormal noises caused by switching recording formats.

Thus, in the digital signal processing circuit 8, the control data DcoN? The recording signal generation circuit 60 independently generates the mute signal DM3 based on
By muting the DT, the configuration of the digital audio recorder 1 can be simplified.

Furthermore, at this time, the digital signal input/output circuit 52 synthesizes a composite mute signal MT based on the mute signal D0, thereby allowing the digital signal processing circuit 8 to
A reproduced audio signal can be reliably muted with a simple configuration that only outputs two composite mute signals MT.

During playback, the clock signal extraction circuit 62 extracts a playback clock signal from the playback signal 5IIF obtained via the recording/playback amplification circuit 64, and outputs the playback clock signal together with the playback signal S□ to the playback signal processing circuit 58. .

The reproduction signal processing circuit 58 receives control data D,. H? On the basis of
After demodulating, the resulting reproduced data D□ is output to the memory circuit 44.

At this time, the reproduction signal processing circuit 58, based on recording information such as a block address added to the audio data,
While storing the reproduced data D□ in the memory circuit 44,
Error detection processing using the 1 code is executed, and the detection result is stored in the memory circuit 44.

The reproduced data D□ demodulated in this way is -1 memory times l.
After being stored in the magnetic tape 1r44, the error is corrected by the error detection and correction circuit 56 and sequentially outputted via the digital signal input/output circuit 52, thereby making it possible to reproduce the digital audio signal recorded on the magnetic tape 15.

Furthermore, the reproduction signal processing circuit 58 detects the sampling frequency of the audio data based on the reproduction data DPI+ of the subcode area, and thereby detects the sampling frequency of the audio data.
Detect recording format.

Furthermore, the reproduction signal processing circuit 58 performs error detection on the sub-data in the sub-code area and the main data area using the parity code added to the sub-data, and converts the error detection result and the error detection result using the C1 code into Based on this, it is determined whether the reproduced signal 5IIF has been reliably reproduced.

That is, when the result of sub-data error detection using a parity code is two or more tracks and less than a predetermined value, it can be determined that a non-recorded portion of the magnetic tape 15 has been reproduced.

Further, when the error detection result using the C1 code is less than a predetermined value, it can be determined that the servo is disturbed during reproduction and the reproduction could not be performed correctly.

Therefore, in this embodiment, when the error detection result of sub-data using the parity code and the error detection result using the C1 code are less than a predetermined value, the signal level of the mute signal DM4 is raised with a delay of a predetermined time.

Further, when the recording format of the magnetic tape 15 is switched between LP mode and SP mode, or when the sampling frequency of reproduced audio data is switched, the signal level of the mute signal D84 is raised with a delay of a predetermined time.

As a result, when the servo is disturbed, the reproduced signal processing circuit 58 mutes the reproduced data in the non-recorded part of the magnetic tape, in the part where the LP and SP modes are switched, and in the part where the sampling frequency is switched.

In reality, if the servo is disturbed, correct reproduction data cannot be reproduced, so the reproduced audio signal S suffers from severe sound quality deterioration. tlT is output.

Furthermore, when switching between LP and SP modes and when switching the sampling frequency, it is necessary to switch the operating reference clock signal of the digital signal processing circuit 8. Therefore, when switching the clock signal,
The clock signal is disrupted and abnormal noise occurs.

Similarly, when retracing the unrecorded portion, the reproduced audio signal S becomes harsh. , JT are output.

Therefore, in such a case, the mute signal D is used.

Raise the signal level of the playback audio signal SoU?
By muting the sound, the usability of the digital audio tape recorder 1 can be improved.

Thus, in the digital signal processing circuit 8, the reproduced signal processing circuit 58 independently detects the unrecorded portion of the magnetic tape based on the recorded information on the magnetic tape and generates the mute signal DH2, and the digital signal processing circuit By muting the reproduced audio data DADT in the digital audio tape recorder 8, the connection between the reproduced signal processing circuit 58 and the system control circuit 6 can be simplified, and the configuration of the digital audio tape recorder 1 can be simplified.

Further, at this time, the digital signal input/output circuit 52 synthesizes a composite mute signal based on the mute signal D□, so that the digital signal processing circuit 8 outputs one composite mute signal MT.
Recurring audio signals can be reliably muted.

In the above configuration, the memory interface circuit 42
, control data input/output circuit 40, digital signal input/output circuit 52, repeat signal processing circuit 58, recording signal generation circuit 60
The error detection and correction circuit 56 loads the control data [)co□ stored in the memory circuit 44 at a predetermined timing, and thereby switches the operation based on the control data DCO1.

That is, during recording, a clock signal is extracted from the AES/EBU format digital audio signal RX input to the input/output circuit 46, and audio data is separated from the digital audio signal RX using the clock signal as a reference.

Accordingly, when selecting and recording the digital audio signal RX, the audio data is the monitor signal S.

At the same time, the signal is output as Ua, and after being divided into blocks by the digital signal input/output circuit 52, it is interleaved and converted into input audio data.

After an error detection and correction code is created for the input audio data in the error detection and correction circuit 56, a recording signal S□ is generated in the recording signal generation circuit 60 in the subsequent interleave period.

is converted to

The recording signal S□0 is sequentially transmitted to the magnetic heads 28A and 28.
B, and thus the AES/E
A BU format digital audio signal RX can be recorded.

At this time, in the input/output circuit 46, when the clock signal extraction circuit loses synchronization and the audio data cannot be separated, the logic level of the mute signal D0 rises, and in response, the logic level of the composite mute signal MT increases. stand up.

This allows the monitor digital audio signal DADT
while muting the playback audio signal S. U? can be line muted, effectively avoiding the occurrence of abnormal noise and muting the reproduced audio signal 5oUt.

In contrast, the input audio signal 8 is an analog signal.
1.4 is an audio signal conversion circuit that converts digital signal A.
After being converted to DDT, the digital signal input/output circuit 52
It is converted into a recording signal S□0 in the same way as the digital audio signal RX.

At this time, when the user operates the mute operator, the logic level of the mute signal DMI rises, and in response, the logic level of the composite mute signal MT rises, muting the playback audio data DADT and muting the playback audio signal S. , line mute JT.

On the other hand, when the recording format is switched, the logic level of the mute signal D rises during the period during which the recording format is switched, and in response, the logic level of the composite mute signal MT rises.

Thereby, during the period, it is possible to effectively avoid the occurrence of abnormal noise and to mute the monitor audio signal.

The reproduced clock signal 5IIF is extracted by the clock signal extraction circuit 62, demodulated by the reproduced signal processing circuit 58, and reproduced data DPI is stored in the memory circuit 44.

The reproduced data D□ stored in the memory circuit 44 is outputted via the digital signal input/output circuit 52 after error detection and correction.

At this time, in the playback signal processing diagram 858, if the servo is disturbed, if a non-recorded part of the magnetic tape, a part where the LP and SP modes are switched, or a part where the sampling frequency of audio data is switched is detected, it will be detected for a specified period of time. The logic level of the mute signal D□ rises with a delay.

As a result, the servo was disturbed during the period when the digital signal processing circuit 8 switched its operation at the LP and SP mode switching section and the sampling frequency switching section, and during the period when the non-recorded part of the magnetic tape was reproduced. In this case, the logic level of the composite mute signal MT rises, and the reproduction audio signal can be muted while effectively avoiding the occurrence of abnormal noise.

According to the above configuration, each circuit block of the digital signal processing circuit 8 outputs a mute signal as necessary, and also synthesizes the mute signals output from each circuit block to generate a composite mute signal. By outputting the mute signal from the digital signal processing circuit 8,
Line muting can be performed based on the composite mute signal, and the generation of abnormal noise can be effectively avoided and noise can be reliably muted with a simple configuration.

(C2) Other Embodiments In the above-described embodiments, a case has been described in which a composite mute signal is generated based on the error detection result of the reproduced signal processing circuit 58, but the present invention is not limited to this. A composite mute signal may be generated based on the error detection and correction results of the correction circuit 56.

Further, in the above-described embodiment, a case has been described in which a composite mute signal is generated based on recorded information and error detection results during playback, but the present invention is not limited to this, and based on control data, for example, a recording mode It can be widely applied to mute the reproduced signal etc. as necessary, such as when switching from mode to reproduction mode.

Further, in the above-described embodiments, a case has been described in which line muting is performed using a composite mute signal, but the present invention is not limited to this, and it may be output as a monitor signal when muting playback data.

Furthermore, in the above-described embodiments, a case has been described in which a composite mute signal is generated based on mute signals output from a recording signal generation circuit, a reproduction signal processing circuit, an input/output circuit, and a system control circuit. The present invention is not limited to this, but can be widely applied to cases in which mute signals output from various circuit blocks are synthesized to generate a composite mute signal as necessary.

Furthermore, in the above embodiment, a case was described in which an audio signal consisting of an AES/EBU format digital audio signal and an analog signal was recorded.
The present invention is not limited to this, and can be applied to various cases such as recording and reproducing only digital audio signals in AES/EBU format, recording and reproducing only analog audio signals, and recording and reproducing other digital audio signals. It can be widely applied to recording and reproducing signals.

Further, in the above-described embodiments, the present invention is applied to a digital audio tape recorder, but the present invention is not limited to this, and can be applied to an external storage device of an arithmetic processing device. Data input and output may be recorded and reproduced.

Furthermore, the invention is not limited to magnetic recording and reproducing devices, but can be widely applied to recording-only and reproducing-only digital audio tape recorders, as well as magnetic recording devices that record and reproduce various data other than audio signals.

H Effects of the Invention As described above, according to the present invention, a mute signal is generated in each circuit block of a digital signal processing circuit based on control data, recorded information, etc., and the generated mute signals are synthesized and output. Accordingly, it is possible to obtain a digital signal processing circuit that can effectively avoid the occurrence of abnormal noise and reliably silence it with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a digital audio tape recorder according to an embodiment of the present invention, FIG. 2 is a block diagram showing a digital signal processing circuit, and FIG. 3 is a block diagram showing an input/output circuit and a digital signal input/output circuit. It is. 1...Digital audio tape recorder,
8...Digital signal processing circuit, 46...
...Input/output circuit, 52...Digital signal input/output circuit, 53...OR circuit, 54...
AND circuit, 55... Inverter circuit.

Claims (2)

[Claims] (1) A memory circuit for storing playback audio data; and playback signal processing for demodulating the playback signal to obtain the playback audio data and recording information, and storing the playback audio data in the memory circuit based on the recording information. an error detection and correction circuit that performs error detection and correction processing on the reproduced audio data based on the recorded information; and an error detection and correction circuit that converts the reproduced audio data stored in the memory circuit into a reproduced digital audio signal based on the recorded information. a data output circuit for conversion; a control circuit for switching the operations of the reproduced signal processing circuit, the error detection and correction circuit, and the data output circuit based on predetermined control data; and a mute signal for combining and transmitting a composite mute signal. a synthesis circuit; and a reproduction data mute circuit that mutes and transmits the reproduction digital audio signal based on the composite mute signal, the reproduction signal processing circuit, the error detection and correction circuit, the data output circuit, and/or the control. The circuit generates a mute signal based on the control data, the recorded information, and/or the processing result of the error detection and correction process, and the mute signal synthesis circuit includes the reproduced signal processing circuit,
A digital signal processing circuit characterized in that the mute signals generated by the error detection and correction circuit, the data output circuit, and/or the control circuit are synthesized to generate the composite mute signal. (2) a memory circuit that stores input audio data and error detection and correction codes; and a memory circuit that converts the input digital audio signal into input audio data and stores it in the memory circuit based on the control data; a data input/output circuit that outputs a digital audio signal for monitoring; and a data input/output circuit that generates the error detection and correction code for the input audio data stored in the memory circuit based on the control data; an error detection and correction circuit that stores in the memory circuit; a recording signal generation circuit that converts the input audio data and the error detection and correction code stored in the memory circuit into a recording signal based on the control data; a mute signal synthesis circuit that synthesizes and sends out a synthesized mute signal; and a data mute circuit that mutes and sends out the monitor digital audio signal based on the synthesized mute signal; the data input/output circuit; and the error detection circuit. The correction circuit and/or the recording signal generation circuit generates a mute signal based on the control data and/or the input digital audio signal, and the mute signal synthesis circuit includes the data input/output circuit,
A digital signal processing circuit characterized in that the mute signals generated by the error detection and correction circuit and/or the recording signal generation circuit are synthesized to generate the composite mute signal.