JPH03203357A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve material utility and effectively manufacture a semiconductor device, by separating a multilayer printed board, as main constitution material, from a large board by dicing, and using the separated board. CONSTITUTION:A semiconductor device is constituted of a semiconductor chip 1, a thermal diffusion plate 2, a wiring board 3, a lead frame 4, through holes 10, blind viaholes 14, and triazine plates 22-24 being insulating boards. When said semiconductor device is manufactured, glass fiber, resin boards like triazine are used, and a copper foil and a printed wiring board plated with copper are used for a package main body. An auxiliary board serves as a chip mounting board of a wiring board wherein copper, aluminum, etc., are used, and the chip is directly buried in a hole formed in the chip mounting board. The multilayer interconnection board as the main material in this constitution is continuously formed in advance, and used by cutting in the case of need.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a semiconductor device, more specifically a quad flat package (QFP) in which external leads extend from the sides.
), Small Outline Package (SOP, 5OJ
), leaded chip carriers (LDCCs), etc., and particularly relates to multi-bin, high-speed signal, high heat dissipation, and low-cost integrated circuit packages such as ASICs (application-optimized ICs) and microcomputers.

(Prior Art and its Technical Issues) In recent years, with the increase in the scale of integrated circuits, the number of signals has increased significantly, and it has become necessary to satisfy the required characteristics of high-speed signal processing and high heat dissipation. On the other hand, it is necessary to meet these demands at low cost, and the pitch of the external lead-in/out lead is 0.
．． QFP, 5OPSol leaded chip carrier, etc., in which the lead frame is molded with a plastic resin such as epoxy, are considered to be particularly effective as surface mount packages.

0.5 lead pitch is said to be the limit of surface mount soldering (Nikkei Electronics, 1988)
December issue P145-158).

Assuming a pitch of 0,5 T1m, it is necessary to increase the number of pins and increase the side length of the package body, resulting in a large package. This increases the length of wiring within the package, which hinders high-speed signal processing.

For integrated circuits that need to be processed at higher speeds than in the past, packaging with degraded electrical characteristics poses a major problem. On the other hand, the power consumption of integrated circuits has gone from less than IW to 2 to 5 W class, and even 6 to 25 W class ones are being developed.
4-1 (1.35 mm, OJ-), but progress in increasing the number of pins is also rapid, and it is clear that high-speed signal processing and high-efficiency heat dissipation are major challenges for packages.

For this reason, various countermeasures have been considered in recent years.

U, S, P, 468 (In the specification of No. 1613, there is a proposal to provide a ground plane under the lead frame wiring layer and create a multilayer lead structure in order to prevent noise generation due to fluctuations in the ground potential within the package wiring. There is.

Further, U, S, P, 4113512 [1] proposes a three-layer lead frame structure in which a power plane is added in order to improve not only the ground potential but also the fluctuation of the power supply potential.

Regarding the heat dissipation structure, Japanese Patent Laid-Open Nos. 63-73541 and 59-28364 propose a two-layer structure in which a heat block is inserted under the lead frame. This transformation is shown in Nikkei Microdevice Magazine, November 1988 issue, P74.
75, which points out that it is possible to dissipate heat of 2 to 3.5 W without special consideration after mounting on a printed circuit board.

There is another problem when increasing the number of pins. The electrodes of a semiconductor chip are either taken out from the periphery or the chip size is small, and if you try to install an electrode with many pins, the pitch between the electrodes becomes narrow, and the pitch between the electrodes becomes narrow, which is the limit pitch for connecting with ordinary gold wire hole wires (130 μm pitch for φ32 μm). become smaller.

Furthermore, the pitch between the tips of the inner leads facing the tip electrodes must also be reduced. For the former, bonding using a tape carrier has been proposed. For example, JP-A-60-241241 and JP-A-61-95539 are examples of this, and JP-A-61-242051 is a proposal in which a tape carrier also serves as an external lead-in/output lead. Regarding the latter, a distantly related example of microfabrication is seen in JP-A-58-122765, in which the internal wiring of the lead frame is passed through a metalized insulating substrate.

There is an example in which a glass epoxy printed circuit board is used in a multilayer structure, as shown in FIGS. 1 and 2 of Nikkei Microdevice Magazine, December 1989 issue P, 42. Printed circuit boards can easily have a multilayer structure, have a low dielectric constant and are suitable for high-speed wiring, and have a copper core that satisfies heat dissipation.However, I have no idea how to attach an external IJ-board frame. is suggesting. That is, the lead frame is sandwiched between glass epoxy resins, electrical conduction is established between the lead frame and the lead frame through a through hole, and then the glass epoxy printed circuit board of the lead frame portion is peeled off to form an integrated structure. The disadvantages are that the entire area of the glass epoxy printed circuit board cannot be used, that alignment with the lead frame is difficult, resulting in high costs, and that the degree of freedom in multilayer configuration is limited due to the insertion of the lead frame.

All of the known examples introduced above are based on molded packages.

Resin molded packages can achieve low costs due to their simple structure, in which the chip is mounted on a single-layer lead frame and completed through a molding process. However, as the number of pins increases, the distortion of the resin mold increases due to the larger size, and many improvements are required in the structure to absorb the distortion, the selection of resin, and the optimization of the process, resulting in high costs. Furthermore, the multi-layered frame and heat dissipation structure described above further complicates this problem and increases the cost of creating the structure. It can be said that the simplicity of the construction process, which was an advantage, is no longer present.

As a countermeasure to this problem, various resin botting type structures have been devised. For example, lMC1986P+ocepdi
ngs, KOhn May 28-30. P1
86-193) Electronic Materials, September 1988 issue F59
~64, Nikkei Microdevice September 1989 issue P68
-70 and Japanese Patent Application Laid-Open No. 55-95348, both of which have the potential to easily produce a multilayer structure, but each has drawbacks. An example of lMC1986 is a ceramic substrate, which generally has a dielectric constant more than twice as high as resin, making it unsuitable as a high-speed wiring structure material. Also, in order to have a heat dissipation structure, it is necessary to use expensive silicon carbide or aluminum nitride.

Electronic materials, in the example of 1988.9, the chip is attached to a material based on a printed circuit board, and it has many advantages, such as easy multilayering and a heat dissipation structure that only requires the preparation of a printed circuit board with a copper heat sink. However, the provision of fine-pitch external lead-in/out leads is a technologically undeveloped field and is used in areas with relatively low pin counts in the form of lead connections to electrodes with large areas. Nikkei Microdevice 1989.4. The example P68-7 [) is based on a tape carrier and has a potted type structure suitable for multi-bin use as a tape carrier package. However, multilayering in tape carrier technology (TAB) has not been technically established. A TAB with a 200-pin output input has the same unit price as a lead frame, but it is thought that the cost will be three times as much for two layers and five times as much for three layers, and the unestablished technology is the cause of the high cost. . As mentioned above, there are various drawbacks to the miniaturization of the wiring pitch around the chip.
No good package has been proposed for increasing the number of pins, increasing speed, and increasing power consumption.

Furthermore, a circuit board having an integral structure of a lead frame and a multilayer wiring board is proposed in Nikkei Microdevice, December 1989 issue P, 34-36; There are disadvantages in that the material removal (yield) of the lead frame part is wasted, and the laborious work process of peeling off unnecessary substrates is required, resulting in high manufacturing costs.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems and to provide a semiconductor device having multi-pin input/output terminals, capable of high-speed signal propagation, and having high heat dissipation ability at a low cost. It is something.

(Means for Solving the Problems) The semiconductor device of the present invention includes a chip mounting board on which one or more semiconductors are mounted and housed at a predetermined position on the inner surface, and a chip mounting board that is electrically connected to a semiconductor circuit and connected to an external terminal. The basic structure is composed of a resin multilayer wiring board to be led out, and external connection leads in the form of beam leads or tape carriers extending on the side surface of the wiring board and electrically connected to the board. The joint between the external connection lead and the external connection lead is made by welding or brazing, and the joint is fixed with an organic adhesive or an organic reinforcing plate so as not to be directly affected by external force.

The resin multilayer wiring board is manufactured by a printed wiring board manufacturing process.

Glass fiber or cloth, silica glass fiber or cloth,
Uses a resin substrate made of epoxy, triazine or maleimide, polyimide, fluororesin, etc. modified with epoxy, aramid, silicone, polyimide, maleimide, etc., reinforced with Gevlar fiber (aramid) or cloth, etc., and coated with copper foil or copper plating or copper. A printed wiring board consisting of a physical covering layer is used as the body of this package. The wiring board also includes a structure in which copper or copper alloy, aluminum or aluminum alloy is attached to the main body as an auxiliary board in order to impart heat dissipation properties.In this case, the auxiliary board is the chip mounting board of the wiring board. The wiring board also serves as a board, with a hole slightly larger than the chip's outer diameter being drilled, and the chip is directly attached to the mounting board.

(Example) An example of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a semiconductor device of the present invention, and FIG. 2 is a cross-sectional view of a resin multilayer wiring board 3.

First, the structure of the wiring board 3 will be explained while showing an example of a preferred method for manufacturing the wiring board 3.

A double-sided copper-clad glass fiber-containing triazine plate 22 and single-sided copper-clad homogeneous plates 23 and 24 are prepared. The board 23 is a power supply layer on the back side (all cross-sectional views are drawn with the back side facing up) after processing the blind via holes 14 and 15, electroless copper plating, and electrolytic copper plating to make the inner surface of the peer holes conductive. 16 and the inner power supply layer 17 are etched in a predetermined pattern. Next, the signal layer j8 and the surface pattern of the plates 23 and 24 are individually etched, and the square holes 2fl'' and 2G'' are formed by router machining or NC machining such as a laser to form the cavity 20 for chip mounting.
' is opened. At the same time, square holes slightly larger than 20" and 20" are drilled in the prepregs corresponding to the plates 23 and 24, respectively, and the processed plates 22, 23, 24 and the prepregs are aligned, then pressed and laminated by heating. . It goes without saying that all of the above processing is performed on a large board in which the wiring boards 3 are arranged in multiple rows. The wiring board 3 is then processed with through holes 10 and subjected to an activation process for electroless plating. Subsequently, a photosensitive film resist 25 is applied to the entire upper and lower surfaces to serve as a plating mask. After exposure and development, only the through holes and their surrounding land areas are opened, and after electroless copper plating, electrolytic copper plating is applied through the back side copper power layer.

Needless to say, the plated conductive pattern 26 is installed from the through hole 10, and the entire large plate becomes one electrode (FIG. 6). After that, after peeling off the film resist 25 and printing a solder resist 27, nickel plating and gold plating are applied to the entire exposed metal surface, and the plated conductive wire 28
is removed by router machining or the like, and a square hole 20' is made by router machining or the like to form the cavity 20. still,
The pier hole 15 is made into a half-moon shape by router processing, and the third
The figure is shown in perspective view. The pier hole 14 has a blind structure even in this process. Subsequently, a solder resist 29 is applied if necessary. Multilayer wiring board 3
As the final step, dicing is performed along the lines shown at 21, and the large board is divided into individual multilayer wiring boards 3. The divided board 3 has high lead solder balls 33 placed on the inner part of the leads 4 as shown in FIG. 4 in advance, and after aligning them with the through-holes of the board 3, is reflowed and soldered as shown in FIG. Solder pillar 11 is placed inside the through hole lO as shown in the figure.
At the same time, the lead tip hole 12, which had been processed in advance, is also filled with solder to obtain a strong bond.

Note that if the lead frame 4 is previously plated with Fura Soche gold plating, the solder will be well wetted.

A preferred method for placing solder balls is a method using a gold wire ball bonder, which is often used for connecting semiconductor elements, such as the method disclosed in Japanese Patent Application Laid-open No. 63-301535. 1986-12
No. 2133, No. 60-89951, No. 61-2332
No. 9, No. 63-104431, No. 511-17583
No. 8, No. 60-134444, No. 59-20875, No. 62-281435, etc. propose a method of attaching ball-shaped bumps by the same means, but this method is also sufficient. Showa 6 (1-86840
Of course, you may use the following. All of the above-mentioned known examples relate to chip/tube electrodes, and it goes without saying that the package is new.

It is actually difficult to achieve sufficient connection strength of the lead frame by simply connecting the lead frame 4 to the wiring board 3 with solder or brazing material because the connection is made over a minute area.

Therefore, the plastic reinforcing material 13 is finally covered. The reinforcing material 13 can be made of solder resist printing (epoxy) commonly used for printed circuit boards, epoxy for semiconductor molds made into square ring-shaped tablets (B-stage resin), heated and fluidized, or coated with epoxy for potting, or epoxy for potting. coated with silicone rubber. Also, a square ring-shaped prepreg without glass fiber (B stage resin) or the like may be used, and a structure to which a reinforcing plate is attached may also be used.

The package is completed as described above, but a slide carrier 30 can be attached if necessary to prevent deformation of the outer peripheral tip of the lead frame. Of course, it is also possible to cut the leads before attaching the slide carrier and apply a burn-in probe for electrical testing through the test hole 31 to make the leads electrically independent.

Also, although the explanation was given using the lead frame, the tape carrier (
It goes without saying that TAB) may be used instead of the lead frame.

In a semiconductor chip that requires a heat dissipation structure, a heat diffusion plate 2 is bonded with an organic adhesive 7. If the thermal expansion coefficients of the multilayer wiring board and the thermal diffusion plate do not match, use a silicone rubber with a small elastic modulus, such as TOI/Silicone CY52-223, as the adhesive 7.
However, when the expansion coefficient is matched, epoxy, such as Nagashio Ciba T524/R-200, is used. Heat spreader 2
As low cost copper or copper alloy, aluminum or aluminum alloy, copper impregnated molybdenum, or tungsten,
Clad material (Cu/Invar/Cu, Co/Mo
/Cu, etc.), aluminum nitride, silicon carbide, etc. It is better to have as large a heat dissipation area as possible for the heat diffusion plate, and it may be larger than the multilayer wiring board 3. Further, in order to avoid swelling of the solder or brazing material 11 in the through hole 10, it may be small. The point is to think within the scope of the necessity of heat dissipation, but if it is not necessary, the insulation layer 22 of the multilayer wiring board 3 may be formed into a closed cavity 20 without processing 20゛, or an additional layer may be added to form the insulation layer 22. A fourth layer of the same material may be added to the back surface.

Although the structure of the package is shown as a multilayer wiring board with 1i3 layers of insulation, it may have more layers or two layers, and although only one cavity 20 is shown, it may have two or more cavities. . In this case, since it is a multi-chip module and inter-chip wiring is performed on the multilayer wiring board 3, the blind via hole 14 or 15 and the through hole 10 are
It is thought that many other parts will be provided.

Next, a method for mounting the semiconductor chip 1 will be explained. When the thermal expansion plate 3 has a thermal expansion mismatch with the chip such as copper, the chip is attached to the cavity 20 using an adhesive 6 with a small elastic modulus.
Shin-Etsu Silicone's silicone rubber K to be bonded to the part]
R9022, low modulus epoxy, etc. are suitable as adhesives. When matching conditions are met, an adhesive 6 with good thermal conductivity such as Au-8i or solder can be used. Subsequently, the electrodes on the chip 1 and the electrodes exposed at each stage of the cavity 20 of the multilayer wiring board 3 are connected by wire bonding or TAB, and then epoxy potting or silicone gel potting is performed to form a sealing structure 8. complete. Since silicone gel is hard, the lid 5 is sealed with an adhesive 9 for mechanical protection. For this lid, it is preferable to use a hard epoxy adhesive when the thermal expansion is matched with the multilayer wiring board 3, but when the thermal expansion is not matched, silicone rubber or the like is used. Thereafter, the leads 4 are formed as shown in FIG. 1 and surface mounted on a printed wiring board. Of course, the leads 4 may be pre-soldered before being joined to the multilayer wiring board 3, or may be pre-soldered after the chip 1 is assembled and sealed. In the latter case, it goes without saying that if the joining solder 11 is high lead solder or Au-3n based, the joint 11 will not re-melt at the working temperature of general solder (eutectic Pb-5n solder). .

It goes without saying that as a heat dissipation structure, a heat dissipation fin or a water-cooled or air-cooled heat sink can be attached to the upper part of the heat diffusion plate 2 as required.

(Effects of the Invention) According to the present invention, the above-mentioned Nikkei Microdevice 198
The manufacturing cost can be lowered compared to the device proposed in December 1999 issue P, 34-36.

That is, in the present invention, since the multilayer wiring board, which is the main constituent material, is separated from the large board by dicing, material removal is easy and efficient manufacturing is possible. Both lead frames and multilayer wiring boards have become more complex as the number of pins increases and speed increases, and when they are integrated using hard processing techniques, the manufacturing yield (good product rate) of each has to be multiplied and the final yield decreases. Separate production makes the yield independent, resulting in a significant cost reduction. The cost of connection and the associated reliability are disadvantages of the present invention, but the technology level of metal bonding has automatically improved with the advancement of TAB technology, and automated methods are now available, so it has a high index. It can be manufactured using the following methods, and there are no major drawbacks in terms of reliability or cost.

The multilayer wiring board is an organic material and has a lower dielectric constant than ceramic, making it an advantageous material for high-speed signal transmission. Furthermore, since a copper metal conductor is used for this wiring, the resistance is low, and these two points provide a high-speed signal transmission path sufficient for increasing the size of the package due to the increase in the number of pins. Furthermore, it has been found that since a free multilayer structure can be created, it is possible to easily provide a structure with low inductance, capacitance, and resistance characteristics, which can also perform impedance matching, high-speed transmission, and noise reduction.

The structure of the thermal diffusion plate can be easily installed, and it is possible to provide a package that can be sufficiently mounted even for high-output semiconductors. This is the Nikkei Micro Device 198 mentioned above.
9. The proposal in December issue P, 34-36 is to mold the whole thing, but the actual purpose is to make an outer wall as a structure together with the multilayer wiring board, so the entire one side of the heat diffusion plate is used as a heat radiation surface. It is highly efficient. Furthermore, the cost can be reduced compared to the idea of molding the entire structure.

Further, by using an organic adhesive or a reinforcing plate at the joint between the wiring board and the external connection lead, the joint strength can be improved and durability can be increased.

Therefore, by taking advantage of the characteristics of high-speed, high-power semiconductors, it is possible to provide a package structure at low cost.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the semiconductor device of the present invention, FIG. 2 is a sectional view of a multilayer wiring board, and FIG. 3 is a perspective view of a cavity portion thereof.
FIG. 4 is an end perspective view of the external connection lead, FIG. 5 is a sectional view of the wiring board to which the external connection lead is connected, and FIG. 6 is a perspective view showing the conduction pattern of the through hole. In the figure, 1... semiconductor chip, 2... thermal diffusion plate, 3...
Wiring board, 4...Lead frame 10...Through hole, 13...Reinforcement material (4...Blind via all, 22, 23.24...j.Reasin board (insulating board) 1st
Figure 2 Figure 3 Patent applicant: Chichibufuji Co., Ltd. Agent Masana Jyuyo

Claims (6)

[Claims] (1) A chip mounting board that mounts and stores one or more semiconductor chips at a predetermined position on its inner surface, a resin multilayer wiring board that electrically connects to the semiconductor circuit and leads to external terminals, and and external connection leads in the form of beam leads or tape carriers, which are electrically connected to each other by welding or brazing, and are not directly affected by external forces. A semiconductor device characterized in that it is bonded and fixed with an organic adhesive or an organic reinforcing plate. (2) The semiconductor device according to claim 1, wherein the chip mounting substrate is made of a material with good heat dissipation such as copper. (3) The chip mounting board and the wiring board have an integral composite structure, and the composite is made of fiber-reinforced epoxy, triazine, maleimide, polyimide, fluororesin, aramid, etc.
4. The semiconductor device according to claim 1, wherein the semiconductor device is a printed wiring board formed of modified resin such as epoxy resin and copper wiring. (4) The joints between the wiring board and the external connection leads are arranged on the same plane of the board surface, and the wiring board side extending from the joint has a multilayer wiring structure via through holes or blind via holes. However, the external connection leads are single-layer or multi-layer, and the joints with the wiring board are arranged in a single row or in multiple rows on the same plane, and the structure for attaching them to the circuit board at the tip of the outer periphery is also single-layer on the same plane. 4. The semiconductor device according to claim 1, which has a row or multi-row surface mounting structure. (5) The semiconductor device according to claim 1, wherein the organic adhesive is a high lead solder or an Au-Sn alloy. (6) The semiconductor device according to any one of claims 1 to 5, wherein a through hole is provided in the bonding portion of the substrate at the bonding portion between the wiring board and the external connection lead.