JPH03201736A - Digital modulation signal demodulator - Google Patents

Abstract

PURPOSE:To improve the transmission quality by providing a control means receiving a phase difference signal and sending a control signal to reduce a symbol phase difference of the signal relating to a reception path before selective diversity reception processing to a variable delay circuit. CONSTITUTION:When a delay BB signal Sm is delayed, a phase comparator circuit 28 and an averaging circuit 30 sends a control signal So decreasing the delay of a 1st variable delay circuit 26a and sends a control signal Sp increasing the delay of a 2nd variable delay circuit 26b. Thus, a symbol phase difference between the delay BB signals Sm, Sn by the closed loop control using the control signals So, Sp to cause equilibrium, that is, to make the phase difference zero. Thus, the symbol phase of the delay BB signals Sm, sn is not jumped at each switching of a switch circuit 22, the phase of an eye aperture is not jumped and a demodulation signal Sr decreasing an error rate characteristic effectively is obtained to improve the transmission quality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digitally modulated signal demodulator that performs selection or combination diversity reception processing. The symbol phase error between the branch and 〉 is corrected,
The present invention also relates to a digital modulation signal demodulation device in which selection or combination diversity reception processing after detection is suitably performed.

[Prior Art] FIG. 3 shows an example of the configuration of a conventional digital modulation signal demodulation device that performs selective ubiquitous reception processing after detecting a digital modulation signal supplied from each branch.

In this example, digital modulated radio waves transmitted from the same transmission source (not shown) are received by branches A and B, and the digital modulated signals Sa and Sb supplied from the branches are sent to the first and second detection circuits, respectively. (2) It is simultaneously supplied to 2a, 12b and the first and second reception level detection circuits 16a, 16b.

Then, the baseband signals (hereinafter referred to as BB multiplied signals) derived from the first and second detection circuits 12a112b are passed through the first and second low-pass filters (LPF) 1.
4a and 14b remove noise, unnecessary harmonic components, etc., and supply the resultant signal to the switch circuit 22.

Furthermore, first and second reception level detection circuits 16a,
Voltage signals indicating the levels of the digital modulation signals Sa and sb are detected from the signal generator 16b and supplied to the comparison circuit 20, respectively.

The comparison circuit 20 compares the values of the voltage signals, and when the output voltage of the first reception level detection circuit 16a is large,
A switch circuit control signal S for the switch circuit 22 to derive the output of the first LPF or switch the reverse.
Send d.

In this way, so-called selection diversity reception processing is performed in which the digital modulated signals Sa and Sb supplied from the branches A and B select the signal with the highest signal strength, and the BB double signal demodulation circuit 24 obtained here The demodulated signal Sc is derived from the demodulated signal Sc.

Therefore, the demodulated signal Se is obtained from the BB multiplied signal of the branch where the received signal (human sensation) strength is high, and the transmission quality is improved.

[Problems to be Solved by the Invention] However, the digital modulation signal demodulation device according to the conventional example described above does not have a function of correcting an error when a symbol phase error exists between branches. For this reason, the BB double signal symbol phase jumps every time a branch is selected, that is, every time the switch circuit is switched, that is, the eye opening point phase jumps.
It has the disadvantage of deteriorating error rate characteristics.

Furthermore, in the case of combining diversity, code amount interference occurs and error rate characteristics deteriorate.

The present invention has been made in view of the above points, and its objects are to improve the average S/N ratio of the BB multiplied signal input to the demodulation circuit, and to improve the symbol phase when switching the BB multiplied signal obtained from the branch. It is an object of the present invention to provide a digital modulation signal demodulation device that does not change abruptly or cause code amount interference during synthesis, improves error rate characteristics in demodulation processing, and has excellent transmission quality as a result.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the digital modulation signal demodulation device of the present invention includes a reception level detection circuit that detects the reception signal level in each of a plurality of reception paths and a reception signal detection circuit that detects the reception signal. A digital modulation signal demodulator that includes a detection circuit and performs selective diversity reception processing after detection includes phase comparison means that detects a symbol phase error in each reception path and sends out a phase difference signal, and selective diversity reception processing. variable delay means arranged on at least one of the previous reception paths and for delaying the input signal based on the supplied control signal; A control means for sending the control signal to a variable delay circuit in order to reduce a symbol phase difference of signals related to a reception path.

[Operation] In the above configuration, after the symbol phase difference between the BB multiplied signals before selection in the selection or combination diversity reception process is effectively reduced, and the BB multiplied signals with a high S/N ratio are selected or combined, Demodulated signal processing is performed.

[Embodiment] Next, an embodiment of the digital modulation signal demodulation device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the overall configuration of the first embodiment, and FIG. 2 is a block diagram showing the overall configuration of the second embodiment.

In order to avoid clutter in the drawings and text, components that are the same as those in the conventional example are designated by common reference numerals, and redundant explanation thereof will be omitted.

A first example will be described.

First, the configuration will be explained. In the example shown in FIG. 1, digital modulation signals Sa and Sb are supplied from a branch ASB to first and second detection circuits 12 which derive a BB multiplied signal.
a, 12b, and first and second LPFs 14a, 14b that derive a BB signal 5eSSf from which BB multiplied signal noise, unnecessary harmonic components, etc. have been removed. At the same time, first and second reception level detection circuits 16a, 16b are supplied with digital modulation signals Sa, Sb and derive voltage signals Sg, Sh indicating respective levels;
The comparison circuit 20 is supplied with Sh and derives a switching control signal Si.

Furthermore, the BB signals Se and Sf are supplied and a delayed BB multiplied signal m corresponding to the input control signal 5oSSp is supplied.
, Sn
, 26b and the delayed BB times signal m, S derived therefrom.
A switch circuit 22 to which n is supplied and a delayed BB multiplied signal m
.

A phase comparison circuit 28 for comparing the phases of Sn is provided. Further, an averaging circuit 30 such as an LPF for averaging the values of the signals derived from the phase comparison circuit 28 and a delayed BB multiplied signal m5S selected by the switch circuit 22 are provided.
The demodulation circuit 24 is provided with a demodulation circuit 24 that is supplied with any one of the n signals and derives a demodulation signal Sr that is modulation information.

Next, the operation in the above configuration will be explained.

The supplied digital modulated signals 5aSSb are simultaneously supplied to first and second detection circuits 12a, 12b and reception level detection circuits 16a, 16b, respectively. Then, the BB multiplied signals derived from the first and second detection circuits 12a and 12b are first and second low-pass filters (LPFs), respectively.
BB signals Se and Sf are inputted to 14a and 14b, and noise, unnecessary harmonic components, etc. are removed. continue,
The signals are supplied to first and second variable delay circuits 26a and 26b, respectively.

Furthermore, first and second reception level detection circuits 16a,
Voltage signals Sg and Sh indicating the levels of the digital modulation signals Sa and sb are detected from 16b and supplied to a comparison circuit 20, where a switching control signal Si is derived by comparing the values of the voltage signals Sg and Sh. In this case, the first and second
The reception level detection circuits 16a and 16b do not follow envelope fluctuations caused by modulation, and the voltage signal 5g5Sh is a voltage proportional to the envelope level of the digital modulation signals 3a and Sb.

The switching control signal Si becomes an H (high) level when the voltage signal Sg is larger than the voltage signal sh, and becomes an L (low) level when the voltage signal Sg is larger than the voltage signal sh.

The switching control signal Si is the selection contact 22C of the switch circuit 22.
is supplied to drive the

Next, the BB signals Se and Sf are supplied to the first and second variable delay circuits 26a and 26b, respectively, and the delayed delay B
The B-multiple signals m and Sn are the selected contacts 22 of the switch circuit 22
a, 22b and the phase comparator circuit 28. and,
The phase difference between the delayed BB multiplied signals m and Sn is detected by the phase comparison circuit 28, and the control signal 5O1Sp, which has been subjected to averaging processing such as integration in the averaging circuit 30, is output to the first and second variable signals, respectively. The signal is input to the delay circuit 26a126b.

Here, when the delayed BB multiplied signal m is delayed, the phase comparator circuit 28 and the averaging circuit 30 send out a control signal SO that reduces the delay amount of the first variable delay circuit 26a, and A control signal Sp that increases the amount of delay of 26b is sent. In this way, the control signals So, S
The delayed BB signals Sm, Sn
The symbol phase difference between them decreases and becomes an equilibrium state, that is, the phase difference becomes zero.

In this case, the switching control signal S derived from the comparison circuit 20
When the voltage signal Sg is larger than the voltage signal sh, i becomes H (high) level, and vice versa, it becomes L (low) level.
level. Here, when the voltage signal Sg has a large value, the selection contact 22C of the switch circuit 22 becomes the selected contact 22C.
It is driven to be connected to H. In addition, when the voltage signal sh has a large value, the selection contact 22C of the switch circuit 22
is driven to be connected to the selected contact 22b.

As a result, one of the delayed BB multiplied signals m and Sn of a large level is always selected and input to the demodulation circuit 24,
So-called selective ubiquity reception processing is performed.

Therefore, the average S/N ratio of the BB-time signal delayed BB-time signal m, 5n-) input to the demodulation circuit 24 is improved. Furthermore, the symbol phases of the delayed BB multiplied signals m and Sn do not jump each time branches A and B are selected, that is, each time the switch circuit 22 switches, and the eye aperture phase does not jump, so that the error rate characteristics are effectively improved. A demodulated signal Sr that is reduced is obtained, and the transmission quality is improved.

Next, a second embodiment is shown in FIG. As can be easily understood from the figure, this example consists of variable delay circuits (A) and (B).
32a and 32b are the first and second detection circuits 12a1
This is the one provided before 12b.

Digital modulation signals Sa and Sb are transmitted through variable delay circuits (A) and (
B) After being supplied to 32a and 32b, the signal is supplied to first and second detection circuits 12a and 12b and first and second reception level detection circuits 16a and 16b. Note that the other configurations, operations, and effects are the same as those of the first embodiment, and detailed explanation thereof will be omitted.

In the first and second embodiments described above, selection diversity reception processing is performed in which signals are selected after detection.
It is not limited to this. The present invention also includes combining diversity reception processing after detection and configuring three or more branches to obtain the same effects as described above.

[Effects of the Invention] As described above, the digital modulation signal demodulation device of the present invention has the following effects and advantages. That is, the symbol phase difference between the BB multiplied signals before selection or combination in the selection or combination diversity reception processing is effectively reduced, and the BB multiplied signals with a high S/N ratio are always selected or combined, and then, It is characterized in that demodulated signal processing is performed.

As a result, the average S/N of the BB multiplied signal input to the demodulation circuit
The ratio is improved, and the symbol phase when switching the BB multiplied signal obtained from the branch does not change significantly, and code amount interference does not occur during synthetic divergence, and the error rate characteristics in demodulation processing are improved. , the transmission quality will improve as a result.

[Brief explanation of drawings]

FIG. 1 shows a first example of a digital modulation signal demodulation device according to the present invention.
FIG. 2 is a block diagram showing the overall configuration of an embodiment of the present invention.
FIG. 3 is a block diagram showing the overall structure of a conventional digital modulation signal demodulation device. 12a, 12b...Detection circuit 16a, 16b...Reception level detection circuit 20...Comparison circuit 22...Switch circuit 24...Demodulation circuit 26a, 26b...Variable delay circuit 28...Phase Comparison circuit 30...Averaging circuit A, B...Branch 5aSSb...Digital modulation signal S e, S f-BB double signal g5Sh...Voltage signal Si...Switching control signal 5O1Sp...Control Signal S m SS n...Delayed BB signal Sr...Demodulated signal

Claims (1)

[Claims] (1) In a digitally modulated signal demodulator that is equipped with a reception level detection circuit that detects the reception signal level and a detection circuit that detects the reception signal in each of the plurality of reception paths, and that performs selection diversity reception processing after the detection, each reception A phase comparison means that detects a symbol phase error in a path and sends out a phase difference signal; and a signal that is inputted based on a control signal that is disposed in at least one of the reception paths before selection diversity reception processing. variable delay means for delaying the signal, and control for sending the control signal to the variable delay circuit in order to reduce the symbol phase difference of the signals related to each reception path when the phase difference signal is supplied and before selection diversity reception processing is performed. A digital modulation signal demodulation device comprising: means;