JPH03201475A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate a lateral type transistor in positional deviation by a method wherein impurity introducing holes are bored in an insulating film corresponding to an isolating region, an emitter region, and a collector region. CONSTITUTION:An insulating film 61 is formed on a reverse conductivity type semiconductor layer 28 provided with a reverse conductivity type buried layer 29. In succession, impurity introducing holes 62 are bored in the insulating film 61 corresponding to a pre-determined emitter region 47, a predetermined collector region 48 of-conductivity type surrounding the emitter region 47, and a predetermined isolating region 31 of-conductivity type. Next, impurity is introduced into the predetermined isolating region 31, the predetermined emitter region 47, and the predetermined collector region 48 through the holes 62. By this setup, a lateral type transistor 25 is prevented from deviating from a design in position, and the positional deviation from a design occurred at the time when a lateral type transistor 25 and a vertical type transistor 21 are integrated together can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a semiconductor integrated circuit in which the steps are simplified and the integration density is significantly improved.

(b) Conventional technology As semiconductor integrated circuits continue to become more sophisticated and functional, high integration has become an extremely important point.

For example, the structure and manufacturing method of bipolar transistors were published by the "Latest LSI Process Technology" Industrial Research Group (April 2, 1984).
5th issue) etc.).

This bipolar transistor (1) is P as shown in Figure 2.
An N-type epitaxial layer (3) is formed on a type semiconductor substrate (2).
) are stacked, and an N+ type buried layer (4) is formed between the semiconductor substrate (2) and the epitaxial layer (3).

Further, around this buried layer (4), P that has reached the semiconductor substrate (2>) from the surface of the epitaxial layer (3)
"There is a separation area (5) of the type. This separation area (5) is
It may be diffused all at once from the surface of the epitaxial layer, or it may be dispersed by a vertical separation method as shown in FIG.

Furthermore, an island (6>) made of the epitaxial layer (3) is formed by the isolation region (3), and this island (6>) becomes an N-type collector region. Base area of mold (7)
an N'' type emitter region (8) formed within the base region (7), and a collector contact region (9) formed in a region where the epitaxial layer serving as the collector is exposed; Further, the epitaxial layer (3)
Sin formed above.

There are respective electrodes formed through contact holes in the membrane.

Next, a method for manufacturing this bipolar transistor (1) will be described. First, on a P-type semiconductor substrate (2),
There is a first step in which a film of Sin is formed, a diffusion hole of a buried layer (4) is formed in this film, and antimony is diffused into the semiconductor substrate (2) through the diffusion hole.

In the case of FIG. 2, since the separation region (5) is achieved by vertical separation, poron is diffused into the semiconductor substrate (2>) through the diffusion hole, and the P+ type lower diffusion layer (
10> is also formed.

Next, an epitaxial layer (3) is formed on the surface of the semiconductor substrate (2).
) are stacked, and a SiO* film is formed on this epitaxial layer (3). In this Sin film, a diffusion hole in the upper diffusion region (11) of the separation region east is formed by photoresist film application, mask alignment, exposure, etching, etc., and the poron is diffused through this diffusion hole. There is a second step in which isolation regions are formed.

Subsequently, the above-mentioned SiO! There is a third step of forming diffusion holes in the membrane for the base region (7) and diffusing poron through the diffusion holes to form the base region (7).

Furthermore, the above-mentioned Sin is further coated again by applying a photoresist film, aligning a mask, exposing to light, etching, etc.

Diffusion holes for the emitter region (8) and collector contact region (9) are formed in the film, and arsenic is diffused through the diffusion holes to form the emitter region (8) and collector contact region (9).
There is a fourth step of forming 9>.

Finally, contact holes for the emitter region (8), base region (7), and collector contact region (9) are formed in the 5iO1 film by applying a photoresist film again, mask alignment, exposure, etching, etc., for example. There is a fifth step of vapor depositing A to form the respective electrodes.

(c) Problems to be Solved by the Invention A bipolar transistor (1) is achieved through the first to fifth steps described above. However, the formation positions of the diffusion holes in the second, third, and fourth steps may deviate from the designed values due to mask alignment and etching.

In FIG. 2, the upper diffusion region (11
) and the base region (7) are respectively 4 μm and 1 μm, they spread to the same extent in the lateral direction.

Furthermore, due to mask alignment or etching, the base region (7) may be formed shifted to the left as shown by the broken line in FIG. Of course, the same thing can be said if the image is shifted to the right or in the direction perpendicular to the plane of the paper. Considering this, in reality, a margin of width (approximately 2 μm) shown by the arrow is provided to prevent contact with each diffusion region. Therefore, a margin of 4 μm is set on both sides for each transistor to be integrated, which has been an obstacle to improving the degree of integration.

Moreover, since the base and emitter regions each require mask alignment, etching, and diffusion steps, the number of steps is long, resulting in a decrease in yield.

Although the above description has been made regarding vertical NPN transistors, problems similar to those of this transistor also occur with lateral type transistors that are also integrated. That is, to explain using FIG. 1N of the present invention, after forming the upper diffusion region (32) of the upper and lower separation regions (31) surrounding the lateral transistor (25), the lateral transistor (25) is constructed. Since the diffusion holes of the P-type emitter (47) and collector region (48) are formed through mask alignment and etching processes, deviations from design values occur.

As described above, the present application is a lateral type transistor (25)
It also prevents deviation from the design value that occurs in the lateral type transistor (25) and vertical type transistor (25).
This is to prevent a deviation from the design value that occurs when the elements 21) and 21) are integrated together.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and provides a method for manufacturing a semiconductor integrated circuit having a lateral transistor (25) having an emitter region (47) of at least one conductivity type. There is a step of forming an insulating film (61) on a semiconductor layer (28) of a reverse conductivity type having a buried layer (29) of a reverse conductivity type, and a step of forming an insulating film (61) on a semiconductor layer (28) having a buried layer (29) of a reverse conductivity type; 47)
A predetermined collector region of one conductivity type surrounding 48) and -
The insulating film (
forming an impurity introduction hole (62) in the impurity introduction hole (61);
), and a step of introducing impurities into the planned emitter region (47) and the planned collector region (48).

Also, a lateral transistor (25) having an emitter region (47) of at least one conductivity type and a vertical transistor (21) having an emitter region (39) of the opposite conductivity type.
A method for manufacturing a semiconductor integrated circuit, comprising: a buried layer (29) of an opposite conductivity type provided in the planned lateral transistor (25) region and the planned vertical transistor (21) region. a semiconductor of opposite conductivity type,
1ii (2B> forming an insulating film (61) on top;
The emitter region (47) scheduled to be formed in the scheduled lateral type transistor (25), this emitter region (4
a collector region (48) of one conductivity type surrounding the planned vertical transistor (21), a base region (38) of one conductivity type planned to be formed in the planned vertical transistor (21), and an isolation region of -conductivity type (
forming impurity introduction holes (62) in the insulating film (61>) corresponding to the insulating films (61>), and introducing impurities into the introduction holes (62) to form the intended isolation regions (31>) and The emitter region (47), the planned collector region (
48) and a step of diffusing the base region (38>).

(*) Effect In the lateral type transistor (25), an impurity introduction hole (62 ) are opened at - degrees, the formation position of each diffusion region can be determined, and the deviation of the formation position that was conventionally provided can be eliminated.Also, the margin due to deviation can be omitted.

On the other hand, when a vertical transistor (21) and a lateral transistor (25) are integrated on a semiconductor substrate, an isolation region (31) formed in the lateral transistor region, an emitter region ( The insulating film (61) corresponding to the isolation region (31) and the base region (38) formed in the vertical transistor region is doped with impurities. Since the introduction holes (62) are opened every second, the formation position of each diffusion region can be determined, and the deviation of the formation position which was conventionally provided can be eliminated.Also, the margin due to deviation can be omitted.

(F> Example) A method for manufacturing a semiconductor integrated circuit, which is an example of the present invention, will be explained below.
transistor (21), lateral PNP type second
I"L (24) consisting of a transistor (22), a vertical NPN third transistor (23), a lateral PNP fourth transistor (25), and a vertical PNP transistor (24). A case in which the fifth transistor (26) is integrated will be explained.

First, the overall configuration will be explained using FIG. 1N.

As shown in the figure, there is a P-type silicon substrate (27), and on this substrate (27) there is an N-type semiconductor layer (28) (hereinafter described as an epitaxial layer). ) and the substrate (27),
The first transistor (21), I”L (24), the fourth transistor (25) and the fifth transistor (26)
) N+ type buried layers (29) are formed respectively corresponding to the regions. Further, a P1 type buried layer (30) is further formed on the N'' type buried layer (29) corresponding to the fifth transistor (26>).

The epitaxial layer (28) surrounds the buried layer (29) with
) There is a P+ type upper and lower separation region (31) passing through.

This upper and lower separation region (3) is composed of an upper diffusion region (32) and a lower diffusion region (33).
2> is diffused downward from the surface of the epitaxial layer (28>), and the lower diffusion region (33) is diffused downward from the surface of the substrate (27>).
This is achieved by spreading upward from the surface. Further, in order to achieve high integration of the Tsujimoto integrated circuit, the lower diffusion region (33) is substantially formed in the epitaxial layer (28).
) is diffused upward to near the surface.

Therefore, the upper and lower separation areas (31) separate the first to fourth islands (34), (35) from the left side of the figure.
, (36), (37) are formed.

The first island arch 34) has the epitaxial layer (28) as a collector, a P-type base region (38),
N+ type emitter region (39) and the base region (
38〉 P1 type base contact region (
40) (vertical NPN transistor) (21).

The second island (35) has a lateral PNP type second transistor (22) and a vertical NPN type third transistor.
At least one I"L (24) is incorporated by the transistor (23) of the second transistor (23).
2> is based on the N-type epitaxial layer (28) and consists of a P+-type emitter region (41) and a P+-type collector region (base contact region of the third transistor (23)) (42). , the emitter region〈
41> is the injector area of I”L (24).-
The transistor (23) of younger brother 3 uses the P+ type well region (43) as a base region, and the epitaxial layer (23)
8) is the emitter region. Further, the N+ type diffusion regions (44) are used as collectors C1 and C2. Furthermore, the P1 type base region is diffused over the entire surface except for two locations in the well region (43). This is because two collector regions (44) are created, and this number can be varied depending on the purpose. Further, on the opposite side of the P1 type injector region (41), there is an N'' type emitter extraction region (45) and an N1 type emitter contact region (46).

A lateral PNP type fourth transistor (25) is incorporated in the third island (36), and is based on the epitaxial layer (28), with a P+ The emitter area of the mold (4
7) and around this emitter region (47) there is a P+ type collector region (48).Furthermore, there is an N1 type diffusion region (48).
9〉, which acts as a base contact region.

The fourth island (37) has a vertical PNP type fifth island.
A transistor (sub) is incorporated. As mentioned above, this island (37) is provided with an N+ type buried layer (29) and a P1 type buried layer (3o) from the bottom, and this P1 type buried layer (3o) This becomes the collector region.In addition, in order to take out this collector region, the P-type buried layer (30) is removed from the surface of the epitaxial layer (28).
) is provided with a P3-type collector take-out area (50). Also, this flexibule take-out area (50
An N+ type well region (51) is overlapped and diffused in the region surrounded by
A mold base contact region (53) is formed.

Although the N1 type well region (51) is overlapped here, it may simply be an N type epitaxial layer (28).

Furthermore, an insulating film (54) made of a silicon oxide film or the like is formed on the surface of the epitaxial layer (28), and electrodes are formed through contact holes.

Starting from the left side of the figure, the first island (3
4) has a collector hole, a base hole, and an emitter hole formed therein, and the collector electrode, base electrode, and emitter electrode are formed through these holes. Second island (3
In 5), an injector hole, a base hole, a collector hole, and an emitter hole are formed, and an injector electrode, a base electrode, a collector electrode, and an emitter electrode are formed.

An emitter hole, a collector hole, and a base hole are formed in the third island (36), and an emitter electrode, a collector electrode, and a base electrode are formed therein. A collector hole, an emitter hole, and a base hole are formed in the fourth island (37), and a collector electrode, an emitter electrode, and a base electrode are formed therein.

As described above, this configuration is achieved using the negative layer of electrodes, but depending on the circuit, it may be configured using two or more layers of electrodes.

Diodes, resistors, etc. are also incorporated, but they are omitted here.

Next, the manufacturing method of the present invention will be explained.

First, as shown in Figure 1A, the impurity concentration is 10'' atoms.
/ cm” After forming a thermal oxide film on the surface of the P-type silicon semiconductor substrate (27), an N1-type buried layer (29) is formed.
After etching the region where the wafer is to be formed, antimony or arsenic, which is an N-type impurity, is doped through the opening.

Next, as shown in FIG.
An opening is made in the thermal oxide film on the region where the P2 type buried layer (3o) is to be formed, and boron, which is a P type impurity, is doped through this opening. Here, it may be achieved by ion implantation. That is, the thermal oxide film formed in the previous process is removed, a thermal oxide film of approximately 500 layers is formed again, a resist serving as a positive mask is applied and patterned, and boron ions are implanted.

After that, the resist is removed, heat treatment is applied, and the film is diffused.

Next, as shown in FIG. 1C, after removing all the thermal oxide film on the semiconductor substrate (27), a well-known vapor phase growth method is applied to the semiconductor substrate (27) with a specific resistance of 0.1 to 5 Ω. An N-type epitaxial layer (28) is formed with a thickness of 2 to 8 μm.At this time, the previously doped impurities are diffused slightly above and below.

Next, as shown in the first diagram, heat treatment is performed in an oxygen atmosphere to form a thermal oxide film (60) of about 500 layers on the surface of the epitaxial layer (28). Next, a negative resist film is applied to the entire surface and patterned to form the fifth transistor (26
) Phosphorus ions are implanted into the surface of the epitaxial layer (28) corresponding to the N1 type well region (51>).

Next, as shown in FIG. 1E, after removing the resist film, a negative resist film is again applied to the entire surface and patterned to form a P+ type well region to be formed in the second island (35). Epitaxial layer (2) corresponding to (43)
8> Inject boron ions into the surface.

Next, as shown in No. 11F (7), a thermal oxide film is formed on the surface of the epitaxial layer (28) by thermal oxidation at a temperature of approximately 1000'C for several hours, and then the entire semiconductor substrate is thermally simulated again. , re-diffusion of previously doped impurities.

Therefore, the lower diffusion region (33) is upwardly diffused to more than about half of the epitaxial layer (28) (substantially near the surface of the epitaxial layer (28)).

Also, by this process, the thermal oxide film (61) on the surface of the epitaxial layer (28) grows to a thickness of several thousand square meters, and this thermal oxide film (61) functions similarly to a mask described later. However, the thermal oxide film may be completely removed and a silicon nitride film or the like may be used as a diffusion mask, or a silicon oxide film may be formed by CVD.

Further, when the thickness of the epitaxial layer is reduced to about half that of the conventional one, the lower front diffusion region (33) is also made shallower. Therefore, the lateral spread can be reduced.

Next, as shown in FIG. 1F, the second island (35
) The insulating film (61) corresponding to the emitter extraction region (45) of the third transistor (23) in ) is etched, and Poclm, which will serve as a diffusion source, is applied to the entire surface.

After that, heat treatment is performed to convert phosphorus into the epitaxial layer <28)
diffuse within. Thereafter, FoC1s is removed and heat treatment is performed again to a predetermined depth.

Next, as shown in Figure 1G, the planned upper and lower separation areas (31)
The upper diffusion region (32) of the intended first transistor (
21), the planned I"L (24), the injector region (41>, which becomes the emitter region of the second transistor (22), the third transistor (23)
), the emitter region (47) and collector region (48) of the intended fourth transistor (25), the emitter region (52) and collector extraction region of the intended fifth transistor (sub) (50
An impurity introduction hole <62> is formed in the silicon oxide film (61>) corresponding to <>.

Here, the film is formed by dry etching using a positive resist film as a mask. After this, an epitaxial layer (2
8) Dummy oxidize the exposed region to form a dummy oxide film. This dummy oxide film is used to reduce damage to the epitaxial layer (2B) caused by the subsequent ion implantation process and to uniformly implant ions by randomly dispersing them.

Next, as shown in FIG. 1H, the base region (38) of the first transistor (21),
The emitter region (4) of the second transistor (22) of 4)
1) and the base contact region (42) of the third transistor (23), the planned fourth transistor (2
5) emitter region (47) and collector region (48)
), a mask (
63) and ions of boron as an impurity are implanted.

Therefore, the planned upper diffusion region <32> and the planned collector extraction region <50> of the fifth transistor (26>)
is injected with boron.

Here, after covering the entire surface with a resist film capable of blocking implanted ions, a so-called mask (63), the mask (63) corresponding to the upper diffusion region (32>) is removed, and the mask (63) corresponding to the upper diffusion region (32>) is removed.
Boron, which is an impurity in the mold, is implanted under predetermined conditions.

In this step, even if the opening of the mask (63) is formed larger than the introduction hole (62) of the silicon oxide film (61) as shown in the figure, the silicon oxide film (61) acts as a mask, so the introduction hole ( 62) and the planned upper diffusion region (32
> indicates that the formation positions match.

Subsequently, as shown in FIG. 1I, the resist (63) serving as the mask is removed, and a meditation cycle is performed under predetermined conditions.

Therefore, the upper diffusion region (32) is the lower diffusion region (32).
33). As mentioned above, the lower diffusion region (3
3) is diffused upward to near the surface of the epitaxial layer (28>), so that the upper diffusion region (32) can be diffused shallowly. Therefore, lateral diffusion of the upper diffusion region 32) can be prevented. Also, the collector extraction area (50)
reaches the P+ type buried layer (30).

Subsequently, as shown in FIG. 1J, impurity ions are implanted into all the introduction holes (62).

Here, since no mask is formed in the introduction hole (62>),
The base region (38) of the first transistor (21), the emitter region (41) of the second transistor (41), the third
The base contact region (42) of the transistor (23)
), the emitter region (47) of the fourth transistor (25)
), the collector region (48), and the emitter region (<52) of the fifth transistor (26). > is ion-implanted again.

Next, as shown in Figure 1, the planned first transistor (
A resist film (64) serving as a mask is formed so that at least the base contact region (40) to be formed in the base region (38) of 21) is opened. Then, boron ions are implanted.

Here, the base region (38> except the base contact region (40) is covered with at least a resist film (64),
In addition, all the introduction holes (62) shown in the figure are open. However, considering the impurity concentration of each, the introduction holes (62)
) may be partially covered with a resist film.

The feature of the present invention lies in the steps explained in FIGS. 1G to 1.

As shown in FIG. 1G, the base region (38) of the first transistor (21), the emitter region (41) of the second transistor (22), the base contact region (42) of the third transistor (23), The emitter region (47) and collector region (48) of the fourth transistor (25), the emitter region (52> and collector extraction region (50) of the fifth transistor (26), and all the upper diffusion regions (32) Since the corresponding introduction hole (62) is formed at - degree and the formation position is determined by this introduction hole (62),
It is possible to omit the conventionally provided margin due to deviation from the design value.

In particular, in the first transistor (21), the upper diffusion region (
32>, base region (38>, second transistor (2
2), the upper diffusion region (32〉) and the emitter region (41〉)
, in the fourth transistor (25), the upper diffusion region (32
), the collector region (48), and the fifth transistor (26
〉, the collector extraction area (50〉) and the emitter area (
52〉 is no longer necessary, and since the allowance is removed in the horizontal and vertical directions, each cell size becomes smaller.
In the end, the chip size can be reduced. Furthermore, since the cell size can be reduced, the length and width and degree of integration can be improved.

On the other hand, the fifth transistor (26) is a vertical PNP.
type transistor, the left and right collector extraction areas (
50> can be shortened, the collector resistance can be made small, and the saturation voltage of VCt can be made small.

In the step of FIG. 1J, diffusion was performed without forming a mask, but in the present application, a mask may be provided in the introduction hole above the separation region.

As explained in FIG. 1M, by simply making the opening of the mask slightly larger than the introduction hole (62), the diffusion region (38) can be accurately determined. Injection into the region (31>) can be prevented.

Next, as shown in the first diagram, the photoresist film (64) is removed and the entire silicon oxide film (61) on the epitaxial layer (28>) is etched.After that, a non-doped silicon oxide film and a phosphorus-doped silicon film are etched on the entire surface. Thousands of oxide films are stacked on each layer to ensure that there is no difference in the overall film thickness.This means that if the silicon oxide film (61) shown in Figure 1 is used, the first transistor (21〉
Since the silicon oxide film (61) on the emitter region (39) is thinner than the silicon oxide film on the collector region, the epitaxial layer that will become the emitter region (39) is This is because the epitaxial layer corresponding to the emitter region (39) is etched or side-etched of the corresponding silicon oxide film (61). The amount of side etching of the silicon oxide film on the epitaxial layer is reduced.

Furthermore, as shown in FIG. 1M, a photoresist film is formed and a contact hole is formed in the silicon oxide film (66) by anisotropic etching.

Specifically, the emitter hole (67), base hole (68> and collector hole (69>) of the first transistor (21>)
, the emitter hole (7o) of the second transistor (22>),
Emitter hole (71), base hole (72) and collector hole (73) of the third transistor (23), emitter hole (74), base hole (75) of the fourth transistor
) and the collector hole (76〉, the fifth transistor (2
6), an emitter hole (77>), a base hole (78>) and a collector hole (77>) are formed.

After removing the photoresist film, the first photoresist film is removed again.
The base hole (68) of the transistor (21), the emitter hole (70) of the second transistor (22), the base hole (72) of the third transistor (23), the emitter hole of the fourth transistor (25) (74) and collector hole (
76>, the emitter hole (7) of the fifth transistor (26)
7) and the collector hole (79) with a resist film (80), and then use this resist film (80) as a mask.
Arsenic is ion-implanted into the emitter region (39) of the first transistor (21) and the emitter region (39) of the third transistor (23).
Then, the emitter contact region (46) and the collector region (44) are formed in the fourth transistor (25), the base region (49) is formed in the fourth transistor (26), and the base contact region (53) is formed in the fifth transistor (26). Here, an N+ type diffusion region is formed to implant arsenic ions.

Finally, the resist film (80) is removed, heat treatment is performed to diffuse the N+ type diffusion region downward, and the silicon oxide film formed on the surface of the hole is removed by light etching. As shown in the figure, the electrodes of the first to fifth transistors are formed by vapor deposition of aluminum.

(g) Effects of the invention As is clear from the above explanation, in a lateral type transistor, impurity introduction holes are formed in the insulating film corresponding to the intended emitter region, intended collector region, and intended isolation region. Therefore, the formation positions of these regions are determined in advance. Therefore, the allowance conventionally provided as a measure against deviation from the designed position can be omitted. Furthermore, the area occupied by the lateral transistor can be reduced.

On the other hand, when a lateral type transistor and a vertical transistor are integrated together, at the same time as the introduction hole provided in the lateral type transistor, the intended base region and intended isolation region of the vertical transistor region are Since the impurity introduction hole is provided in the corresponding insulating film, the occupied area can be reduced for the same reason as mentioned above.

[Brief explanation of drawings]

1A to 1N are cross-sectional views showing the method of manufacturing a semiconductor integrated circuit according to the present invention, and FIG. 2 is a cross-sectional view of a conventional semiconductor integrated circuit manufactured by the company.

Claims (6)

[Claims] (1) A method for manufacturing a semiconductor integrated circuit having a lateral transistor having an emitter region of at least one conductivity type, the method comprising forming an insulating film on a semiconductor layer of an opposite conductivity type having a buried layer of an opposite conductivity type. forming impurity introduction holes in the insulating film corresponding to the intended emitter region, the intended collector region of one conductivity type surrounding the emitter region, and the intended isolation region of one conductivity type; A method for manufacturing a semiconductor integrated circuit, comprising the step of introducing impurities into the intended isolation region, the intended emitter region, and the intended collector region through an introduction hole. (2) A method for manufacturing a semiconductor integrated circuit having a lateral transistor having an emitter region of at least one conductivity type, comprising: forming a buried layer of an opposite conductivity type in a semiconductor substrate of one conductivity type; a step of forming a lower diffusion region of a vertical isolation region that is scheduled to surround a buried layer of an opposite conductivity type; a step of forming a semiconductor layer of an opposite conductivity type on the semiconductor substrate; and a step of forming an insulating film on the semiconductor layer. forming an impurity introduction hole in the insulating film corresponding to the intended emitter region, the intended collector region of one conductivity type surrounding the emitter region, and the intended isolation region of one conductivity type; A method for manufacturing a semiconductor integrated circuit, comprising the step of introducing impurities into the intended isolation region, the intended emitter region, and the intended collector region through the introduction hole. (3) The method for manufacturing a semiconductor integrated circuit according to claim 2, wherein the semiconductor layer is an epitaxial layer. (4) A method for manufacturing a semiconductor integrated circuit having a lateral type transistor having an emitter region of at least one conductivity type and a vertical type transistor having an opposite conductivity type, the method comprising the steps of: forming an insulating film on a reverse conductivity type semiconductor layer having a reverse conductivity type buried layer provided in a vertical transistor region, the emitter region to be formed in the planned lateral transistor; Impurity introduction holes are formed in the insulating film corresponding to a collector region of one conductivity type surrounding the emitter region, a base region of one conductivity type to be formed in the vertical transistor, and an isolation region of one conductivity type, respectively. and a step of introducing an impurity into the introduction hole to diffuse the intended isolation region, the intended emitter region, the intended collector region, and the base region. manufacturing method. (5) A method for manufacturing a semiconductor integrated circuit having a lateral transistor having an emitter region of at least one conductivity type and a vertical transistor of an opposite conductivity type, the method comprising: the scheduled lateral transistor and the scheduled vertical transistor; A step of forming a buried layer of an opposite conductivity type in a semiconductor substrate of one conductivity type corresponding to a transistor of the same type, and a step of forming a lower diffusion region of a planned vertical isolation region of one conductivity type surrounding the buried layer. a step of forming a semiconductor layer of an opposite conductivity type on the semiconductor substrate; a step of diffusing the lower diffusion region upward to near the surface of the semiconductor layer and forming an insulating film on the surface of the semiconductor layer; The emitter region to be formed in the planned lateral transistor, the planned collector region of one conductivity type surrounding the emitter region, the base region of one conductivity type to be formed in the planned vertical transistor, and the one conductivity type. forming impurity introduction holes in the insulating film corresponding to the isolation regions, respectively, and introducing impurities into the introduction holes to form the intended isolation regions, the intended emitter regions, the intended collector regions, and the base. 1. A method of manufacturing a semiconductor integrated circuit, comprising the step of diffusing a region. (6) A method for manufacturing a semiconductor integrated circuit having a lateral type transistor having an emitter region of at least one conductivity type and a vertical type transistor of an opposite conductivity type, the method comprising: the scheduled lateral type transistor and the scheduled vertical type transistor; A step of forming a buried layer of an opposite conductivity type in a semiconductor substrate of one conductivity type corresponding to a transistor of the same type, and a step of forming a lower diffusion region of a planned vertical isolation region of one conductivity type surrounding the buried layer. forming a semiconductor base layer of opposite conductivity type on the semiconductor substrate; diffusing the lower diffusion region upward to near the surface of the semiconductor layer and forming an insulating film on the surface of the semiconductor layer; The emitter region to be formed in the planned lateral transistor, the planned collector region of one conductivity type surrounding the emitter region, the base region of one conductivity type to be formed in the planned vertical transistor, and the one conductivity type. forming impurity introduction holes in the insulating film corresponding to the isolation regions, respectively, and providing a mask in the introduction holes on the intended emitter region, the intended collector region, and the intended base region, and introducing impurities into the insulating film. introducing impurities into the isolation region; after removing the mask, introducing impurities into all the introduction holes to diffuse the intended isolation region, the intended emitter region, and the intended collector region; A step of providing a mask in a part of the base region of the intended lateral type transistor, and introducing impurities into the intended base contact region in the base region, the emitter region of the intended lateral type transistor, and the intended collector region. A method for manufacturing a semiconductor integrated circuit, comprising: