JPH03201447A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To suppress the deterioration or oscillation of an element and to perform precisely a measurement and evaluation of the electrical characteristics of the element by a method wherein a source electrode is divided into a plurality of pieces and the measurement of the electrical characteristics in a state that the thickness of a GaAs substrate is thick and the heat dissipation characteristics of the substrate is bad is performed using the divided individual source electrodes as a unit. CONSTITUTION:Gate electrodes 3 are formed of an Al film on the main surface on one side of a substrate into a comb type. A Schottky contact is formed between the electrodes 3 and an active layer 5. Source electrodes 2 and a drain electrode 1 are formed of an ohmic metal film to ohmic-contact to the layer 5 into a combe type in such a way as to hold the electrodes 3 between them. At this time, the electrodes 2 are formed in such a way that they are divided as many as 5 pieces into S1 to S5. At this state, a measurement of the electrical characteristics of an IDSS, a Vth and the like is performed using the divided individual source electrodes 2 as a unit. At this time, when the values of the IDSS and the like are all necessary, the values are found by taking the sum of the individual values of the electrical characteristics measured using the divided electrodes as a unit. According to this measured result, a judgement or the like on whether the following manufacturing process can be proceeded intact or not is formed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a GaAs field effect transistor for power use (
The present invention relates to a method for producing G a As F ET (hereinafter referred to as G a As F ET).

[Prior Art] GaAsFETs for power use generally have a gate length of 1 μm or less and a gate width of several mm to 10 mm. Compared to the gate width of a normal power level device, which is about 1 mm or less, the gate width is smaller. Extremely large. Therefore, its electrode structure is comb-shaped.

A conventional method for manufacturing such a GaAsFET for power use is, for example, as follows.

That is, a GaAs substrate with an initial thickness of about 400 μm is used, and on one main surface on which the active layer is formed, a source electrode, a drain electrode, and a gate electrode that make ohmic contact with the active layer are formed. be done. Each of these electrodes is formed in a comb shape, and by creating a structure in which these comb-shaped electrodes mesh in a desired manner, a gate width of the required length as described above can be obtained.

Thereafter, the other main surface of the GaAs substrate is subjected to paccite wrapping to obtain a required thickness of 100 μm or less, and then the GaAs substrate is divided into each element.

The final thickness of the device is 100μm due to backside wrap.
GaAs has a lower thermal conductivity than Si or the like, so the reason why it is made as thin as below is a necessary measure to efficiently dissipate heat from a large amount of power. However, GaAs
If the thickness of the substrate is reduced from the beginning of manufacture, GaAs has cleavage properties and is easily broken, which causes handling problems when forming source electrodes, drain electrodes, gate electrodes, and the like.

Therefore, as mentioned above, the GaAs substrate at the time of manufacture is
A thickness of about 400 μm is used.

[Problems to be Solved by the Invention] By the way, GaAsFETs have relatively large variations in characteristics during manufacture. Therefore, in order to decide whether to proceed with the subsequent manufacturing process or not, or to classify based on characteristics, electrical characteristics such as saturated drain current ID5S and gate threshold voltage vth are checked during the manufacturing process before backside lapping. measurement (DC test) is required.

However, in the conventional GaAsFET manufacturing method, each electrode is formed in a comb-shaped structure in a thick GaAs substrate before the backside wrap, which has poor heat dissipation characteristics. Since the electrode structure was formed to be the same as the final electrode structure after the device was divided, there was a risk that the substrate temperature would rise during measurements such as 1oss, leading to deterioration or destruction of the device.
There is a problem in that oscillation is likely to occur due to the negative resistance effect peculiar to s, and it is difficult to accurately evaluate the electrical characteristics. In addition, the total gate width due to the comb-shaped structure is several mm to 10 m.
Even if a part of about 20 μm in length is defective due to peeling, etc., this defective part corresponds to less than 1% of the total gate length, so such a defective part cannot be detected. The problem was that it was difficult.

Therefore, the present invention provides a field effect transistor whose electrical characteristics can be accurately evaluated before backside lapping, and whose uniformity within the substrate can also be accurately measured and evaluated. The purpose is to provide a manufacturing method for.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides (a) GaAs
forming a gate electrode, a drain electrode, and a divided source electrode on one main surface of the substrate; (b) applying a voltage between the gate electrode, the drain electrode, and the divided source electrode; (c) cutting off the other main surface of the GaAs substrate to make the GaAs substrate a required thickness; (d) measuring the required electrical characteristics for each source electrode that has been divided into The gist is to sequentially perform the steps of electrically connecting between the source electrodes.

The electrical connection between the above divided source electrodes is made of Ga
Preferably, connections from the back side are used through via holes formed in the As substrate. Furthermore, connection on the surface side of the substrate by means such as wire bonding after element division can also be used.

[Operation] In the step of forming each electrode, among the gate electrode, drain electrode, and source electrode, the source electrode, which is a low potential electrode, is divided into a plurality of appropriate parts and formed.

In a state where the GaAs substrate before backside lapping is thick and has poor heat dissipation characteristics, electrical characteristics such as ID5S are measured using each divided source electrode as a unit. Therefore, the power applied during measurement is reduced, the temperature rise of the substrate is kept low, there is no risk of deterioration of the device, and there is no risk of oscillation, allowing accurate measurement and evaluation of its electrical characteristics. becomes possible.

Furthermore, since the test is performed on each divided source electrode as a unit, it is possible to accurately measure and evaluate the uniformity of electrical characteristics within the substrate.

After measuring the electrical characteristics, the other main surface of the GaAs substrate is shaved to the required substrate thickness, and the divided source electrodes are electrically connected, and in the device state, the gate electrode, drain electrode The source electrode and the source electrode are arranged to be in an electrically normal electrode state.

[Example] Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2. This embodiment is applied to a method of manufacturing a Schottky gate type GaAsFET for power use.

First, with reference to FIG. 1, the pattern of each electrode within one element after the step of forming each electrode, that is, when measuring electrical characteristics, will be explained. In addition, in the same figure (b), the arrow part A in the same figure (a)
- It is an A line enlarged sectional view.

In the figure, 1 is a drain electrode, 2 is a source electrode, and 3 is a gate electrode. These electrodes are each formed in a comb shape, and these comb-shaped electrodes 1, 2, and 3 mesh in a required manner. It is patterned like this. Of these electrodes, source electrode 2 is s, s2 s3, s
As shown in 4 and s5, it is divided into, for example, five pieces.

Further, 40 gate electrodes 3 are combined between the drain electrode 1 and the source electrode 2 in the comb-teeth portion. The portion of the source electrode 2 that intersects with the gate power supply line is connected by an air bridge, as shown in FIG. 2(b).

Note that for the purpose of reducing the applied power when measuring electrical characteristics, the drain electrode may be divided into multiple parts instead of dividing the source electrode, but the drain electrode is the electrode connected to the load. Therefore, if there is a routing portion for commonly connecting the divided electrodes after that, there is a risk that the device performance will deteriorate. On the other hand, since the source electrode is an electrode that is grounded (at a low potential), there is no risk of deteriorating element performance even if there is a common connection routing portion therein. Therefore, in this embodiment, the source electrode side is divided into a plurality of parts as described above.

Next, a method for manufacturing a GaAsFET will be explained using FIG. Note that (a) to (d) in Figure 2 are similar to those in Figure 1 (
FIG. 2(e) is an enlarged sectional view of a portion corresponding to line BB in FIG. 1(a), and FIG. 2(e) is a sectional view of a portion corresponding to line C--C in FIG. 1(a).

(2) An n-type active layer 5, which will become a channel layer, is formed by ion implantation on one main surface of a semi-insulating GaAs substrate 4 having a thickness of about 450 μm (FIG. 2(a)).

(2) A comb-shaped gate electrode 3 with a gate length of about 0.5 μm is formed on one main surface of the substrate using an A film by a normal photolithography process (FIG. 2 (b)). A Schottky contact is formed between the gate electrode 3 and the active layer 5 .

(2) The source electrode 2 and the drain electrode 1 are formed in a comb shape using an ohmic metal that makes ohmic contact with the active layer 5, with the gate electrode 3 sandwiched therebetween.

At this time, the number of source electrodes 2 is five, S, -s, as described above.
It is formed so that it is divided into 5 parts (Fig. 1(a), Fig. 2(c)).

(2) At this stage, electrical characteristics such as ID5S and Vth are measured for each divided source electrode 2 as a unit. At this time, if the value of all ID5S etc. is required, it is obtained by calculating the sum of each divided measurement. Based on this measurement result, it is determined whether to proceed with the subsequent manufacturing process or not.

■ Back side lap the other main surface of the semi-insulating GaAs substrate 4 to form a substrate with a thickness of about 450 μm and a thickness of 50 μm.
(Fig. 2(d)).

■ By making a hole under the source electrode 2 by reactive ion etching from the back surface, and forming a metal layer 6 on the entire back surface, a hole is formed between the divided source electrodes 2 via each via hole 7. electrically connect (Fig. 2(e))
.

■ Divide into each element to complete a power GaAsFET.

As mentioned above, in the GaAsFET manufacturing method of this embodiment, the thickness of the semi-insulating GaAs substrate 4 before backside wrapping is as thick as about 450 μm, and the electrical characteristics such as ID5S cannot be measured in a state where the heat dissipation characteristics are poor. This is performed using the divided source electrodes s and -s5 as units. Therefore, the applied power during measurement is reduced and the semi-insulating GaAs substrate 4
temperature rise is suppressed to a low level, there is no risk of deterioration of the element formed on one main surface, and there is no risk of oscillation, making it possible to accurately measure and evaluate its electrical characteristics. Furthermore, since the test is performed for each divided source electrode 81 to S5 as a unit, it is possible to accurately measure and evaluate the uniformity of electrical characteristics within the substrate 4.

Then, based on this accurate measurement and evaluation, it becomes possible to appropriately determine whether or not to proceed with subsequent steps as they are, change process conditions, etc. In addition, by measuring the electrical characteristics described above, it becomes possible to ship only products with uniform internal characteristics, and furthermore, it becomes possible to
It is also possible to attach accurate characteristic values such as 5S.

Note that in the above embodiment, Schottky gate type GaAsF
Although we have described the manufacturing method of ET, junction type GaAsFE
It can also be applied to the manufacturing method of GaAsFET such as T.

[Effects of the Invention] As explained above, according to the present invention, the source electrode among the gate electrode, drain electrode, and source electrode is divided into a plurality of parts in the process of forming each electrode, and the thickness of the GaAs substrate is increased. Since electrical characteristics are measured in conditions with poor heat dissipation characteristics using each divided source electrode as a unit, less power is applied during measurement, suppressing the temperature rise of the substrate and preventing device deterioration. Alternatively, the electrical characteristics can be measured and evaluated accurately without the possibility of oscillation or the like occurring. Furthermore, since the test is performed using each divided source electrode as a unit, it is possible to accurately measure and evaluate the uniformity of electrical characteristics within the substrate. Therefore, it is possible to provide an extremely suitable method for manufacturing GaAsFETs for power use.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the pattern of each electrode during electrical characteristic measurement in an embodiment of the method for manufacturing a field effect transistor according to the present invention, and FIG. 2 is a process diagram showing the manufacturing process of the above embodiment. 1 double drain electrode, 2: source electrode, 3: gate electrode, 4: semi-insulating GaAs substrate, 5: active layer formed on one main surface of semi-insulating GaAs substrate, 6: electrically connecting the divided source electrode. 7: Via hole.

Claims (1)

[Claims] (a) A step of forming a gate electrode, a drain electrode, and a divided source electrode on one main surface of a GaAs substrate; (b) A step of forming a gate electrode, a drain electrode, and a divided source electrode on one main surface of a GaAs substrate; (c) cutting the other main surface of the GaAs substrate to measure the required electrical characteristics for each of the divided source electrodes;
A method for manufacturing a field effect transistor, comprising sequentially performing the steps of: (d) making the substrate a required thickness; and (d) electrically connecting the divided source electrodes.