JPH03200348A - Life time measurement of semiconductor - Google Patents

Life time measurement of semiconductor

Info

Publication number
JPH03200348A
JPH03200348A JP24873987A JP24873987A JPH03200348A JP H03200348 A JPH03200348 A JP H03200348A JP 24873987 A JP24873987 A JP 24873987A JP 24873987 A JP24873987 A JP 24873987A JP H03200348 A JPH03200348 A JP H03200348A
Authority
JP
Japan
Prior art keywords
measurement
capacity
time
capacitance
cfin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24873987A
Other languages
Japanese (ja)
Inventor
Morimasa Miyazaki
宮崎 守正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KYUSHU ELECTRON METAL CO Ltd
Osaka Titanium Co Ltd
Original Assignee
KYUSHU ELECTRON METAL CO Ltd
Osaka Titanium Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KYUSHU ELECTRON METAL CO Ltd, Osaka Titanium Co Ltd filed Critical KYUSHU ELECTRON METAL CO Ltd
Priority to JP24873987A priority Critical patent/JPH03200348A/en
Publication of JPH03200348A publication Critical patent/JPH03200348A/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To shorten measurement time of generated life time without the loss of measurement accuracy by previously estimating balancing capacity at inversion voltage by a capacity-voltage measurement and completing a measurement at the time the balancing capacity is attained by a capacity-time measurement. CONSTITUTION:A C meter 1 for measuring capacity by application of voltage, a central processing unit CPU2, and a printer 3 are connected with each other through a data-address bus 4. Further, a sample 5 of a MOS semiconductor wafer is connected to the C meter 1, whereby capacity C of a semiconductor 5 is measured as a function of voltage V as well as the capacity C of the semiconductor 5 is measured as a function of time t. Balancing capacity at inversion voltage is previously estimated, and upon a C-t measurement the measurement is interrupted before the balancing capacity is attained and after the elapse of arbitrary time since the initiation of the measurement. Upon a self-analysis thereafter the balancing capacity is substituted to measure generated life time. Hereby, measurement time of the generated life time can be shortened without losing measurement accuracy.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、MOS  C−を法による発生ライフタイム
の測定方法に関し、測定時間の短縮を図つたものである
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for measuring generation lifetime using the MOS C-method, and is intended to shorten the measurement time.

(従来の技術) 従来において、Si型半導体基板の発生ライフタイムを
測定する方法として、MOSダイオードを形成し容量の
過渡応答を用いる手法(MOSC−を法)が用いられて
いる。
(Prior Art) Conventionally, as a method of measuring the generation lifetime of a Si-type semiconductor substrate, a method (MOSC-method) has been used in which a MOS diode is formed and the transient response of the capacitance is used.

このC−を法は、印加電圧を蓄積状態から反転状態に切
り換えることによって生じる容量Cの過渡変化を測定し
、容量Cが平衡容量Cfinに達するまでCの過渡変化
を測定後、縦軸に−d/d t(Cox/C)”を、横
軸に(Cfin /C−1)をとりプロット(セルプス
トプロット)する。その際の直線部の傾きmから発生ラ
イフタイムが求められる。尚、Coxは酸化膜容量であ
る。
This C- method measures the transient change in capacitance C caused by switching the applied voltage from the accumulation state to the inversion state, and after measuring the transient change in C until the capacitance C reaches the equilibrium capacitance Cfin, the vertical axis shows - d/d t(Cox/C)" is plotted (Selbst plot) with (Cfin/C-1) on the horizontal axis. The generation lifetime is determined from the slope m of the straight line. Cox is the oxide film capacitance.

(発明が解決しようとする問題点) ところが、上述したC−を法においては、容量Cが反転
電圧での平衡容量Cfinに達するまでCの過渡変化を
モニターせねばならず、測定に長時間を要する問題があ
る。
(Problem to be Solved by the Invention) However, in the C- method described above, transient changes in C must be monitored until the capacitance C reaches the equilibrium capacitance Cfin at the inversion voltage, and it takes a long time to measure. There is a problem that needs to be addressed.

そこで、本発明は、C−を法により発生ライフタイムを
測定する時間を出来るだけ短縮し、かつ精度を同程度に
保持できるライフタイム測定方法を提供することを目的
としている。
Therefore, an object of the present invention is to provide a lifetime measuring method that can reduce the time required to measure the generation lifetime by the C- method as much as possible, and maintain the same level of accuracy.

(問題点を解決するための手段) 本発明のライフタイム測定方法は、MOS型半導体のラ
イフタイムなC−を法により測定する方法であって、予
めC−v法(容量−電圧法)により反転電圧での平衡容
量Cfinを求めておき、C−を測定時に、前記容量C
finに達する以前であって測定開始から任意時間経過
した後に測定を中断し、その後のゼルブスト解析時に前
記容量Cfinを代入して発生ライフタイムを測定する
構成としたものである。
(Means for Solving the Problems) The lifetime measuring method of the present invention is a method of measuring the lifetime C- of a MOS type semiconductor using the C-v method (capacitance-voltage method) in advance. Find the equilibrium capacitance Cfin at the inversion voltage, and when measuring C-, the capacitance Cfin
The measurement is interrupted after an arbitrary period of time has elapsed from the start of the measurement before reaching fin, and the generation lifetime is measured by substituting the capacitance Cfin during the subsequent Zelbst analysis.

(作 用) 本発明と、従来の測定方法とを第4図を用いて説明する
と、例えば、P型Si半導体の場合印加電圧をマイナス
5ボルト場合(蓄積領域)からプラス5ボルト(強度転
領域)に切り換え、その後の容量の回復過程を時間変化
として測定する(第4図(1))。このような従来法で
は、−回の測定につき1000 sec以上の長時間を
要することとなる。
(Function) To explain the present invention and the conventional measurement method using FIG. 4, for example, in the case of a P-type Si semiconductor, the applied voltage changes from -5 volts (accumulation region) to ), and the subsequent capacity recovery process is measured as a time change (Fig. 4 (1)). Such a conventional method requires a long time of 1000 seconds or more for each measurement.

これに対し本発明の場合は、C−v法を用い〔第4図(
2))、暗状態で電圧をマイナス5ボルトからプラス5
ボルトに掃引すると、容量Cが図示の如く変化する。プ
ラス5ボルトにおいて、明状態にすると平衡容量Cfi
nに短時間で達する点に着目したもので、この容量Cf
inを前記C−を法の測定値とともに所定条件式に代入
して、半導体の発生ライフタイムを求める。
On the other hand, in the case of the present invention, the C-v method is used [Fig. 4 (
2)), change the voltage from minus 5 volts to plus 5 volts in the dark
When swept in volts, the capacitance C changes as shown. At +5 volts, the equilibrium capacitance Cfi in the bright state
It focuses on the point where n is reached in a short time, and this capacitance Cf
By substituting in into a predetermined conditional expression together with the measured value of C-, the generation lifetime of the semiconductor is determined.

(実施例) 以下に本発明の実施例を図面に基づき説明する。(Example) Embodiments of the present invention will be described below based on the drawings.

第1図は測定装置の概略を示し、図中、1はCメータ(
電圧を与えて容量を測定するメータ)、2は中央処理装
置CPtT、3はプリンタであり、これらは互いにデー
タおよびアドレスバス4により接続されて構成されてい
る。また、Cメータ1にはMOSfi半導体ウェハのサ
ンプル5が接続され、半導体5の容量を電圧の関数とし
て測定したり、また、半導体5の容量を時間の関数とし
て測定できる構成となっている。
Figure 1 shows the outline of the measuring device, in which 1 is a C meter (
2 is a central processing unit CPtT, 3 is a printer, and these are connected to each other by a data and address bus 4. Further, a sample 5 of a MOSfi semiconductor wafer is connected to the C meter 1, and the configuration is such that the capacitance of the semiconductor 5 can be measured as a function of voltage, and the capacitance of the semiconductor 5 can be measured as a function of time.

尚、上記ライフタイム測定例で用いたSL半導体基板及
び作成したMOSダイオードに関しては、別表に示す仕
様、熱処理条件および電極作成条件としたものを使用し
ている。
In addition, regarding the SL semiconductor substrate and the produced MOS diode used in the above lifetime measurement example, the specifications, heat treatment conditions, and electrode production conditions shown in the attached table were used.

別表 (以下余白) 次に、本方法によるMO5型半導体の発生ライフタイム
の測定手順を示す。先ず、C−v法によりシリコンのド
ーパント濃度(Nsub )及びCfinを測定する。
Attached Table (blank below) Next, the procedure for measuring the generation lifetime of MO5 type semiconductor using this method will be shown. First, the dopant concentration (Nsub) and Cfin of silicon are measured by the C-v method.

そして、C−を法により、印加電圧を蓄積状態から反転
状態に切り換えることによって生じる容量Cの過渡変化
を測定する。容量Cの過渡変化は次式により表わされる
Then, the transient change in the capacitance C caused by switching the applied voltage from the accumulation state to the inversion state is measured using the C- method. The transient change in capacitance C is expressed by the following equation.

(−d/dt)(Cox/C)”m(2nicox/N
5ub −EoxEsi)S。
(-d/dt)(Cox/C)”m(2nicox/N
5ub-EoxEsi)S.

+(2niCox/N5ub−Cfin)・(1/ τ
g) ・[(Cfin/c)−11・・・(1) 但し、Cox;酸化膜容量、 ni;真性キャリア濃度
Eox ;酸化膜誘電率、 Esi;Stの誘電率τg
;少数少数リヤリフライフタイム、  So;  表面
発生速度上記容量Cの過渡変化を測定する場合には、容
量CがCfinに達する以前に測定をストップさせ、C
finを(1)(2)式に代入し、縦軸に(−d/dt
)・(Cox/C)2を、横軸に[(Cfin/C)−
11をとりプロット(ゼルブストプロット)する。その
際の傾きをmとすると、次式により発生ライフタイムを
求めることかできる。
+(2niCox/N5ub-Cfin)・(1/τ
g) ・[(Cfin/c)-11...(1) However, Cox: oxide film capacitance, ni: intrinsic carrier concentration Eox: oxide film dielectric constant, Esi: dielectric constant τg of St
; Minority rear life time, So; Surface generation speed When measuring the transient change in the above capacitance C, stop the measurement before the capacitance C reaches Cfin, and
Substitute fin into equations (1) and (2), and plot (-d/dt
)・(Cox/C)2 on the horizontal axis [(Cfin/C)−
11 and plot it (Zerbst plot). If the slope at that time is m, then the generation lifetime can be calculated using the following equation.

? r2m−’ (ni/N5ub) ・(Cox/C
f in)    ・・・(2)但し、測定ストップま
での時間が短かすぎるとτgが精度良く測れないので、
CがCfinの80%程度の容量に達した時点で測定を
ストップさせると良い。
? r2m-' (ni/N5ub) ・(Cox/C
f in) ...(2) However, if the time until the measurement stop is too short, τg cannot be measured accurately.
It is preferable to stop the measurement when C reaches a capacity of about 80% of Cfin.

本発明者が試験を行った結果、第2図〜第3図に示す結
果を得ることができた。第2図にはMOS  C−を法
による容量の過度変化(第2図(a)。
As a result of the tests conducted by the inventor, the results shown in FIGS. 2 and 3 were obtained. Figure 2 shows the transient change in capacitance by the MOS C- method (Figure 2(a)).

(b)、(C)、(d) ”)とゼルブストプロット(
第2図(e)、(f)、(g)、(h) )を示してお
り、第2図(a)と(e)が従来方法による場合を、第
2図(b)〜(d)。
(b), (C), (d)”) and Serbst plot (
Figures 2(e), (f), (g), and (h)) are shown, and Figures 2(b) to (d) show the cases in which Figures 2(a) and (e) are based on the conventional method. ).

(f)〜(h)が本発明方法による場合を示している。(f) to (h) show cases in which the method of the present invention is used.

第3図(a)には、従来方法と本発明方法における測定
時間と発生ライフタイムとの相関を示しており、第3図
(b)には双方の方法におけるCe(測定終了時の容量
)/Cfinと発生ライフタイムの相関を示している。
Figure 3(a) shows the correlation between the measurement time and generation lifetime in the conventional method and the method of the present invention, and Figure 3(b) shows the Ce (capacity at the end of measurement) in both methods. It shows the correlation between /Cfin and occurrence lifetime.

尚、第3図(f)〜(h)において、左右の一点鎖線は
、傾きの計算範囲を示している。
In addition, in FIGS. 3(f) to 3(h), the left and right dashed lines indicate the calculation range of the slope.

本結果より、本方法によれば、C/Cfin =0.8
程度となるまで、容量の過度変化を測定すれば、従来法
と同程度の精度で且つ60%程度の時間で発生ライフタ
イムを測定し得ることが明らかになった。
From this result, according to this method, C/Cfin = 0.8
It has become clear that by measuring transient changes in capacitance up to a certain level, generation lifetime can be measured with accuracy comparable to that of conventional methods and in about 60% of the time.

(発明の効果) 以上説明したように本発明によると、あらかじめC−■
測定により反転電圧での平衡容量Cfinを求めておけ
ば、C−を測定でCfinの80%程度の容量に達した
時点で測定を終了すれば、測定精度を損なうことなく、
発生ライフタイムの測定時間の短縮化を可能とする効果
を奏する。
(Effect of the invention) As explained above, according to the present invention, C-■
If the balanced capacitance Cfin at the inversion voltage is determined by measurement, if C- is measured and the measurement is finished when the capacitance reaches approximately 80% of Cfin, the measurement accuracy will not be compromised.
This has the effect of making it possible to shorten the time required to measure the occurrence lifetime.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は測定装置の概略構成図、第2図(a)〜(d)
と(e)〜(f)容量過度変化およびセルプストプロッ
トとの関係を示す図、第3図(a)は測定時間と発生ラ
イフタイムとの相関図、第3図(b)はCe/Cfin
と発生ライフタイムの相関図、第4図はC−を法とC−
v法の説明図である。 4・・・MOS型半導体ウェハ τg・・・ライフタイム
Figure 1 is a schematic configuration diagram of the measuring device, Figure 2 (a) to (d)
(e) to (f) A diagram showing the relationship between capacitance transient change and Selbst plot, Figure 3 (a) is a correlation diagram between measurement time and generation lifetime, and Figure 3 (b) is Ce/Cfin.
Figure 4 shows the relationship between C- and occurrence lifetime.
FIG. 2 is an explanatory diagram of the v method. 4...MOS type semiconductor wafer τg...lifetime

Claims (2)

【特許請求の範囲】[Claims] (1)Si型半導体基板のライフタイムをMOSC−t
法により測定する方法であって、予めC−V法により反
転電圧での平衡容量Cfinを求めておき、C−t測定
時に、前記容量Cfinに達する以前であって測定開始
から任意時間経過した後に測定を中断し、その後のセル
プスト解析時に前記容量Cfinを代入して発生ライフ
タイムを求めることを特徴とする半導体のライフタイム
測定方法。
(1) MOSC-t Si type semiconductor substrate lifetime
In this method, the equilibrium capacitance Cfin at the reversal voltage is determined in advance by the CV method, and when measuring C-t, the capacitance Cfin is measured before the capacitance Cfin is reached and after an arbitrary period of time has elapsed from the start of the measurement. 1. A semiconductor lifetime measuring method, characterized in that measurement is interrupted and the capacitance Cfin is substituted during subsequent Selpst analysis to determine generation lifetime.
(2)前記容量Cfinの80%程度に達した時点で、
C−t法による測定を中断させる特許請求の範囲第1項
記載の半導体のライフタイム測定法。
(2) When approximately 80% of the capacity Cfin is reached,
2. A semiconductor lifetime measuring method according to claim 1, wherein measurement by the C-t method is interrupted.
JP24873987A 1987-10-01 1987-10-01 Life time measurement of semiconductor Pending JPH03200348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24873987A JPH03200348A (en) 1987-10-01 1987-10-01 Life time measurement of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24873987A JPH03200348A (en) 1987-10-01 1987-10-01 Life time measurement of semiconductor

Publications (1)

Publication Number Publication Date
JPH03200348A true JPH03200348A (en) 1991-09-02

Family

ID=17182644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24873987A Pending JPH03200348A (en) 1987-10-01 1987-10-01 Life time measurement of semiconductor

Country Status (1)

Country Link
JP (1) JPH03200348A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040199A (en) * 1996-11-22 2000-03-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor test structure for estimating defects at isolation edge and test method using the same
JP2017009307A (en) * 2015-06-17 2017-01-12 信越半導体株式会社 Method for evaluating semiconductor substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040199A (en) * 1996-11-22 2000-03-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor test structure for estimating defects at isolation edge and test method using the same
JP2017009307A (en) * 2015-06-17 2017-01-12 信越半導体株式会社 Method for evaluating semiconductor substrate

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