JPH0319988B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory device that enables efficient vector operations in a computer system.

[Technical background of the invention and its problems]

In high-speed computers called supercomputers, various efforts have been made to process vector operations quickly and efficiently. The above vector operation, for example, adds each element A(I) and B(I) of two array data A and B, respectively, to obtain array data C of elements such that C(I)=A(I)+B(I). It is something to seek. This vector operation is performed by performing the same calculation for each element of each of the above vectors, and the operation is broken down into, for example, comparison of exponent parts, digit alignment of mantissa parts, addition processing of mantissa parts, rounding processing, normalization processing, etc. However, the processing is performed sequentially for each element in a pipeline manner. FIG. 1 shows an example of this, and shows how an operation with five pipeline stages is executed six times. This calculation method is called a pipeline method, and when the number of pipeline stages is m, the calculation time (pipeline pitch) at each stage of this pipeline calculation is τ, and the number of data is n, the time required for the calculation is T. becomes T=mτ+(n-1)τ=(m-1)τ+nτ. As is clear from this formula, the number of data n
When there are many, it can be executed in the time of the vector operation (nτ). Furthermore, when the number m of pipeline stages is increased, the pipeline pitch τ
Since the execution time (nτ) can be shortened, the overall computational performance can be improved.

By the way, in order to efficiently execute vector operations using this type of pipeline method, it is necessary to provide the data (each element of the array data) to be used for the operations one after another at each pipeline pitch τ. be. However, vectors used in circuit network analysis, power flow calculations, etc. are so-called super spectra (sparse vectors), and have the property that most of the vector elements are zero (0). That is, the nonzero elements of the super spectrum are, for example, the second
As shown in the figure, it is at most a few percent. For this reason, even if these data are sequentially read out and subjected to pipeline calculation, it is not possible to substantially improve the calculation efficiency. Furthermore, storing such super spectra SA and SB as they are in memory and using them for calculations requires too much memory capacity, which poses a problem.

Therefore, in the past, the super spectrum shown in Figure 2 was
Focusing on the data positions of non-zero elements of SA and SB, the data positions are expressed as index data IA and IB, and for example, as shown in Figure 3, non-zero element data SAN and SBN and their data exist. It is being considered to express it in a dense vector format using indices IA and IB that indicate the position in the vector and use it for vector calculations. In addition, in the dense vector SA shown in the example shown in Fig. 3, the data of the third element of the vector SA is "4", the 120th raw data is "9"...
It shows that.

FIG. 4 is a diagram showing the flow of conventional vector calculation processing using such dense vectors. To briefly explain the flow of this process, there are two parameters I, which sequentially specify the elements of the dense vector,
The index data IA (I), B (J) are read out as data X, Y according to these parameters I, J. And these data X,
When Y are equal, the vectors SA,
Find the data position (address) in SB, and set that address LA,
The data SAN and SBN stored in the LB are read out and given to the pipeline calculation unit to perform the calculation. Thereafter, the parameters I and J are each incremented, and the process moves on to data extraction processing when the data X and Y become equal. Furthermore, if the data X and Y are different in the comparison, the data X or the data Y is incremented according to the magnitude relationship, and a process is performed to find the data where the data L and Y are equal. By repeatedly performing the above processing to extract only the data of non-zero elements having the same index, and sequentially supplying this data to the pipeline calculation unit, the speed of the vector calculation can be increased. It goes without saying that when processing is executed in this manner, the index data must be arranged in ascending order.

However, when performing such processing, it is necessary to compare one index of one vector with most of the indexes of the other vector. In particular, if the indices of the dense vectors are not arranged in ascending order, it becomes necessary to compare each index of one vector with all the indices of the other vector.
Its processing efficiency is very poor. Moreover, since a lot of time is spent on the index comparison process, there is a problem in that it is difficult to sequentially extract data to be used for vector operations in synchronization with the pipeline pitch τ.

Therefore, the present inventors developed the dense vector shown in Fig. 3.
We considered converting SA into a sparse spectrum (sparse vector) format, storing it in memory, and using it for vector calculations (Japanese Patent Application No. 58-50499).
Figure 5 is a schematic diagram of the main parts of a processing device that performs vector calculations by converting vector formats, in which 1 is a data memory that stores vector data SAN and SBN, and 2 is a memory that stores vector data SAN and SBN. An index memory 3 stores index data IA and IB, and a working memory 3 creates a sparse vector from the vector SA. 4 is a counter for sequentially reading data SAN and IA of vector SA from memories 1 and 2, and registers 5 and 6
The storage address of the vector SA in the memories 1 and 2 is initially set. Then, the data indicated by the counter 4 and the data initialized in the registers 5 and 6 are added by adders 7 and 8, respectively, and the memories 1 and 2 are accessed by these data to obtain the data. SAN,
IAs are read in order. At this time, the index data IA is added to the storage start address data WA in the work memory 3 of the sparse vector initialized in the register 10 by the adder 9, and the added data is used as the address designation data of the work memory 3. The data SAN read from the data memory 1 is written to the address. As a result, the data SAN read from the data memory 1 corresponding to the position of the non-zero element of the super spectrum A is stored in the working memory 3. This processing is performed on all elements of the vector SA, and as a result, a vector converted into the format shown in FIG. 2 is obtained in the working memory 3.

Then, the elements of vector SB are read out from data memory 1 and index memory 2 in sequence. Then, the data set in the register 10 is added to the index data IB taken out from the index memory 2, and the working memory 3 is accessed using the data. As a result, from working memory 3, the vector
Data existing at an index equal to index data IB of SB will be read together with each data SBN of the vector SB. As a result, the data SAN and SBN to be subjected to vector calculation are successively supplied to the pipeline calculation unit 11 in order. In this case, the data read from the working memory 3 may include other than non-zero elements of the vector SA, and the "0" data may be a wasteful process for vector calculations. However, even if there is some waste like this, the data SAN and SBN required for vector calculation can be obtained very easily, rapidly and continuously, so compared to the process shown in Fig. 4 described above, The processing efficiency of vector operations is much improved.

By the way, when processing vectors in this way, each time the vector to be processed changes, it is necessary to initialize all of the working memory 3 to zero (0), or to use the address where the data SAN was previously stored. In some cases, it is necessary to reset addresses whose data has not been updated by new data SAN in the current data processing to zero (0). If this reset processing is not performed, when reading the data SBN, the data SAN of the previous vector SA corresponding to the index data IB will be read from the working memory 3, which will have a negative impact on vector calculations. . Therefore, the above reset process cannot be omitted. However, as mentioned above, working memory 3 is a vector
Since the SA is converted into a super spectrum format and stored, the number of addresses is extremely large. Therefore, there is a problem in that a large amount of time is required to reset the data at all of these addresses. Furthermore, searching for the address in the working memory 3 where the data SAN is written and performing reset processing only on that address not only complicates the control, but also requires a lot of processing time for the address. I have a problem that requires . Therefore, in order to solve this problem, it has been considered to provide two working memories in parallel and reset the other memory while one memory is performing the above-mentioned vector processing. There is. However, configuring the device in this manner requires a large capacity memory as the working memory 3, creating a problem in that the hardware becomes large-scale.

[Purpose of the invention]

The present invention has been made in consideration of these circumstances, and its purpose is to easily and efficiently continuously extract elements of a super spectrum to be subjected to vector calculation by pipeline processing. The object of the present invention is to provide a highly practical memory device that can perform the following functions.

[Summary of the invention]

The present invention integrally registers tag information indicating the type of data together with the data in a memory that stores data to be subjected to arithmetic processing, and when the data and tag information are read from this memory, the tag Compare the information with the tag information specified for reading, and when these tag information are equal, output the data read from the memory, and when the two tag information are different, replace it with the data read from the memory. The data specified in advance is output.

Specifically, different tag information is set for each vector data, the data of the vector is registered together with the tag information in the working memory, and when the data is read from the working memory, the tag information is specified. The above-mentioned data is output only when , and in other cases, specific data, such as zero (0) data, is output instead of the above-mentioned data.

〔Effect of the invention〕

Thus, according to the present invention, the data read from the working memory according to the index data IB of the vector SB is the target vector A (vector
Even if it is data other than SAN (a vector obtained by converting SA into a super spectrum), it is converted to, for example, zero (0) data and output by the tag information comparison process, so it is ultimately not effective for vector calculation. It becomes possible to output only the data SAN of the vector SA. Moreover, when writing vector data to the working memory, simply write the tag information that identifies the vector at the same time, and the data output will be controlled by the tag information, eliminating the need for any troublesome reset processing. Data processing efficiency can be significantly improved. That is, it is possible to equivalently reset the data already written in the working memory other than the vector data written in the working memory to zero (0), and it is possible to execute processing on the super spectrum extremely efficiently. becomes. Further, data can be efficiently and continuously provided to pipeline processing, and a great practical effect can be achieved.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 6 shows a schematic configuration of the main parts of the apparatus according to the embodiment, and numeral 3 in the figure corresponds to the working memory shown in FIG. 5. This working memory 3 is addressed by index data, and the memory area is divided into a data section 3a and a tag section 3b. The tag section 3b is the data section 3a.
The tag information set for each vector SA to which the vector data SAN registered in
It is registered in correspondence with the SAN. As described above, this tag information is set in the tag register 12 corresponding to the vector to be written into the working memory 3, and is given to the working memory 3 from the tag register 12. Writing of data into the working memory 3 is performed as described above. That is, the data SAN of the dense vector SA as shown in FIG.
This is done by writing the index data IA to the corresponding address of the working memory 3, respectively. At this time, the tag data set in the tag register 12 is transferred to the tag section 3b of the working memory 3.
are simultaneously written to the addresses indicated by the index data IA. As a result, the vector SA is developed in the form of a super spectrum in the working memory 3, and is written in a form in which tag data is attached to each non-zero element data. It goes without saying that when data of another new vector is written into the working memory 3, the value of the tag data is changed before the writing is performed.

That is, for example, as shown in the configuration of the working memory 3 in FIG. 7, tag data "1" is set for one vector and the data is written in the working memory 3.
When the processing is finished and the data of the next vector is written into the working memory 3, the value of the tag data is changed to, for example, "2" as described above. Then, vector data is written along with the tag data to the corresponding address in the working memory 3 according to the vector index. At this time, even if the previous vector data has already been written to the address specified by the index data, the data that has already been registered at that address will be replaced by the newly written data. It will be updated. Then, tag data "2", which is completely different from before, is attached to the addresses in the working memory 3 to which new vector data is written, including the addresses where the data has been updated in this way. That will happen.

Therefore, when the vector data registered in the working memory 3 in this manner is to be output one after another, the tag data indicating the vector is set in the tag register 12, and in other words, the tag data used when writing the data is changed. done without doing anything. Then, the index data IB of the vector SB to be used in the vector calculation is read out from the working memory 3 together with the data SAN of the vector SA. At this time, the tag part 3 of the working memory 3
The tag data read from B is compared with the tag data set in the tag register 12 by a comparator 13. When the two tag data are equal, the comparator 13 outputs a gate open signal to the gate circuit 14 to open the gate, and outputs the data read from the data section 3a of the working memory 3 together with the tag data. Then, this is given to the pipeline calculation section 11. In addition, the comparator 13
generates a gate open signal to the gate circuit 14 when the two tag data are different, and prevents output of the data read from the data section 3a to the pipeline calculation section 11. As a result, zero (0) data is output to the pipeline calculation unit 11 instead of the data read from the working memory. After all of the corresponding data of the vector SA is read from the working memory 3 in accordance with the index data IB of the vector SB in this way, the data of the next vector is written to the working memory 3 in order to perform the next vector operation. be exposed. In this case, since the vectors are different, it goes without saying that tag data with different values are used as described above.

According to the device configured as described above,
Even if data other than the elements of the vector SA are read from the working memory 3 according to the index data IB, the data output is prevented by the control of the gate circuit 14 based on the comparison result of the tag information. Therefore, data other than the vector SA is not output. In other words, the vector
Data other than SA is automatically converted to zero (0) data and output, and an equivalent reset is performed here. Therefore, there is no need for reset processing, which has been a problem in the past, and it is possible to significantly improve the processing efficiency.

Note that when all of the tag data prepared in advance is used, it is necessary to use the tag data again. At this time, a problem arises in that vector data corresponding to previously used tag data and vectors corresponding to reused tag data cannot be distinguished. Therefore, in such a case, it is necessary to reset all of the working memory 3 to zero (0), but the frequency of this reset process is extremely low. Specifically, if 8-bit data is used as the tag information, the reset process will be faster than when the working memory 3 is reset each time one vector is processed in the apparatus shown in FIG. The number of times will be reduced to 1/256. Therefore, vector calculation processing including the above-mentioned reset processing can be executed extremely efficiently, and its practical advantages are enormous. It goes without saying that even if memory processing is performed on vectors in this manner, data to be used in vector calculations can be continuously output as shown in FIG. 5 described above.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, if the tag data read from the working memory is different from the specified tag data, zero (0) is set as the prespecified data.
Although the data is output, all "1" data may be output as the previously specified data. In other words, fixed data necessary for vector calculation may be set in advance, and when the tag data differs, this may be output. Even in this case, from the perspective of the pipeline calculation section, it can be considered that the working memory has been equally reset. Further, the number of bits of tag information used in this process, the number of elements of the vector to be processed, etc. may be determined according to the calculation specifications of the device. It goes without saying that the present invention can be modified and implemented in various ways without departing from the spirit thereof.

[Brief explanation of the drawing]

Figure 1 is a diagram schematically showing pipeline processing of vector operations, Figure 2 is a diagram showing the data structure of a super spectrum, Figure 3 is a diagram showing the data structure of a dense vector whose structure has been transformed, and Figure 4 is a diagram showing the data structure of a dense vector that has been structurally transformed. FIG. 5 is a diagram showing the flow of conventional vector data processing; FIG. 5 is a block diagram of the previously proposed vector processing device; FIG. 6 is a schematic diagram of the memory device according to an embodiment of the present invention;
The figure is a diagram showing the structure of the working memory in the same embodiment. 3... Working memory, 3a... Data section, 3b...
...Tag section, 11...Pipeline operation section, 12...
...Tag register, 13...Comparator, 14...Gate circuit.

Claims (1)

[Scope of Claims] 1. A memory for registering one vector data to be operated on consisting of non-zero elements together with tag information for identifying the vector, and an address for the other vector data to be operated on consisting of non-zero elements. Accordingly, a means for reading the duct information together with the data from the memory, and a means for comparing the duct information read from the memory with the duct information of one of the vectors to be calculated, and when these duct information are equal, the above-mentioned duct information is calculated. outputting data read from the memory, and outputting zero data in place of the data read from the memory when the two pieces of data are different;
What is claimed is: 1. A memory device characterized by comprising means for performing calculations. 2. The memory device according to claim 1, wherein the one vector data and the other vector data to be operated on, which are composed of non-zero elements, are obtained by converting a sparse vector into a dense vector format. 3. The memory device according to claim 1, wherein when different vector data is registered in the memory, its vector information is also changed and registered.