JPH03198509A - High frequency power amplifier circuit - Google Patents

Abstract

PURPOSE:To attain stable operation against the dispersion of transistor(TR) characteristic at manufacture and against a temperature change by providing a 2nd field effect TR manufactured by the same condition as that of a 1st field effect TR deciding a bias voltage in addition to the 1st field effect TR implementing power amplification. CONSTITUTION:The amplifier circuit consists of a power amplifier section 5, a bias circuit section 6 and a buffer amplifier section 7. The bias circuit section 6 consists of a field effect TR 21 manufactured in the same condition of the shape, conduction type of the diffusion layer and the impurity concentration or the like as those of field effect TRs 8, 9, 10 of the power amplifier section 5 and resistors 22, 23, 24 to constitute a voltage negative feedback type bias circuit, then a bias voltage obtaining the optimum operating current of the TR 21 is fed to a gate of the TR 21. The buffer amplifier section 7 applies a voltage of the same voltage as the gate voltage of the TR 21 to each gate of the TRs 8, 9, 10 via the resistors 12, 15, 18. Thus, the TRs 8, 9, 10 are operated in the optimum condition.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a high frequency power amplification circuit constituted by field effect transistors, and more particularly to a high frequency power amplification circuit in which the field effect transistors are biased to a predetermined operating point.

[Prior Art] Conventionally, three methods shown in FIGS. 2(a) to 2(C) are known as bias setting methods for this type of high-frequency power amplifier circuit.

FIG. 2(a) is a circuit diagram showing a conventional voltage negative feedback bias type high frequency power amplifier circuit.

The gate of the field effect transistor 34 is connected to the input terminal 30 via a capacitor 35, and is also connected to the bias power supply terminal 33 via a bias voltage supply resistor 38. The source of this transistor 34 is connected to ground 40, and the drain is connected to the power supply terminal 32 via a load resistor 36 and to the output terminal 31 via a capacitor 39.

Furthermore, a feedback resistor 37 is interposed between the gate and drain of the transistor 34.

In the high frequency power amplifier circuit configured in this manner, a power supply voltage vDD is applied to the power supply terminal 32, and a bias voltage V is applied to the bias power supply terminal 33. . When V! is applied, the transistor 34 receives the input signal V! input to the input terminal 3o. The AC component is power amplified and an output signal Vo is output to the output terminal 31 via the capacitor 39. In this voltage negative feedback method, the bias voltage of the transistor 34 is the voltage V of the bias power supply terminal 33. . It is also determined by the drain voltage fed back through the resistor 37.

This voltage negative feedback bias type high frequency power amplifier circuit has the advantage of being able to operate stably despite being affected by variations in transistor characteristics during manufacturing and temperature changes.

FIG. 2(b) is a circuit diagram showing a conventional self-bias type high frequency power amplifier circuit.

The gate of field effect transistor 44 is connected to input terminal 41 via capacitor 45 .

Further, a resistor 47 is inserted between the gate of the transistor 44 and the ground 5o. The source of this transistor 44 is connected to ground 5o via a resistor 48. The drain of this transistor 44 is connected to the power supply terminal 43 via an inductance 46, and
It is connected to the output terminal 42 via a capacitor 49.

In the high frequency power amplification circuit configured in this way, when the power supply voltage vDD is applied to the power supply terminal 43, the transistor 44 amplifies the power of the AC component of the input signal V inputted to the input terminal 41. Output terminal 4
2 is the output signal V. Output. In this self-biasing method, the voltage drop of the current flowing from the source to ground 50 across resistor 48 becomes the bias voltage of transistor 44 .

This self-biasing high-frequency power amplifier circuit has the advantage of not requiring a bias power supply.

FIG. 2(C) is a circuit diagram showing a conventional fixed bias type high frequency power amplifier circuit.

The gate of the field effect transistor 55 is connected to the input terminal 51 via a capacitor 56, and also connected to a resistor 58.
It is connected to the bias power supply terminal 54 via. Further, the source of this transistor 55 is connected to the ground θO, the drain is connected to the power supply terminal 53 via the inductance 57, and the output terminal 52 is connected via the capacitor 59.

In the high frequency power amplifier circuit configured in this way, when the power supply voltage van is applied to the power supply terminal 53 and the bias voltage Voo is applied to the bias power supply terminal 54,
The transistor 55 power amplifies the AC component of the input signal V□ input to the input terminal 51, and outputs the signal V to the output terminal 52 via the capacitor 59. Output. In this fixed bias method, the bias voltage of the transistor 55 is the voltage V supplied from the bias power supply terminal 54. It becomes 0.

This fixed bias type high frequency power amplifier circuit has the advantage of high utilization of the power supply.

[Problems to be Solved by the Invention] However, all conventional high frequency power amplifier circuits have the following drawbacks.

In the voltage negative feedback bias type high frequency power amplifier circuit, when attempting to amplify a large amount of power, it is necessary to flow a large current through the resistor 36, which deteriorates the utilization rate of the power supply voltage and causes a decrease in output power. Further, since this resistor 36 becomes a load on the field effect transistor 34, power loss is large.

Furthermore, in a self-biasing high frequency power amplifier circuit, when it is necessary to flow a large current through the transistor 44, the resistance value of the resistor 48 inserted between the source and the ground 50 must be set to an extremely small value. This makes manufacturing difficult and reduces circuit stability. Another disadvantage is that the resistor 48 reduces the gain of the transistor 44.

Furthermore, in the case of a fixed bias type high frequency power amplifier circuit, it is necessary to supply the optimum gate bias voltage of the transistor 55 from the outside, and furthermore, this optimum gate bias voltage varies depending on variations in the manufacturing process of the transistors and temperature changes. Therefore, the adjustment is complicated. In particular, when the power amplification circuit is composed of a plurality of transistors, it is necessary to adjust the gate voltage for each transistor due to manufacturing variations and temperature changes of each transistor, which is extremely complicated.

The present invention has been made in view of such problems, and includes:
Provides a high-frequency power amplifier circuit that suppresses power loss, output power decrease, and gain decrease, has a high utilization rate of power supply voltage, and can easily realize stable operation against manufacturing variations and temperature changes. The purpose is to

[Means for Solving the Problems] The high frequency power amplifier circuit according to the present invention includes a first field effect transistor that power amplifies an input signal input to its gate, and a first field effect transistor that is operated under the same conditions as the first field effect transistor. a second field effect transistor formed and having its source connected to the first power supply terminal; and a first field effect transistor interposed between the drain of the second field effect transistor and the second power supply terminal. a second resistor inserted between a resistor and a drain and a gate of the second field effect transistor; a second resistor inserted between a gate of the second field effect transistor and a bias voltage supply terminal; The device is characterized in that it includes a third resistor and a buffer amplifier that inputs the gate voltage of the second transistor and supplies a bias voltage to the gate of the first field effect transistor.

[Operations] The present invention includes a second field effect transistor for determining a bias voltage in addition to the first field effect transistor for power amplification.

Since the second field effect transistor is formed on the same substrate and under the same conditions as the first field effect transistor, its electrical characteristics are similar to those of the first field effect transistor.

Since this second field effect transistor forms a voltage negative feedback bias circuit, this voltage negative feedback bias circuit brings this transistor into the optimal operating state for the gate of the second transistor. By applying such a bias voltage, the effects of temperature changes and manufacturing variations are suppressed. This bias voltage is supplied to the gate of the first field effect transistor for power amplification via a buffer amplifier. As mentioned above, since this first field effect transistor has the same characteristics as the second field effect transistor, by applying the optimum bias voltage of the second field effect transistor, the first field effect transistor also has the same characteristics. be in optimal condition. Thereby, changes in characteristics due to temperature or the like can be avoided.

Further, in the present invention, as described above, in order to apply a bias voltage directly to the gate of the first field effect transistor for power amplification, the source or drain of the first transistor and the first or second power supply There is no need to interpose a resistor between the terminal and the terminal.

This avoids power loss and gain reduction.

Furthermore, since the first field effect transistor that performs power amplification is provided separately from the bias circuit, deterioration of the power supply voltage utilization rate, increase in power loss, decrease in output power, decrease in gain, etc. can be avoided. be able to.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a high frequency power amplifier circuit according to an embodiment of the present invention.

This high frequency power amplification circuit includes a power amplification section 5, a bias circuit section 6, and a buffer amplification section 7. In addition,
The power amplifying section 5 and the bias circuit section 6 are formed on the same semiconductor chip.

The power amplification section 5 includes three field effect transistors 8°9.1
This is a three-stage amplifier configured by 0. Input terminal 1 is connected to the gate of first-stage transistor 8 of power amplifying section 5 via capacitor 11 . This transistor 8
Its source is connected to ground 27, and its drain is connected to power supply terminal 3 via inductance 13 and to the gate of transistor 9 in the next stage via capacitor 14. This transistor 9 also has its source connected to the ground 27, and its drain connected to the power supply terminal 3 via an inductance 16, as well as to the gate of the next stage transistor 10 via a capacitor 17. .

This transistor 10 also has its source connected to ground 27, and its drain connected to power supply terminal 3 via inductance 19 and to output terminal 2 via capacitor 20.

The gates of these transistors 8.9.10 are connected to the output of a buffer amplifier 7, which will be described later, via resistors 12 and 15.18 having high resistance values, respectively.

The bias circuit section 6 includes a transistor 8. of the power amplification section 5.
9.10, and a field effect transistor 21 formed under the same conditions as the shape, the conductivity type of the diffusion layer, the impurity concentration, etc.
It is composed of resistors 22, 23, and 24. The source of the transistor 21 is connected to ground 27, and the drain is connected to the power supply terminal 3 via a load resistor 22.

Further, the gate of this transistor 21 is connected to the bias power supply terminal 4 via a bias voltage supply resistor 24, and is also connected to the non-inverting input section of the buffer amplification section 7. Furthermore, a feedback resistor 23 is inserted between the gate and drain of this transistor 21. This constitutes a voltage negative feedback type bias circuit.

The buffer amplifier section 7 includes a differential amplifier 25 and a resistor 26. This resistor 26 is inserted between the inverting input section and the output of the differential amplifier 25. Further, the non-inverting input section of the differential amplifier 25 is connected to the gate of the transistor 21 of the bias circuit section 6, as described above. Furthermore, the output of this differential amplifier 25 is
2, 15, and 18 to the respective gates of transistors 8, 9, and 10.

In the high frequency power amplifier circuit according to this embodiment having the above configuration, the power supply voltage vI)D is applied to the power supply terminal 3, and the bias voltage V is applied to the bias power supply terminal 4. When 0 is applied, the bias circuit section 6 constitutes a voltage negative feedback type bias circuit in which the bias voltage of the transistor 21 is determined by the drain voltage of the transistor 21 and the voltage VOO of the bias power supply terminal 4. A bias voltage that provides an optimum operating current of is applied to the gate of transistor 21.

The buffer amplifier section 7 applies a voltage having the same potential as the gate voltage of the transistor 21 to each gate of the transistors 8, 9, and 10 via the resistors 12, 15, and 18. Since these transistors 8, 9, and 10 are formed under the same conditions as the transistor 21 of the bias circuit section 6, their characteristics against temperature changes, manufacturing variations, etc. are also the same as the transistor 21. Therefore, transistor 2
By being biased to the same potential as the gate voltage of 1, these transistors 8, 9, and 10 also operate under optimal conditions. As a result, the input signal V□ input to the input terminal 1 is power amplified, and the output signal v0 is output to the output terminal 2.

As described above, the high frequency power amplifier circuit according to this embodiment has one of a plurality of transistors formed under the same conditions.
A voltage negative feedback type bias circuit is formed by these transistors, and the bias voltage obtained by this bias circuit is supplied as a bias voltage to other power amplifying transistors. Therefore, the same effect as if each transistor had a voltage negative feedback type bias circuit can be obtained.

Further, the circuit for supplying bias voltage to the transistors 8, 9, and 10 of the power amplifying section 5, that is, the resistor 12.degree. Since there is no interposition between the source and drain of the transistor 8.9.10 and the ground 27 or the power supply terminal 3, the utilization rate of the power supply voltage is high, and power loss, reduction in output power, and reduction in gain are avoided. be able to.

[Effects of the Invention] As explained above, according to the present invention, the first
The second field effect transistor was formed under the same conditions as the field effect transistor.
A voltage negative feedback bias circuit is formed by the field effect transistor, and since the bias voltage of this second field effect transistor is supplied to the first field effect transistor via a buffer amplifier, temperature changes and manufacturing process Stable operation despite variations in transistor characteristics.

In addition, since there is no need to interpose a resistor between the source or drain of the first field effect transistor for power amplification and the power supply, the power supply utilization rate is high, resulting in power loss, decrease in output power, and decrease in gain. is suppressed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a high frequency power amplifier circuit according to an embodiment of the present invention, and FIGS. 2(a) to 2(c) are circuit diagrams showing conventional high frequency power amplifier circuits. 1.30, 41, 51; Input terminal, 2.31°42.5
2; Output terminal, 3, 32, 43, 53; Power terminal, 4,
33, 54; bias power supply terminal, 5; power amplification section, 6;
Bias circuit section, 7; buffer amplifier section, 8.9, 10.21
, 34, 44, 55; field effect transistor, 11, 1
4, 17.20.35.39, 45.5B, 59; Capacitor, 12.15, 18.22, 23, 24.26'
,'36.37.38.47.48.58;Resistance, 1
3゜1B, 19.46.57; Inductance, 25゜27.40.50, 80; Ground

Claims (1)

[Claims] (1) A first field effect transistor for power amplifying an input signal input to its gate; and a first field effect transistor formed under the same conditions as the first field effect transistor and having its source connected to a first power supply terminal. a first resistor inserted between the drain of the second field effect transistor and a second power supply terminal; and a first resistor inserted between the drain and the gate of the second field effect transistor; a second resistor inserted between, a third resistor inserted between the gate of the second field effect transistor and the bias voltage supply terminal, and inputting the gate voltage of the second transistor; and a buffer amplifier that supplies a bias voltage to the gate of the first field effect transistor.