JP4471789B2 - High frequency semiconductor circuit - Google Patents

Description

  The present invention relates to a configuration of a bias circuit for setting an operating point of a circuit such as a FET, HEMT, or MMIC used in a high-frequency semiconductor circuit, in particular, a transmitter that transmits a high-frequency signal such as a microwave.

Conventionally, FET (field effect transistor), HEMT (High Electron Mobility) are used to amplify RF (high frequency) signals.
Transistors such as transistors, or MMICs (Microwave Monolithic ICs) that integrate these transistors are used, and bias circuits that set and adjust the operating points of these FET, HEMT, and MMIC circuits There are a fixed bias circuit, a self-bias circuit, and an auto-bias circuit. For example, a low-noise amplifier with a low current mainly uses a self-bias circuit or an auto-bias circuit, and a high-frequency power amplifier that requires a high output current and linearity mainly uses a fixed-bias circuit or an auto-bias circuit. .

  FIG. 5 shows a configuration of a high-frequency semiconductor circuit in which a fixed bias circuit is applied to an FET (or HEMT). As shown in the figure, between an RF signal input terminal RFin and an output terminal RFout, For example, an amplification FET 41, DC cut capacitors 43 and 44, and matching circuits 45 and 46 are arranged. A variable voltage source 47 for variably adjusting the gate voltage is connected to the gate of the FET 41. According to such a fixed bias circuit, the gate voltage of the FET 41 is adjusted at room temperature by the variable voltage source 47 so that the recommended operating current value set at the time of device design is obtained.

  FIG. 6 shows the configuration of a high-frequency semiconductor circuit in which a self-bias circuit is applied to an FET (or HEMT). As shown in the figure, the gate of the FET 41 is grounded in a direct current manner, and the source / ground is grounded. A resistor 51 and a capacitor 52 are inserted between them. According to such a self-bias circuit, the drain current of the FET 41 can be adjusted by making the gate potential relatively lower than the source potential by the current flowing through the resistance 51 between the source and the ground.

  FIG. 7 shows a configuration of a high-frequency semiconductor circuit in which an auto bias circuit is applied to an FET (or HEMT). As shown in the figure, a resistor 54 for detecting the drain current of the FET 41, a reference voltage, and the like. Voltage divider resistors 55 and 56, and a comparator 57 that compares the drain current with a reference voltage. According to this auto-bias circuit, the drain current of the FET 41 is detected, and a voltage corresponding to the change in the drain current is fed back from the comparator 57 to adjust the gate voltage so that the drain current becomes the recommended operating current value. Controlled.

FIG. 4 is a characteristic diagram showing the operation of the FET. As shown in this figure, in the FET or HEMT, a change in the voltage applied to the gate appears as a change in the amplitude of the drain current. Is done. When used as an amplifier, by setting the DC operating point (bias point when no RF signal is input) to about half of the saturation current value (I _DSS ), an amplifier with low distortion characteristics and good linearity can be realized. In this case, the optimum operating point has a substantially proportional relationship with the saturation current value, and the actual operating point is set in a range of about I _DSS × 0.4 to I _DSS × 0.7 depending on the characteristic of the device. In many cases, when this operating point deviates from the optimum operating point, the cross modulation distortion characteristic deteriorates.
JP 11-195935 A Japanese Patent Laid-Open No. 2-151109

  By the way, the setting of the current value of the operating point in the high-frequency semiconductor circuit such as a conventional FET, HEMT, MMIC, etc. is determined from the device design value or the average value of data of several lots, and the value is used in all devices. Is common. However, the DC (direct current) characteristics of individual devices have variations and distributions within a process lot or a wafer, and even when set to a recommended operating point, the operating point is not always optimal for each device.

  In addition, since the DC characteristics of the device fluctuate with temperature, a fixed bias circuit in which the gate voltage is set to a constant value at room temperature, or an auto bias circuit configured with a feedback circuit in which the drain current becomes a constant current, There is a problem that the operating point is deviated from the optimum operating point due to the change of the above, and the original characteristics of the device cannot be sufficiently extracted.

  The present invention has been made in view of the above problems, and its purpose is to set an optimum operating point for each device even when there are variations in process lots, wafers, or temperature fluctuations. An object of the present invention is to provide a high-frequency semiconductor circuit that can bring out the ability of the above.

In order to achieve the above object, an invention according to claim 1 is formed to monitor a drain current of a main transistor formed with a main transistor for inputting a high-frequency signal and a state separated from the main transistor at a high frequency. A monitor transistor having a gate width smaller than the gate width; a power supply for supplying a drain current to the main transistor; and a first operating current setting first inserted between the power supply and the drain of the main transistor. A feedback bias circuit provided with a resistor, a power source for supplying current to the monitoring transistor, and a second resistor for operating current setting inserted in series between the power source and the drain of the monitoring transistor; If provided, to set the operating point of the main transistor to x% of the saturation current value, the feedback bias The first value _{R 1} of the resistor value _{R 2} of the second resistor of the road, Wg ₁ the gate width of the main transistor, the gate width of the monitor transistor and _{Wg 2, R 1 / R 2} = (Wg 2 / Wg ₁ ) / (x / 100) is selected, and the feedback bias circuit controls the gate voltage of the main transistor so that the drain voltages of the main transistor and the monitoring transistor are equal. And The first resistor serves to detect the drain current, and the second resistor serves to detect the saturation current.

According to the above configuration, the main transistor of the Gate width Wg ₁ (FET), a monitor transistor having a gate width Wg ₂ is formed on the same semiconductor chip in a state of being separated from the RF signal. In this case, the saturation current _{I DSS 1} of the main transistor, when the saturation current of the monitor transistor and _{I DSS2,} obtained in _{I DSS1 = I DSS2 × (Wg} 1 / Wg 2), the operating point of the main transistor (drain current) Is set to 1/2 of this I _DSS1 (in the case of 50%), for example. In the feedback bias circuit, the saturation current of the monitoring transistor is detected, and even if this saturation current changes, the drain current of the main transistor is always at the operating point (1/2) I _DSS1. The gate voltage is adjusted and controlled so that the optimum operating point is set.

That is , the values of the first resistor and the second resistor are selected according to the gate width and the ratio (%) of the operating point (current value) to the saturation current value, so that the drain voltages of the main transistor and the monitoring transistor are equal. By controlling the gate voltage, the optimum operating point can always be obtained.

  According to the present invention, the saturation current of the main transistor is monitored by the monitoring transistor, and the gate voltage is controlled so that the operating point is set based on this saturation current. Even if it occurs, the optimum operating point of each device can be set, and the original capability of the device can be maximized. In particular, a circuit having stable P1 dB output power characteristics and distortion characteristics can be realized, and an improvement in yield can be expected.

  In addition, in devices such as FETs, the Vg-Id characteristics and saturation current change with temperature, so even when set to the optimum operating point at room temperature, the linearity deteriorates because it deviates from the optimum point at low or high temperatures. In the present invention, the optimum operating point is set even when there is such a temperature fluctuation, so that it is possible to suppress degradation of characteristics due to temperature and obtain an amplifier circuit having excellent linearity in a wide temperature range. Become.

  FIG. 1 shows the configuration of a high-frequency semiconductor circuit according to a first embodiment of the present invention, which uses a depletion mode type FET. In FIG. 1, an amplification main FET 1, DC cut capacitors 3 and 4, and matching circuits 5 and 6 are connected between an RF signal input terminal RFin and an output terminal RFout, and the same chip (CHIP) as the main FET 1 is connected. A monitoring FET 2 is formed thereon. The monitoring FET 2 is separated from the main FET 1 at a high frequency, and is configured such that a saturation current can be detected in a DC manner by grounding the base and the source.

  Further, a power supply 8 (+ V) for detecting the drain current of the main FET 1 and the saturation current of the monitoring FET 2 is provided as a feedback bias circuit, and the drain of the main FET 1 has a high frequency between the power supply 8 and the drain. The first resistor 11 for setting the operating point (operating current) (which also serves to detect the drain current) is provided, and the drain current is determined by the voltage drop of the first resistor 11. And the change is detected. A capacitor 12 is disposed between the power supply side of the inductor 10 and the ground. Further, a second resistor 14 is provided between the monitoring FET 2 and the power supply 8 to set an operating point (which also serves to detect a saturation current). The saturation current and its change are detected by the amount of drop.

  A comparator 15 that compares the voltage at the connection point between the drain of the monitoring FET 2 and the second resistor 14 and the voltage at the connection point between the inductor 10 and the first resistor 11 and outputs a control voltage to the gate of the main FET 1 is provided. A high frequency cut inductor 16 is provided between the comparator 15 and the gate of the main FET 1, and a capacitor 17 is disposed between the comparator side of the inductor 16 and the ground.

Then, the value _{R 2} of the values _{R 1} and the second resistor 14 of the first resistor 11 mainly FET1 Wg ₁ the gate width of, Wg ₂ the gate width of the monitoring FET2, the ratio of the operating point settings for saturation current If x%, R ₁ / R ₂
= Select so that the ratio is (Wg ₂ / Wg ₁ ) / (x / 100). For example, when the voltage of the power supply 8 is 6 V, the gate width Wg ₂ of the monitoring FET ₂ is 50 μm, the saturation current is 50 mA, and the gate width Wg ₁ of the main FET ₁ is 600 μm, the saturation current of the main FET ₁ is proportional to the gate width. 50 mA × (600 μm / 50 μm) = 600 mA. When setting the operating point to 50%, R ₁ / R ₂
= (50/600) / (50/100) = 1/6. Here, since the operating point current value of the main FET 1 is 50% of 600 mA, it is 300 mA. When the amount of drop in the drain voltage of the main FET 1 is, for example, 0.1 V or less, the value R ₁ of the first resistor 11 is 0.1V / 300 mA≈333 mΩ, and the value R ₂ of the second resistor 14 is set to R ₁ × 6 = 2Ω. The value R ₂ of the values R ₁ and the second resistor 14 of the first resistor 11 is preferably the drain voltage is a small resistance value so as not to decrease.

Thus, by setting the values R ₁ and R ₂ of the first resistor 11 and the second resistor 14, the drain voltage of the monitoring FET 2 becomes 6V− (2Ω × 50 mA) = 5.9V, Since the drain current (operating point) of the FET 1 is 300 mA (≈0.1 V / 333 mΩ), the drain voltage of the main FET 1 is 5.9 V. In the first embodiment, by controlling the gate voltage so that the drain voltages of the monitoring FET 2 and the main FET 1 are equal, it is possible to always realize an operating point of 50% of the saturation current (this value is arbitrary).

  That is, assuming that the saturation current detected by the monitoring FET 2 has changed to 55 mA due to temperature fluctuation, for example, the saturation current of the main FET 1 is 55 mA × (600 μm / 50 μm) = 660 mA. The drain voltage of the monitoring FET 2 is 6V− (2Ω × 55 mA) = 5.89 V, and the gate voltage is controlled by the comparator 15 so that the drain voltage of the main FET 1 becomes 5.89 V. Thus, the operating point current is (6V-5.89V) ÷ 333 mΩ≈330 mA. This operating point current corresponds to 50% of the saturation current 660 mA of the main FET 1 at the time of temperature variation, and even when the temperature variation occurs, the operating point current is always maintained at 50% of the saturation current. This is the same even when the characteristics of the main FET 1 vary among individual devices, and it is possible to always set the optimum operating point of each device.

As described above, in the first embodiment, the values R ₁ and R ₂ of the first resistor 11 and the second resistor 14 are selected according to the gate width and the ratio (%) of the operating point, and the monitoring FET 2 and the main FET 1 Although the gate voltage of the main FET 1 is controlled so that the drain voltages are equal, the saturation current (and its change) of the monitoring FET 2 is detected by the current adjustment / setting means of another configuration, and based on this Thus, it is possible to adjust the gate voltage so that the drain current of the main FET 1 changes, and to always maintain the optimum operating point set in the main FET 1.

  FIG. 4 shows the general characteristics of an FET with the drain voltage in the positive direction of the X axis, the gate voltage in the negative direction, and the drain current in the Y axis. The graph on the right half shows the gate voltage. The graph shows a change in drain current when the drain voltage is raised at a certain point, measured at several gate voltages. The locus of the voltage current (AC load line) when a high-frequency signal is applied is changed for the input voltage. Are displayed in layers. Further, the graph of the left half shows the change of the drain current with respect to the gate voltage, and the input voltage waveform shown in the left half is the output waveform shown in the right half.

  FIG. 2 shows the configuration of a second embodiment applied to an MMIC provided with a plurality of FETs. In the second embodiment, two amplification main FETs 1A and 1B are arranged between an RF signal input terminal RFin and an output terminal RFout, and are separated from the main FETs 1A and 1B in terms of high frequency. The FET 2A is formed on the same MMIC chip (CHIP). Also, DC cut capacitors 19a to 19c and matching circuits 20a to 20d are connected.

  Similarly to the first embodiment, in order to detect the saturation current of the monitoring FET 2A as a voltage, a power source 26 and a first resistor 27 are provided to detect both the drain currents of the main FETs 1A and 1B as a voltage. In addition, a second resistor 28 connected to the power source 26 is provided, and a comparator 29 for controlling the gate voltages of the main FETs 1A and 1B by comparing both the detected voltages is disposed. Further, inductors 22a to 22d and capacitors 23a to 23d are provided in the MMIC chip, and capacitors 24a and 24b and inductors 25a and 25b are arranged.

  In the case of the second embodiment, the values of the first resistor 27 and the second resistor 28 for setting the operating current are set to the ratio of the total gate width of the main FETs 1A and 1B to the gate width of the monitoring FET 2A and the operation. By selecting according to the ratio of the point to the saturation current value, the gate voltages of the main FETs 1A and 1B are controlled so that the drain voltages of the monitoring FET 2A and the main FETs 1A and 1B are equal, as in the first embodiment.

  FIG. 3 shows the configuration of a third embodiment applied to an enhancement type FET. In the third embodiment, the main FET 1C and the monitoring FET 2C are of the enhancement type. Resistors 31 and 32 for dividing the voltage of the power supply 8 and supplying a positive constant voltage are provided at the gate of the monitoring FET 2C. The resistors 31 and 32 distribute the voltage of the power supply 8 by resistance distribution. As a result, a gate voltage for allowing a saturation current value to flow through the monitoring FET 2C is set. Other configurations are the same as those of the first embodiment.

  In the third embodiment as well, by detecting the saturation current of the monitoring FET 2C and indirectly monitoring the saturation current of the main FET 1C, even if there is a temperature variation or individual difference, the saturation current in the main FET 1C is increased. On the other hand, it is possible to always obtain an optimum operating point at a predetermined ratio.

  As a high output FET, HEMT, MMIC device, it can be applied to a microwave radio transmitter, a satellite communication transmitter, a ground communication transmitter, and the like.

It is a figure which shows the structure of the high frequency semiconductor circuit which concerns on 1st Example of this invention. It is a figure which shows the structure of the high frequency semiconductor circuit of 2nd Example. It is a figure which shows the structure of the high frequency semiconductor circuit of 3rd Example. It is a graph which shows the IV characteristic and input-output waveform of FET. It is a figure which shows the structure of the fixed bias circuit applied to the conventional FET. It is a figure which shows the structure of the self-bias circuit applied to the conventional FET. It is a figure which shows the structure of the auto bias circuit applied to the conventional FET.

Explanation of symbols

1, 1A, 1B, 1C ... main FET,
2, 2A, 2C ... FET for monitoring,
8, 26 ... power supply,
11, 27 ... 1st resistance, 14, 28 ... 2nd resistance,
15, 29, 57 ... comparator 41 ... FET.

Claims (1)

A main transistor for inputting a high-frequency signal;
A monitoring transistor formed in a state separated from the main transistor at a high frequency and having a gate width smaller than the gate width for monitoring the drain current of the main transistor;
A power source for supplying a drain current to the main transistor, a first resistor for operating current setting inserted in series between the power source and the drain of the main transistor, a power source for supplying a current to the monitoring transistor, And a feedback bias circuit provided with a second resistor for setting an operating current inserted in series between the power supply and the drain of the monitor transistor,
When the operating point of the main transistor is set to x% of the saturation current value, the first resistance value R ₁ and the second resistance value R ₂ of the feedback bias circuit, the gate width of the main transistor Wg ₁ , and the monitor If the gate width of the transistor is Wg ₂ ,
R ₁ / R ₂ = (Wg ₂ / Wg ₁ ) / (x / 100)
Selected to satisfy
The feedback bias circuit is a high-frequency semiconductor circuit that controls the gate voltage of the main transistor so that the drain voltages of the main transistor and the monitoring transistor are equal .

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