JPH03198429A - Input level deciding circuit for a/d converter - Google Patents

Input level deciding circuit for a/d converter

Info

Publication number
JPH03198429A
JPH03198429A JP1341448A JP34144889A JPH03198429A JP H03198429 A JPH03198429 A JP H03198429A JP 1341448 A JP1341448 A JP 1341448A JP 34144889 A JP34144889 A JP 34144889A JP H03198429 A JPH03198429 A JP H03198429A
Authority
JP
Japan
Prior art keywords
converter
signal
input
digital signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1341448A
Other languages
Japanese (ja)
Inventor
Masamichi Fujimoto
藤本 正道
Hiroko Yamabe
山辺 裕子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1341448A priority Critical patent/JPH03198429A/en
Publication of JPH03198429A publication Critical patent/JPH03198429A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905Exception handling
    • G06F7/4991Overflow or underflow

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Picture Signal Circuits (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To easily and accurately adjust the input level of an A/D converter by detecting the maximum value and the minimum value of the output signal of the A/D converter, and inverting the result to project the image on a monitor. CONSTITUTION:A device consists of an input terminal 1, an A/D converter 2, a D/A converter 3, logic circuits 4 and 5, and a monitor 6. A maximum value and a minimum value of the digital signal converted by the A/D converter 2 are detected, and the signal is inverted, and this inverted digital signal is converted to an analog signal and is outputted. Thus, the input signal level of the A/D converter 2 is accurately discriminated in real time, and an operator can easily and accurately adjust the input signal level while seeing the image.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、テレビジョン受像機などのようにA/D変
換器を搭載した機器におけるA/D変換器への入力レベ
ルを調整する場合にその入力レベルを判定するように用
いられるA/D変換器の入力レベル判定回路に関するも
のである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to adjusting the input level to an A/D converter in a device equipped with an A/D converter such as a television receiver. The present invention relates to an input level determination circuit of an A/D converter used to determine the input level of the A/D converter.

[従来の技術] fJS4図は従来のA/D変換器の人力レベル判定回路
の構成図であり、同図において、’(1)はアナログ信
号(a)の入力端子、(2)はその入力アナログ信号を
ディジタル信号に変換するA/D変換器、(3)は上記
A/D変換器(2)から出力されるディジタル信号(C
)をアナログ信号に変換するD/A変換器、(4)は変
換されたアナログ信号(b)の出力端子である。
[Prior Art] Figure fJS4 is a configuration diagram of a conventional A/D converter manual level determination circuit. The A/D converter (3) converts an analog signal into a digital signal, and the A/D converter (3) converts the digital signal (C
) to an analog signal, and (4) is an output terminal for the converted analog signal (b).

つぎに、上記構成の動作について説明する。Next, the operation of the above configuration will be explained.

入力端子(1)に第5図(a)で示されるような波形の
アナログビデオ信号を入力すると、その入力されたアナ
ログビデオ信号(a)はA/D変換器(2)によりディ
ジタル信号(e)に変換される。ここで、上記A/D変
換器(2)に入力ηf能なビデオ信号(a)が第5図の
(菫)を上限としくy)を下限とする範囲内のものであ
ると、ディジタル信号(C)は、第5図の(重)の上部
と(りの下部の斜線部が切取られた信号になる。
When an analog video signal with a waveform as shown in FIG. 5(a) is input to the input terminal (1), the input analog video signal (a) is converted into a digital signal (e) by the A/D converter (2). ) is converted to Here, if the video signal (a) that can be input to the A/D converter (2) is within the range between (violet) in FIG. 5 as the upper limit and y) as the lower limit, the digital signal (C) is a signal in which the upper part of (heavy) and the lower part of (ri) in FIG. 5 are cut out.

つぎに、その変換されたディジタル信号(C)はD/A
変換器(3)に入力されて、第5図(b)で示すような
波形のアナログ信号に変換され、出力端子(4)に出力
される。
Next, the converted digital signal (C) is converted into a D/A
The signal is inputted to a converter (3), converted into an analog signal with a waveform as shown in FIG. 5(b), and outputted to an output terminal (4).

ここにおいて、入力信号(a)と同じ波形の出力信号(
b)を得るために、−上記A/D変換器(2)への入力
レベルの調整をおこなう場合、D/A変換器(3)の出
力信号波形をオシロスコープなどで観測しながら1人力
レベルを調整していた。
Here, the output signal (
In order to obtain b), - When adjusting the input level to the A/D converter (2), adjust the level by yourself while observing the output signal waveform of the D/A converter (3) with an oscilloscope, etc. I was adjusting.

[発明が解決しようとする課題] 従来のA/D変換器の入力レベル判定回路は以上のよう
に構成されているので、入出力信号の波形を同一にする
ために入力信号のレベルを正確に調整する場合、D/A
変換器(3)の出力信号波形をオシロスコープなどによ
り観測しながら、入力信号のレベルを調整しなければな
らず、レベル調整が複雑かつ面倒になるという問題があ
った。
[Problems to be Solved by the Invention] Since the input level determination circuit of the conventional A/D converter is configured as described above, it is necessary to accurately determine the level of the input signal in order to make the waveforms of the input and output signals the same. When adjusting, D/A
The level of the input signal must be adjusted while observing the output signal waveform of the converter (3) using an oscilloscope or the like, which poses a problem that level adjustment becomes complicated and troublesome.

この発明は上記のような問題点を解消するためになされ
たもので、オシロスコープなどにより出力信号波形を観
測するという面倒な作業を省いて、A/D変換器の入力
レベルを容易に、かつ正確に調整することができるA/
D変換器の入力レベル判定回路を提供することを目的と
する。
This invention was made to solve the above-mentioned problems, and it is possible to easily and accurately measure the input level of an A/D converter by eliminating the troublesome work of observing the output signal waveform with an oscilloscope or the like. A/
An object of the present invention is to provide an input level determination circuit for a D converter.

[課題を解決するための手段] この発明に係るA/D変換器の入力レベル判定回路は、
A/D変換器で変換されたディジタル信号の最大値およ
び最小値を検出し、その信号を反転させるとともに、そ
の反転されたディジタル信号をアナログ信号に変換して
出力するように構成したことを特徴とする。
[Means for solving the problem] An input level determination circuit for an A/D converter according to the present invention includes:
It is characterized by being configured to detect the maximum and minimum values of a digital signal converted by an A/D converter, invert the signal, and convert the inverted digital signal into an analog signal and output it. shall be.

[作用] この発明によれば、入力されたアナログ信号をディジタ
ル信号に変換し、その変換されたディジタル信号の最大
値および最小値を検出することにより、出力信号をテレ
ビジョン受信機のモニタなどに画像として写し出しなが
ら、正しい画像が得られるように、A/D変換器の入力
レベルを簡単に調整することができる。
[Operation] According to the present invention, an input analog signal is converted into a digital signal, and the maximum value and minimum value of the converted digital signal are detected, so that the output signal can be displayed on a monitor of a television receiver, etc. While displaying the image, the input level of the A/D converter can be easily adjusted so that the correct image is obtained.

[発明の実施例] 以下、この発明の一実施例を図面にもとづいて説明する
[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described based on the drawings.

第1図はこの発明の一実施例によるA/D変換器の入力
レベル判定回路の構成図であり、同図において、(1)
はアナログ信号(a)の入力端子、(2)はその入力ア
ナログ信号をディジタル信号(C)に変換するA/D変
換器、(3)はD/A変換器、(4)はA/D変換器(
1)で変換されたディジタル信号(C)の最大値および
最小値を求める論理回路で、AND回路(41)、NO
R回路(42)、OR回路(43)からなる。
FIG. 1 is a block diagram of an input level determination circuit of an A/D converter according to an embodiment of the present invention, in which (1)
is an input terminal for analog signal (a), (2) is an A/D converter that converts the input analog signal into a digital signal (C), (3) is a D/A converter, and (4) is an A/D converter. converter(
A logic circuit that calculates the maximum and minimum values of the digital signal (C) converted in step 1), which includes an AND circuit (41), NO
It consists of an R circuit (42) and an OR circuit (43).

(5)はA/D変換器(2)の出力を反転させる論理回
路で、複数のXOR回路(51)からなる、(6)はモ
ニタ、(d)は論理回路(4)で得られるディジタル信
号、(e)は論理回路(5)で得られるディジタル信号
である。
(5) is a logic circuit that inverts the output of the A/D converter (2), consisting of multiple XOR circuits (51), (6) is a monitor, and (d) is a digital signal obtained by the logic circuit (4). The signal (e) is a digital signal obtained by the logic circuit (5).

つぎに、上記構成の動作について説明する。Next, the operation of the above configuration will be explained.

いま、入力端子(1)に第2図(a)に示すような波形
のアナログビデオ信号が入力されると、A/D変換器(
2)の入力信号変換レベルが第2図(a)の(K)〜(
りの範囲内であるとき、第2図(a)で示す信号は(f
)のところで最大となり、A/D変換器(2)によって
rllllllllJの8ビツトのディジタル信号(C
)に変換される。
Now, when an analog video signal with a waveform as shown in FIG. 2(a) is input to the input terminal (1), the A/D converter (
The input signal conversion level of 2) is (K) to ( in Fig. 2(a)).
When the signal shown in FIG. 2(a) is within the range of (f
), and the A/D converter (2) converts the 8-bit digital signal (C
) is converted to

ついで、このディジタル信号(C)が論理回路(4)に
入力され、このとき、AND回路(41)は第3図の真
理値表に示すようにrlJが出力される方、NOR回路
(42)は第3図の真理値表に示すようにrOJが出力
され、それぞれの出力がOR回路(43)に入力されて
、このOR回路(43)は第3図の真理値表に示すよう
に「l」、のディジタル信号(d)を出力する。
Next, this digital signal (C) is input to the logic circuit (4), and at this time, the AND circuit (41) outputs rlJ and the NOR circuit (42) as shown in the truth table of FIG. rOJ is output as shown in the truth table of FIG. 3, and each output is input to the OR circuit (43), and this OR circuit (43) A digital signal (d) of "1" is output.

つぎに、ディジタル信号(C)とディジタル信号(d)
とが論理回路(5)に入力され、XOR回路(51)に
おいて第3図の真理値表に示すように、ディジタル信号
が反転されrooooooooJの8ビツトのディジタ
ル信号Ce)が得られる。
Next, digital signal (C) and digital signal (d)
is input to the logic circuit (5), and the digital signal is inverted in the XOR circuit (51) as shown in the truth table of FIG. 3 to obtain an 8-bit digital signal Ce) of roooooooooJ.

また、第2図(a)で示す信号は第2図の(g)のとこ
ろで最小となり、A/D変換器(2)によって、roo
ooooooJの8ビツトのディジタル信号(c)に変
換される。
Furthermore, the signal shown in FIG. 2(a) becomes the minimum at point (g) in FIG. 2, and the signal shown in FIG.
It is converted into an 8-bit digital signal (c) of ooooooJ.

ついで、このディジタル信号(C)が論理回路(4)に
入力され、このとき、AND回路(41)は第3図の真
理値表に示すように「O」が出力される一方、NOR回
路(42)は第3図の真理値表に示すようにrl」が出
力され、それぞれの出力がOR回路(43)に入力され
て、このOR回路(43)は第3図の真理値表に示すよ
うにrQJのディジタル信LHd)を出力する。
Next, this digital signal (C) is input to the logic circuit (4), and at this time, the AND circuit (41) outputs "O" as shown in the truth table of FIG. 3, while the NOR circuit ( 42) outputs "rl" as shown in the truth table of Fig. 3, and each output is input to the OR circuit (43), which is in turn as shown in the truth table of Fig. 3. The rQJ digital signal LHd) is output as follows.

つづいて、ディジタル信号(C)とディジタル信号(d
)が論理回路(5)に入力され、XOR回路(51)に
おいてディジタル信号が反転され。
Next, the digital signal (C) and the digital signal (d
) is input to the logic circuit (5), and the digital signal is inverted in the XOR circuit (51).

rllllllllJの8ビツトのディジタル信”>(
e)が得られる。
rllllllllllJ's 8-bit digital signal
e) is obtained.

L記のようにして得られた第2図(e)で示すようなデ
ィジタル信号がD/A変換器(3)でアナログ信桂に変
換されて、第2図(b)で示すような波形の出力信号を
モニタ(6)に人力する。
The digital signal as shown in FIG. 2(e) obtained as described in L is converted into an analog signal by the D/A converter (3), resulting in a waveform as shown in FIG. 2(b). The output signal is manually input to the monitor (6).

この出力信号(b)は人力信号(a)とは全く異なり、
A/D変換器(2)の入力信号レベルが適当でないと、
出力信号をテレビジ冒ン受信機などのモニタ(6)に入
力したとき、止しい画像が得られない。そこで、モニタ
(6)を見ながら、正しい画像が得られる範囲で、A/
D人力信号レベルを最大とするような調整をおこなうこ
とにより、適正な調整をおこなうことができる。
This output signal (b) is completely different from the human input signal (a),
If the input signal level of the A/D converter (2) is not appropriate,
When the output signal is input to a monitor (6) such as a television receiver, a clear image cannot be obtained. Therefore, while looking at the monitor (6), adjust the A/
D Proper adjustment can be made by making adjustments to maximize the human power signal level.

[発明の効果] 以上のように、この発明によれば、A/D変換器の出力
信号の最大値および最小値を検出し、それを反転してモ
ニタなどに画像を写すことにより、A/D変換器の入力
信号レベルをリアルタイムに正確に判定することができ
、その画像を見ながら、人力信号レベルを容易に、かつ
正確に調整することがで診る。
[Effects of the Invention] As described above, according to the present invention, by detecting the maximum value and minimum value of the output signal of the A/D converter, inverting them, and displaying the image on a monitor, etc. The input signal level of the D converter can be accurately determined in real time, and the human signal level can be easily and accurately adjusted while viewing the image.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例によるA/D変換器の入力
レベル判定回路の構成図、第2図は入出力信号の波形図
、第3図は論理回路の真理イ^、第4図は従来のA/D
変換器の入力レベル判定回路の構成図、第5図は従来の
回路の人出力信号の波形図である。 (2)・・・A/D変換器、(3)・・・D/A変換器
、(4) 、 (5)・・・論理回路、(6)・・・モ
ニタ。 なお、図中の同一符号は同一または相当部分を示す。
Fig. 1 is a configuration diagram of an input level determination circuit of an A/D converter according to an embodiment of the present invention, Fig. 2 is a waveform diagram of input/output signals, Fig. 3 is a logic circuit truth diagram, and Fig. 4 is a conventional A/D
FIG. 5 is a block diagram of the input level determination circuit of the converter, and is a waveform diagram of the human output signal of the conventional circuit. (2)...A/D converter, (3)...D/A converter, (4), (5)...logic circuit, (6)...monitor. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] (1)入力アナログ信号をディジタル信号に変換するA
/D変換器と、このA/D変換器から出力されるディジ
タル信号の最大値および最小値を検出する論理回路と、
上記A/D変換器から出力されるディジタル信号を反転
する論理回路と、その反転されたディジタル信号をアナ
ログ信号に変換するD/A変換器とを備えたことを特徴
とするA/D変換器の入力レベル判定回路。
(1) A that converts input analog signals to digital signals
/D converter; a logic circuit that detects the maximum value and minimum value of the digital signal output from the A/D converter;
An A/D converter comprising: a logic circuit that inverts a digital signal output from the A/D converter; and a D/A converter that converts the inverted digital signal into an analog signal. input level judgment circuit.
JP1341448A 1989-12-26 1989-12-26 Input level deciding circuit for a/d converter Pending JPH03198429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1341448A JPH03198429A (en) 1989-12-26 1989-12-26 Input level deciding circuit for a/d converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1341448A JPH03198429A (en) 1989-12-26 1989-12-26 Input level deciding circuit for a/d converter

Publications (1)

Publication Number Publication Date
JPH03198429A true JPH03198429A (en) 1991-08-29

Family

ID=18346159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1341448A Pending JPH03198429A (en) 1989-12-26 1989-12-26 Input level deciding circuit for a/d converter

Country Status (1)

Country Link
JP (1) JPH03198429A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574838B2 (en) * 1975-12-23 1982-01-27
JPS6159913A (en) * 1984-08-30 1986-03-27 Shin Kobe Electric Mach Co Ltd Ad converting circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574838B2 (en) * 1975-12-23 1982-01-27
JPS6159913A (en) * 1984-08-30 1986-03-27 Shin Kobe Electric Mach Co Ltd Ad converting circuit

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