JPS63225173A - Phase detector - Google Patents

Abstract

PURPOSE:To provide a highly accurate phase detector, by measuring the level of one of two input voltage at the rising point of time of other voltage. CONSTITUTION:With respect to two input voltages V'RS, R'TS' the level of one voltage at the rising point of time of the other voltage is alternately measured by a rising detection means 4 and a level detection means 5. The measuring results are compared with each other by a level comparing means 6 to make it possible to confirm which is an H-level. Therefore, on the basis of the advance or delay of the phase thereof, the phase order of a circuit can be measured by a positive phase and reverse phase discrimination means 7. In the case of phase omission, no rising is detected by the means 4 or the output of the means 5 equally becomes '0' or '1' or the output of the means 6 becomes non-coincidence and, therefore, the phase omission is certainly detected by a phase omission processing means 8. A measuring result is displayed on a display means 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a particularly digital phase detector for measuring the phase advance and lag of a line voltage in a three-phase AC circuit or the like.

[Conventional technology]

When connecting rotating equipment to a three-phase AC line, etc., it is necessary to check in advance whether the phase of the line voltage is positive or negative in order to prevent danger from reverse rotation. An analog type phase detector is used.

[Problem that the invention seeks to solve]

Incidentally, recently, for measuring other electrical quantities such as the line voltage of a three-phase AC power line, digital measuring instruments equipped with, for example, a microcomputer have been used, and these have become mainstream. Therefore, for on-site use, it is necessary to prepare at least two analog phase detectors and another digital measuring instrument, which is especially inconvenient when working outdoors.

This invention has been made in view of the above points, and its first purpose is to realize a highly accurate phase detector that performs measurements digitally. A second object of the present invention is to provide a phase detector which can be incorporated into, for example, another digital measuring instrument and can perform measurements by sharing its microcomputer.

[Measurement principle]

First, the measurement principle of the phase detector according to the present invention will be explained with reference to FIG. In the same figure (A), for example, symmetry 3
Let the phase voltage of each phase circuit be VR + VatMl, and 3
What is the line voltage of real lines R, S, and T? *s+? ts, the phase relationship between these two voltages is shown, for example, in (a) of FIG. 1(B).

For example, when looking at the voltage vTs with VR3 as a reference, if the phase of the voltage VTS is ahead of the phase of the voltage VFIs, as shown by the solid line in the figure, it is assumed to be in positive phase, and it is delayed as shown by the one-dot line. If so, it is determined that the phase is reversed. In this way, the above two voltages VRs and vis can be converted into square waves of voltages V'R5 and v'Ts shown in (b) and (c) of FIG. 1(B), respectively, using a zero-cross comparator, for example. In the case of shaping, if you measure the level of voltage v'as at time t1 or t2 when voltage v'as rises from zero level, you can tell whether the phase is advanced or delayed depending on whether it is at H level or L level. , it is possible to judge whether the phase is normal or reversed.

In this case, for example, the falling point t of v'Rs, or t
The level of the voltage v'Ts at 4 may be measured; however, in this case, when it is at L level, it is in the positive phase, and when it is at H level, it is in the opposite phase.

[Structure of the invention]

This embodiment of the phase detector has the functions shown in FIG. 7, that is, three electrical circuits to be measured R, S, T
an input level adjusting means 1 for adjusting the voltages VR8 and vis applied from the input terminal to appropriate levels, a waveform shaping means 2 for converting the adjusted voltages into square wave voltages vRs' and V'τS, respectively; has a reference voltage source 3 for setting a threshold level of the converted voltage, and a rise detection means 4 for detecting the rise time of one of the converted voltages and alternately measuring the level of the other voltage at that time; means 5.

Further, for example, a level comparison means 6 for comparing which of the two detection outputs V'R3 and V'τ obtained by the level detection means 5 is the H level and which is the L level; According to the result, the above input voltage VR8 and vdings
The positive phase/negative phase determining means 7 performs phase determination, and the rise detecting means 4 detects the square wave voltage V'R8 or V'
When the rise of the level is not detected, and when the measured level is uniformly zero or 1 even if the level detecting means 5 measures a predetermined number of times.

Alternatively, it has an open-phase processing means 8 that determines that the phase is open when the comparison result of the level comparison means 6 does not match the previous comparison result, and a display means 9 that displays these determinations.

In this embodiment, for example, the rise detection means 4. measurement number setting means 10 for causing the level detection means 5 and the level comparison means 6 to perform measurements a predetermined number of times;
When the measured output of the level detection means 5 is at zero level,
This level detecting means 5 and a measurement aborting means 11 for aborting the measurement operation of the rise detecting means 4 after a predetermined number of times are provided.

[For production]

As is clear from the above description of the functional blocks and the above description of the operating principle, the rise detection means 4 and the level detection means 5 detect the two input voltages v'R3 and V'T8 at the time when one voltage rises and the other The voltage level V'RS can be determined by alternately measuring v'Ts and comparing them with the level comparison means 6 to determine which one is the H level and which one is the L level. In the case of an open phase, the rise detection means 4 does not detect the rise, or the output of the level detection means 5 is uniformly O.
or 1, or the output of the level comparison means 6 becomes inconsistent, so this can also be reliably detected.

〔Example〕

Referring to FIG. 3 in which an embodiment of the present invention is shown, line voltages VR8 and v-rs of the electrical circuits to be measured R, S, and T are shown.
For example, two attenuators 21 each share the electric circuit S.
a, 21b, and after being adjusted to an appropriate level, it is input to waveform shapers 22a, 22b.

In the operating principle explanatory diagram of FIG. 1(B) above, a case is illustrated in which waveform shaping is performed using a zero-cross comparator, but in this embodiment, in order to remove interference waves such as noise, for example, from the reference voltage source 23. A comparator whose threshold level is a given reference voltage is used as a waveform shaper. The voltages v'R and v'Ts converted into square waves by the waveform shapers 22a and 22b are applied to the microcomputer 24, for example, and it is detected which one is the H level and which is the L level. Based on the lead or lag of the phase, the route phase and reverse phase of the electrical circuits to be measured R, S, and T are determined and displayed on the display 29.

This microcomputer 24 is equipped with the respective functions in the block 24' surrounded by the dotted line frame, such as the rise detection means 4 or the phase loss processing means 8, the measurement number setting means 10, and the measurement aborting means 11 in FIG. It is being

Here, the operation will be explained with reference to the fourth example.

At the start of measurement, the number of repetitions of measurement is first set in, for example, a working register. This measurement is repeated to prevent erroneous judgments, and if it is set to 1, for example, 10 times, in the case of 507 electrical circuits, a series of measurements will be completed in about 0.2 seconds.

Next, activate the timer counter and start measurement.
For example, the rise of one input voltage V'R1+ is detected. In this case, if it is already level 1, the detection will be repeated until it returns to level Q and rises to level 1 again. If, for example, 0.2 seconds elapse without any change in the state of level 1, a timeout command is issued from the timer counter, a predetermined flag is set to indicate an open phase, and the measurement is terminated. If the voltage v'Rs remains at level 0 and does not rise to level 1, a timeout similarly occurs and is treated as an open phase.

When the voltage v'R rises to level 1, for example, the level of the other input voltage V'T8 is detected, and its value 1 or 0 is set in a predetermined flag as V'TB.

Next, the level of one input voltage V'R8 is detected at the time of rise of the other input voltage V', . In this case, if the voltage v'T remains at level 1 or level O and does not rise, a timeout similarly occurs and the voltage v'rs is treated as an open phase. If the voltage v'T rises, the voltage v'Rs at that point
The level of is detected, and its value 1 or 0 is set to a predetermined flag, for example, as v'Rs.

Next, the two level data v set in the above flags
A comparison of 'R,,v', and a phase determination thereof are performed. In other words, if v'R, is 1 and V''r4 is also 1, it is an abnormality and is treated as having an open phase in the circuit under test.If the data V'T9 is 0, the first measurement If so, the flag is set as negative phase, and the measurement is repeated the remaining number of times. If it has been measured multiple times, it is compared with the previous data, and if that data is in positive phase, it is different from the current data, which is an abnormality, and is similarly treated as an open phase.

If the data up to the previous time is in reverse phase, the remaining number of measurements are performed.

When the above v'Rs data is 0, if the V'TS data is 0, it is treated as an open phase, and if the V'TS data is 1 and it is the first measurement, it is treated as an open phase. It is set as a positive phase and the remaining number of measurements are taken. If the data has been measured multiple times, it is compared with the previous data, and if there is a mismatch, it is similarly treated as an open phase, and if there is a match, the measurement is repeated the remaining number of times.

〔effect〕

As described in detail, the phase checker according to the present invention adjusts the two line voltages of the AC line to be measured to an appropriate level via an attenuator, and then converts the voltage into a square wave voltage using a waveform shaper. and a rise detection means and a level detection means that alternately measure the level of the other square wave voltage at the time of rise of one square wave voltage, and two voltage data obtained by the level detection means. The level comparison means detects the lead or lag of the phase depending on which one is level 1 and which is level 0, and this level is provided.

Further, the measurement aborting means aborts the measurement after a predetermined time has elapsed when the rising edge of the square wave voltage is not detected by the rising edge detecting means and when the two comparison data in the level comparing means are both 1 or 0. Furthermore, if the current measurement data does not match the measurement data up to the previous time in the normal phase/inverse phase discrimination means, it is further provided with an open phase processing means that determines that there is an open phase as well as when the measurement is discontinued.

Therefore, by replacing each of the above-mentioned means with a microcomputer, for example, it is possible to provide a phase detector that measures the normal phase, negative phase, or open phase of the three-phase electric circuit to be measured at high speed and with high accuracy. Moreover, if it is incorporated into another digital measuring device and its microcomputer is shared, it is possible to realize a relatively low-cost, multi-functional on-site measuring device equipped with a phase detector.

[Brief explanation of the drawing]

The attached drawings all relate to embodiments of the phase detector according to the present invention, and FIG. 1(A) and FIG. 1(B) are diagrams illustrating the operating principle;
FIG. 2 is a block diagram showing an example of the functional configuration, FIG. 3 is a block diagram showing an example of the device configuration, and FIG. 4 is a flow diagram showing an example of program control of the operation of this device. . In the figure, 2 is a waveform shaping means, 4 is a rise detection means, and 5 is a waveform shaping means.
1 is a level detection means, 6 is a level comparison means, 7 is a positive/negative phase discrimination means, 8 is an open phase processing means, 10 is a measurement number setting means, 22a, 22b are waveform shapers, 24 is a microcomputer, R, S , T is the three-phase electric circuit to be measured, V R8* V
79 is the line voltage, V'R8+V'TS is the square wave voltage, and V'Rjl V'7g is the level detection data. Patent applicant Takuya Ohara, agent of Hioki Electric Co., Ltd., patent attorney Figure 1 (A) ) ys Figure 1 (B)

Claims (1)

[Claims] The two line voltages of the three-phase electric circuit to be measured are each converted into square wave voltages, and the rising edge of one square wave voltage is detected via a rising edge detection means, and at the time of detection, the rising edge of the other square wave voltage is detected. level detecting means for alternately measuring the level of the wave voltage a predetermined number of times; and comparing the level value of one of the square wave voltages and the level value of the other square wave voltage sent from the level detecting means to determine the level of the two square wave voltages. level comparison means for detecting phase lead/lag of the wave voltage; positive/negative phase discrimination means for determining the phase order of the three-phase electric circuit to be measured based on the detection output from the level comparison means; the rise detection means; A phase detector comprising an open phase processing means for determining an open phase in the three-phase electric circuit to be measured based on the outputs of the detecting means and the level comparing means or the discrimination data of the positive/negative phase discriminating means.