JPH0319692B2 - - Google Patents

Info

Publication number
JPH0319692B2
JPH0319692B2 JP55059988A JP5998880A JPH0319692B2 JP H0319692 B2 JPH0319692 B2 JP H0319692B2 JP 55059988 A JP55059988 A JP 55059988A JP 5998880 A JP5998880 A JP 5998880A JP H0319692 B2 JPH0319692 B2 JP H0319692B2
Authority
JP
Japan
Prior art keywords
layer
pattern
deposited layer
workpiece
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP55059988A
Other languages
Japanese (ja)
Other versions
JPS56157026A (en
Inventor
Yoshiharu Ozaki
Kazuo Hirata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP5998880A priority Critical patent/JPS56157026A/en
Publication of JPS56157026A publication Critical patent/JPS56157026A/en
Publication of JPH0319692B2 publication Critical patent/JPH0319692B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Description

【発明の詳細な説明】 本発明は集積回路の製造工程においてレジスト
層を用いることなくウエハー上の被加工物層の微
細パターンを形成する方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming fine patterns in a workpiece layer on a wafer without using a resist layer in an integrated circuit manufacturing process.

従来の集積回路のパターンを形成する方法は被
加工物層上にレジスト膜を形成し、次にこのレジ
スト膜にパターンを形成し、このパターン形成さ
れたレジスト膜をマスク層として被加工物層をエ
ツチングしてパターンを形成するものであつた。
このようにレジスト膜を用いる方法は、次のよう
な欠点をもつていた。即ち、レジスト膜は耐熱性
が劣るために、たとえば200℃以上の雰囲気での
加工が不可能であること、レジスト膜は通常スピ
ナによつて塗布されるが、このために膜厚がウエ
ハー内で均一にならないこと、レジスト材を構成
する高分子の分子量が大きいこと、特に被加工物
をドライエツチングするためにはレジスト膜厚を
厚くする必要があり、しかもウエハーの表面段差
部でレジスト膜厚が一様にならないことによつ
て、線幅1μm以下のパターンをエツチングする
ためのマスク層としてはレジスト膜は不適であつ
た。
The conventional method for forming integrated circuit patterns is to form a resist film on a workpiece layer, then form a pattern on this resist film, and use the patterned resist film as a mask layer to cover the workpiece layer. The pattern was formed by etching.
This method of using a resist film has the following drawbacks. In other words, the resist film has poor heat resistance, so it is impossible to process it in an atmosphere of 200°C or higher, and the resist film is usually applied using a spinner, which causes the film thickness to vary within the wafer. The resist film is not uniform, the molecular weight of the polymer that makes up the resist material is large, and the resist film thickness must be increased especially for dry etching the workpiece. Because the resist film is not uniform, it is not suitable as a mask layer for etching a pattern with a line width of 1 μm or less.

また、最近このような欠点を除去するため、レ
ジスト膜を用いないで被加工物層上にパターンを
形成する方法が提案されている。
Furthermore, recently, in order to eliminate such defects, a method has been proposed in which a pattern is formed on a workpiece layer without using a resist film.

一つは特開昭53−102845号公報に記載された方
法で、絶縁層上に電子ビームを所望パターン状に
照射して、この電子ビームの電荷で絶縁層上に潜
像を形成し、この潜像を利用して絶縁層をドライ
エツチングしてパターンを形成する方法である。
しかしながら、この方法は適用できる被加工物が
表面に電荷を保持できる絶縁層に限られるという
欠点があるばかりでなく、潜像のある領域と他の
領域とのエツチング選択比がどの程度とれるか問
題がある。
One is the method described in JP-A-53-102845, in which an electron beam is irradiated onto an insulating layer in a desired pattern, and a latent image is formed on the insulating layer by the charge of the electron beam. This method uses a latent image to dry-etch an insulating layer to form a pattern.
However, this method has the disadvantage that the workpiece to which it can be applied is limited to an insulating layer that can retain charge on the surface, and there is also the problem of the degree of etching selectivity between the area with the latent image and other areas. There is.

他の一つは特開昭54−61477号公報に記載され
た方法で、アルミニウム層表面に電子ビームを照
射して、照射されたアルミニウム層表面上に汚染
膜を形成し、この汚染膜をマスク層としてアルミ
ニウム層をエツチング又は陽極酸化して、アルミ
ニウム層のパターンを形成する方法である。しか
しながら、この方法は適用できる被加工物がアル
ミニウム層に限られるという欠点があるばかりで
なく、汚染膜を形成するための雰囲気中の成分が
以後の製造工程に与える影響が問題である。
The other method is described in Japanese Patent Application Laid-Open No. 54-61477, in which the surface of the aluminum layer is irradiated with an electron beam, a contamination film is formed on the irradiated surface of the aluminum layer, and this contamination film is used as a mask. In this method, a pattern of the aluminum layer is formed by etching or anodizing the aluminum layer as a layer. However, this method not only has the drawback that the workpiece to which it can be applied is limited to aluminum layers, but also has the problem of the influence of components in the atmosphere for forming the contaminated film on subsequent manufacturing steps.

本発明はこれらの欠点を解決するために、プラ
ズマ雰囲気中でウエハー上の被加工物層表面に堆
積層を形成し、この堆積層に粒子線ビームを所望
のパターン状に照射して、照射された領域の堆積
層を除去し、このパターン状に残つた堆積層をマ
スク層として被加工物層をエツチングして、パタ
ーンを形成するようにしたもので、以下に実施例
で詳細に説明する。
In order to solve these drawbacks, the present invention forms a deposited layer on the surface of a workpiece layer on a wafer in a plasma atmosphere, and irradiates this deposited layer with a particle beam in a desired pattern. The pattern is formed by removing the deposited layer in the area and etching the workpiece layer using the deposited layer that remains in the pattern as a mask layer, which will be described in detail in Examples below.

図は本発明の実施例で、1はシリコン基板、2
はシリコン基板1を熱酸化して形成した層間絶縁
膜となる酸化シリコン膜であり、本実施例では酸
化シリコン膜2が被加工物層である。
The figure shows an embodiment of the present invention, where 1 is a silicon substrate, 2
is a silicon oxide film which becomes an interlayer insulating film formed by thermally oxidizing a silicon substrate 1, and in this embodiment, the silicon oxide film 2 is the workpiece layer.

はじめに、1及び2からなる試料をCF4ガスを
導入した円筒型プラズマ装置に入れ、約10分間試
料表面をプラズマ雰囲気にさらすと、吸着作用に
よつて、酸化シリコン膜2の表面にC(炭素)と
C及びF(フツ素)からなる化合物とからなる堆
積層3が図Aに示すように膜厚約100Å形成され
た。このときのプラズマ条件は圧力0.6Torr、パ
ワー300Wである。この場合、シリコン基板1上
の被加工物層がアルミニウム膜であつても、これ
は吸着作用であるから同様に上記堆積層が形成さ
れる。また、この堆積条件はプラズマエツチング
にならない条件であることを意味するものである
から、装置としては円筒型装置に限らず他の装置
を用いても可能であり、そのガス成分もC及びF
を含むガスであればCF4ガスに限らず、さらに
CxFy、CxFyClz、CxFyHz等のいわゆるフロン
系ガスであつても堆積層3の形成は可能であるこ
とは明らかであろう。また、堆積層3の膜厚は後
に粒子線ビームで除去する点、及びエツチングの
マスク材とする点から100Å程度が望ましい。
First, a sample consisting of 1 and 2 is placed in a cylindrical plasma device that introduces CF 4 gas, and when the sample surface is exposed to the plasma atmosphere for about 10 minutes, C (carbon ) and a compound consisting of C and F (fluorine) was formed to a thickness of about 100 Å as shown in Figure A. The plasma conditions at this time were a pressure of 0.6 Torr and a power of 300 W. In this case, even if the workpiece layer on the silicon substrate 1 is an aluminum film, the deposited layer is formed in the same way because this is an adsorption effect. In addition, since this deposition condition means that plasma etching does not occur, it is possible to use not only a cylindrical device but also other devices, and the gas components also include C and F.
Not only CF4 gas, but also gas containing
It is clear that the deposited layer 3 can be formed using so-called fluorocarbon gases such as CxFy, CxFyClz, and CxFyHz. Further, the thickness of the deposited layer 3 is desirably about 100 Å since it will be removed later with a particle beam and it will be used as a mask material for etching.

次に、図Bに示すように、堆積層3表面の必要
な部分に、所望のパターン状にたとえばコンタク
ト・ホールの形状に粒子線ビーム4を照射し、照
射された部分の堆積層を除去し、所望のパターン
5を形成する。この場の粒子線ビームはビーム径
を絞つて微細なパターンを描ける点から電子ビー
ムが適当であるが、要は堆積層3を除去できるだ
けのエネルギをもつた粒子線ビームであればよ
い。
Next, as shown in Figure B, a particle beam 4 is irradiated onto a desired portion of the surface of the deposited layer 3 in a desired pattern, for example in the shape of a contact hole, and the irradiated portion of the deposited layer is removed. , to form a desired pattern 5. An electron beam is suitable as the particle beam in this case because it can draw a fine pattern by narrowing down the beam diameter, but any particle beam that has enough energy to remove the deposited layer 3 is sufficient.

次に、この試料をCF4(標準状態で50c.c./分)
とH2(標準状態で25c.c./分)との混合ガスで、パ
ワー300W、20分間反応性スパツタエツチングを
行つた。このとき、図Cに示すように、パターニ
ングされた堆積層3の領域では堆積3とプラズマ
とが相互作用して、プラズマ重合膜の成長と反応
性スパツタエツチングがほぼ平衡状態になり、こ
のエツチング中も堆積層3の厚さは殆んど減少し
ない。一方、堆積層3のない領域ではプラズマ重
合が起らないため反応性スパツタエツチングのみ
が進行し、酸化シリコン膜2はエツチングされて
いく。即ち、堆積層3のない領域のみが選択的に
エツチングされ、パタン5が形成され、従つて酸
化シリコン膜2のパタンが形成されることにな
る。この実験例では酸化シリコン膜2が1170Åエ
ツチングされたのに対して、堆積層3は90Åエツ
チングされただけである。即ち、酸化シリコン膜
2と堆積層3とのエツチング速度は各々73Å/
分、5.5Å/分となり、両者のエツチング選択比
は10以上が得られている。なお、この場合被加工
物層をアルミニウム層とするときはアルミニウム
のエツチング可能な雰囲気とすればよい。
This sample was then heated to CF 4 (50 c.c./min under standard conditions).
Reactive sputter etching was performed for 20 minutes at a power of 300 W using a mixed gas of H 2 and H 2 (25 c.c./min under standard conditions). At this time, as shown in FIG. Even inside, the thickness of the deposited layer 3 hardly decreases. On the other hand, in areas where there is no deposited layer 3, plasma polymerization does not occur, so only reactive sputter etching proceeds, and the silicon oxide film 2 is etched. That is, only the area where the deposited layer 3 is not present is selectively etched to form the pattern 5, and thus the pattern of the silicon oxide film 2. In this experimental example, the silicon oxide film 2 was etched by 1170 Å, whereas the deposited layer 3 was etched by only 90 Å. That is, the etching rates of the silicon oxide film 2 and the deposited layer 3 are each 73 Å/
5.5 Å/min, and an etching selectivity of 10 or more was obtained between the two. In this case, when the workpiece layer is an aluminum layer, an atmosphere that can etch aluminum may be used.

次に、25KV、25mAのイオンビームを約1分
間照射して、プラズマ重合した残存する堆積層3
を除去すると、図Dに示すような所望の幅1μm
以下の酸化シリコン膜のパターンが形成された。
この堆積層は分子間の結合力も弱く、又下地層と
の密着力も弱いため、Ar(アルゴン)イオンビー
ムのエネルギによつて照射された部分の堆積層の
分子がはじき飛ばされたものと考えられる。上述
の堆積層3を除去するには酸又は有機溶剤による
処理でも可能であるが、要は堆積層3と相互作用
してプラズマ重合しないようなエネルギ粒子の雰
囲気中でのドライプロセス処理であるならば可能
である。たとえば、上述のArの他、N2、O2等の
プラズマやイオン・ビームに試料をさらせば、堆
積層は容易に除去できる。また、堆積層3のパタ
ーニングに用いた電子ビームによつてももちろん
除去可能である。
Next, an ion beam of 25KV and 25mA is irradiated for about 1 minute to remove the plasma-polymerized remaining deposited layer 3.
, the desired width of 1 μm as shown in Figure D
The following silicon oxide film pattern was formed.
This deposited layer has weak intermolecular bonding strength and weak adhesion to the underlying layer, so it is thought that the molecules of the deposited layer in the areas irradiated by the energy of the Ar (argon) ion beam were repelled. The above-mentioned deposited layer 3 can be removed by treatment with an acid or an organic solvent, but the key is to use a dry process in an atmosphere of energetic particles that will not interact with the deposited layer 3 and cause plasma polymerization. It is possible. For example, in addition to the above-mentioned Ar, the deposited layer can be easily removed by exposing the sample to plasma or ion beam of N 2 , O 2 or the like. Furthermore, it can of course be removed by the electron beam used for patterning the deposited layer 3.

以上説明したように、本発明は粒子線ビームで
ウエハ上の被加工物層のパターンを形成するこ
と、更にマスク材となる堆積層の膜厚が100Å程
度と極めて薄いためパターン分解能が高いこと、
エツチング選択比が高いことが相埃つて、1μm
以下の微細パターンが極めて容易に形成できるも
のである。さらに、本発明はレジストを用いない
パターン形成法であるので、エツチング時の温度
条件の限定を受けないことはもちろん、マスク材
となる堆積層はウエハーの表面段差のどの部分で
も均一性よく形成され、ウエハ内でのパターン形
成の均一性が良い。
As explained above, the present invention uses a particle beam to form a pattern on a workpiece layer on a wafer, and furthermore, since the thickness of the deposited layer serving as a mask material is extremely thin at about 100 Å, the pattern resolution is high.
Coupled with the high etching selectivity, 1μm
The following fine patterns can be formed extremely easily. Furthermore, since the present invention is a pattern forming method that does not use a resist, it is not limited by the temperature conditions during etching, and the deposited layer that becomes the mask material can be formed with good uniformity on any part of the surface steps of the wafer. , the uniformity of pattern formation within the wafer is good.

【図面の簡単な説明】[Brief explanation of drawings]

図AからDは本発明の一実施例で、各工程にお
ける断面図を示したものである。 1……シリコン基板、2……酸化シリコン膜、
3……堆積層、4……粒子線ビーム、5……堆積
層の除去されたパターン。
Figures A to D show an embodiment of the present invention, and show cross-sectional views at each step. 1...Silicon substrate, 2...Silicon oxide film,
3...Deposited layer, 4...Particle beam, 5...Removed pattern of the deposited layer.

Claims (1)

【特許請求の範囲】[Claims] 1 被加工物層表面を炭素と弗素と塩素からなる
フロン系ガスのガスプラズマ雰囲気にさらして、
前記被加工物層表面に前記フロン系ガスの構成元
素を成分とする堆積層を形成する工程と、次に前
記堆積層表面に粒子線ビームを所要パターン状に
照射して、照射された前記堆積層の領域を除去
し、前記堆積層のパターンを形成する工程と、次
に前記堆積層のパターンをマスク層として前記被
加工物層を弗化炭素に水素を混合したガスのガス
プラズマ雰囲気にさらして前記所望のパターンに
形成する工程とからなることを特徴とするパター
ン形成法。
1. Expose the surface of the workpiece layer to a gas plasma atmosphere of fluorocarbon gas consisting of carbon, fluorine, and chlorine,
a step of forming a deposited layer containing constituent elements of the fluorocarbon-based gas on the surface of the workpiece layer, and then irradiating the surface of the deposited layer with a particle beam in a desired pattern to reduce the irradiated deposited layer. removing a region of the layer and forming a pattern of the deposited layer, and then exposing the workpiece layer to a gas plasma atmosphere of a mixture of carbon fluoride and hydrogen, using the pattern of the deposited layer as a mask layer. A pattern forming method comprising the step of forming the desired pattern using
JP5998880A 1980-05-08 1980-05-08 Formation of pattern Granted JPS56157026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5998880A JPS56157026A (en) 1980-05-08 1980-05-08 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5998880A JPS56157026A (en) 1980-05-08 1980-05-08 Formation of pattern

Publications (2)

Publication Number Publication Date
JPS56157026A JPS56157026A (en) 1981-12-04
JPH0319692B2 true JPH0319692B2 (en) 1991-03-15

Family

ID=13129051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5998880A Granted JPS56157026A (en) 1980-05-08 1980-05-08 Formation of pattern

Country Status (1)

Country Link
JP (1) JPS56157026A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63198327A (en) * 1987-02-13 1988-08-17 Nec Corp Forming method for ultrafine pattern of adsorption layer due to electron beam separation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS527315A (en) * 1975-05-28 1977-01-20 Pechiney Aluminium Making of wire consist of aluminium magnesiummsilicon alloy
JPS55129345A (en) * 1979-03-29 1980-10-07 Ulvac Corp Electron beam plate making method by vapor phase film formation and vapor phase development

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS527315A (en) * 1975-05-28 1977-01-20 Pechiney Aluminium Making of wire consist of aluminium magnesiummsilicon alloy
JPS55129345A (en) * 1979-03-29 1980-10-07 Ulvac Corp Electron beam plate making method by vapor phase film formation and vapor phase development

Also Published As

Publication number Publication date
JPS56157026A (en) 1981-12-04

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