JPH03192836A - Method and apparatus for carrier detection - Google Patents

Abstract

PURPOSE:To normally detect a carrier independently of the deterioration in the characteristic of a transmission line by discriminating it to be detection of a carrier when a peak is observed m-times for N periods in any of plural areas divided in one period of a code series in the carrier detection of the CSK modulation system. CONSTITUTION:The apparatus is provided with a peak position detection circuit 26, a peak position discrimination circuit 27, a counter circuit 28 and an m/N discrimination circuit 29. The peak position detection circuit 26 detects the correlation peak position of a correlation signal between a reception signal and a code series of a prescribed code length for one period each of a code series over 1st prescribed number (N) periods to be consecutive at most and discriminates to which area the peak position detected by the peak position discrimination circuit 27 belongs among areas of plural the number to be divided in one period. The counter circuit 28 counts the number of detected peaks belonging to the area each and the m/M discrimination circuit 29 discriminates whether or not the detection peak count in any area for the 1st prescribed number (N) periods at most reaches the 2nd prescribed number (m) and outputs a carrier detection signal when the count reaches the number (m).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a receiving device for spread spectrum (SS) communication, particularly for code shift keying (Code Shift Keying).
The present invention relates to a carrier detection method and device in a receiving device using the Sh[t Keying -CS K ) modulation method.

The conventional SS communication method has been widely applied to power line communication as well as satellite communication and mobile communication. The conventional SS communication system will be explained with reference to FIG. 31 and FIG. 32. On the transmitting side, the output a of the PN (pseudo-noise) code sequence generator 1 is subjected to an EX-OR operation (signal c) with the transmission data b by the EX-OR circuit 2 (signal c), and then sent to the transmission line as a transmission signal by the amplifier 3. On the receiving side, the received signal is amplified by an amplifier 4, then correlated with the output d of the synchronous PN code sequence generator 5 by a correlator 6, and the correlation value (signal e) is compared with a predetermined threshold value by a comparator 7. Demodulate the received data f.

The transmission path may be wireless, wired, or other transmission media. Therefore, the transmission signal is not only sent directly to the transmission medium, but also often converted into a signal suitable for transmission through the transmission medium and sent. Also, power line communication requires an interface that separates it from commercial power. The connection portion with the transmission medium that performs such signal conversion and separation is hereinafter referred to as a reception interface and a transmission interface.

In the conventional communication system, the PN sequence generated by the synchronous PN code sequence generator 5 on the receiving side must be synchronized with the PN sequence on the transmitting side, and for this purpose, it is first necessary to search for a synchronization point. If there is no problem with the transmission characteristics of the transmission path, a peak is detected in the correlation waveform at the synchronization point. However, in power line communications, where the transmission characteristics are extremely poor and there are dip points within the transmission band, the correlation waveform deteriorates and the relationship between positive and negative correlation values becomes reversed.

This may result in a 1.0 error in the data. Another drawback was that synchronization could not be maintained due to waveform deterioration.

The inventors proposed a new C5K communication system that overcomes the drawbacks of the conventional SS communication system described above (Hoso et al.; "High-performance power line SS modem" Institute of Electronics, Information and Communication Engineers (IEICE) Spread spectrum technology and its applied research Meeting March, 221
9895STA89-8).

In the C5K communication system, on the transmitting side, two binary PN code sequences of the same code length with low cross-correlation are generated at a fixed cycle, and at each fixed cycle, the two binary PN code sequences are generated depending on whether the transmitted data is 1 or 0. One of the different PN code sequences is selected and sent as a transmission signal. On the other hand, on the receiving side, two correlation outputs are obtained by correlating the received signal with the two PN code sequences used on the transmitting side. A correlation peak always appears in one of these two correlation outputs at each of the above-mentioned fixed periods. Therefore, 2
Demodulated data of 1 or 0 is created based on the comparison of the peak values of the two correlation outputs.

In such a C3K communication system, the receiving side compares two correlation outputs and assigns 0 or 1 to the received data depending on the magnitude of the peak value, so the code sequence on the receiving side is the same as that on the transmitting side. There is no need to strictly synchronize with this, and data demodulation errors will not occur. Also as the output of the correlator.

By taking the absolute value, there is an effect that no error occurs even in the case of a transmission line whose characteristics are deteriorated such that the transmission peak value becomes negative.

As described above, a correlation peak appears in one of the two correlation outputs at each of the above-mentioned fixed periods. In order to correctly detect this correlation peak on the receiving side, it is necessary to synchronize the operation of the receiving side device with the received signal so that the correlation peak appears periodically within a certain period. especially,
In the case of power line communication, when using a poor transmission path such as a commercial AC power line, the transmission characteristics may change rapidly and the peak position may vary greatly.

In the above C3K communication system, a correlation peak of a correlation signal between a received signal and a code sequence of a predetermined code length is detected, and a position of this correlation peak within a data interval of a period corresponding to the code length is detected. Then, it is determined whether this peak position is within the 4p section set within the data section. Then, when it is determined that the peak position exists within the observation interval a predetermined number of times consecutively, it is determined that carrier detection, that is, synchronization has been established.

Problems to be Solved by the Invention As described above, in the C5K communication system previously proposed by the inventors, when the correlation peak of a correlation signal is detected a predetermined number of times in a row within a predetermined observation interval, it is determined that a carrier is present. However, if the characteristics of the transmission path deteriorate, the correlation peak position will fluctuate,
It has been found that even though a carrier is present, carrier detection may not be performed normally because the correlation peak position deviates from the observation interval.

Means for Solving the Problems A carrier detection method according to the present invention detects the correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length by detecting the correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length, at maximum, in a continuous first predetermined position for each cycle of the code sequence. Detection is performed over several N periods, and it is determined to which area the detected peak position belongs among the areas divided into a plurality of areas within one period, and the number of detected peaks belonging to that area is calculated for each area. It is determined whether the detected peak count value in any one area has reached a second predetermined number m during the first predetermined number N cycles, and if it has reached the carrier detection signal. It is characterized by outputting.

A carrier detection device according to the present invention includes a peak position detection circuit that detects a correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length for each period of the code sequence; A peak position determination circuit that determines which area it belongs to among multiple areas divided within a cycle.

a counting circuit that counts, for each area, the number of detected peaks determined to belong to that area over a first predetermined number of consecutive N cycles;

During the first predetermined number N periods, it is determined whether the detected peak count value in any one area has reached the second predetermined number m, and if it has reached the second predetermined number m, a carrier detection signal is outputted. It is characterized by being equipped with an N determination circuit.

The carrier detection device according to the present invention also detects the correlation peak position of a correlation signal between two received signals and a code sequence of a predetermined code length.
a peak position detection circuit that detects each cycle of a code sequence;
storage means for storing the detected peak positions over a first predetermined number N or more consecutive cycles; and storage means for storing the detected peak positions over a first predetermined number N or more consecutive cycles, and for each of the stored peak positions for the first predetermined number N consecutive cycles, Determine which area it belongs to among the divided areas, count the number of peak positions determined to belong to each area, and calculate the peak position count value in any one area as a second predetermined number. The present invention is characterized in that it includes a determining means that determines whether the number is equal to or greater than m, and determines that carrier detection is performed if the number is equal to or greater than a second predetermined number m.

The correlation peak position of the correlation signal between the received signal and the code sequence of a predetermined code length is determined for each cycle of the code sequence.

A maximum of a first predetermined number of consecutive N cycles are detected. It is determined to which area the detected peak position belongs among the areas divided into a plurality of areas within one cycle, and the detection is performed for each area.

The number of detected peaks belonging to that area is counted. At most, during the first predetermined number N cycles, the detected peak count value in any one area reaches a second predetermined number m.
It is determined whether or not it has been reached, and if it has been reached, carrier detection is determined.

Embodiment (1) Overall configuration of C8K communication system FIG. 1 shows the overall configuration of a C3K type communication system using the Manchester code M sequence.

On the transmitting side, the modulating device (transmitting device) 11 is provided with two Manchester M-sequence generators 31 and 32 that respectively generate Manchester code M-sequences synchronously with low cross-correlation and the same code length, Their code outputs are given to the switching circuit 33. This switching circuit 33 is controlled according to the binary transmission data (1 or 0); for example, when the transmission data is 0, the code output of the generator 31 is selected, and when the transmission data is 1, the code output of the generator 32 is selected.

The code output signal selected by this switching circuit 33 becomes the transmission signal TXO. Switching control in the switching circuit 33 is performed in synchronization with the cycle of the Manchester code M series that is generated, and one piece of binary data (1 or O) is expressed by the Manchester code M series of -cycle.

This modulation method is called code shift keying (C3K) because the switching or selection of two different Manchester code M sequences is performed depending on the code (1 or 0) of the data to be transmitted.

Of course, in C8K, other PN code sequences may be used instead of the Manchester M sequence.

The transmission signal TXO is sent out to the transmission line or transmission medium via the transmission interface 12A. As described in the "Prior Art" section, the transmission interface 12A is a connection section in a broad sense, and is a section that performs carrier modulation, mixing processing into a power line, and the like.

The reception interface 12B also demodulates the carrier.

It performs separation from the power line, A/D conversion, etc., and converts the signal input from the transmission path or transmission medium into a digital reception signal RXI and outputs it.

The receiving device on the receiving side includes two correlators 21, 22° demodulator 23. Carrier detection circuit 24. It includes a synchronous control circuit 25 and the like. The digital reception signal RXI output from the reception interface 12B is branched into two and input into correlators 21 and 22, respectively. A Manchester code M sequence generated from one Manchester M sequence generator 31 is set in one correlator 21, and a correlation is taken between this set sequence and the received signal RXI. Similarly, the other correlator 22 is set with the Manchester code M sequence generated from the other Manchester M sequence generator 32.
The correlation between this setting sequence and the received signal RXI is taken. The correlation outputs obtained from these correlators 21 and 22 are given to a demodulator 23, in which a demodulated signal 1 or 0 is assigned according to the correlation value, and the received data R
Output as XD. That is, if the correlator 21 shows a larger correlation peak value among the correlation outputs of the correlators 21 and 22, the received data of 0 will be received by the correlator 22.
If the correlation peak value is larger than that of the correlation peak value, one received data is generated.

The correlation output is also input to carrier detection circuit 24 and synchronization control circuit 25. The carrier detection circuit 24 detects the presence or absence of a carrier based on the correlation output, and provides the detection signal to the synchronization control circuit 25. The presence or absence of a carrier is determined by the received signal RX.
This is used to determine whether or not I is being received. The synchronous control circuit 25 is.

When a carrier is being detected, a timing signal for demodulation and carrier detection is created based on the correlation output and is provided to the demodulator 23 and the carrier detection circuit 24.

As described above, in the CSK communication system, two correlation outputs are compared on the receiving side, and the output of the received data is determined depending on the magnitude.
Since the Manchester M sequence on the receiving side does not need to be strictly synchronized with that on the transmitting side, data demodulation errors do not occur. Furthermore, if the absolute value is taken as the output of the correlator, no error will occur even in the case of a transmission line with degraded characteristics such that the transmission peak value becomes negative. Furthermore, by using the Manchester code M sequence, it is possible to reduce the low-frequency components of the received signal and suppress the coupling loss with the transmission path.

(2) Configuration example of CSK modulation device FIG. 2 shows a specific configuration example of C5K modulation device II. Further, output signal waveforms of each part of this circuit are shown in FIG.

In this embodiment, each Manchester M-sequence generator 31, 32
is a three-stage (n-3) shift register FF++ to FF, 3
．． FF2□~FF2. These shift registers receive a clock signal CK output from a clock generator 34.
Data shift operation is performed at the timing of . The feedback circuits of these shift registers are different from each other. That is, in shift registers F F 1r to F F +3,
The codes of the cells in the second and third stages are determined by the exclusive OR circuit (EX
-OR) 31a to its input side, whereas shift register FF2. ~ In the FF 23, the codes of the first and third stage cells are fed back via the EX-OR circuit 32a. The shift register and its feedback circuit are connected to an M-sequence generator (PN code generator, PN code-PseudeNo.
ise Code=pseudo-noise code). Then, the sign output P of the final stage of each shift register
A Manchester code is created by taking the exclusive OR of NI, PN2 and the clock signal CK in EX-OR circuits 37 and 38, respectively.

When one Manchester M-sequence generator 31 has a specific phase (all 1), the other Manchester M-sequence generator 32
A phase synchronization circuit is provided so that the phase always remains constant (initial phase). This phase synchronization circuit includes a NAND circuit 36 and an initial phase setter 35. The initial phase setter 35 is a shift register FF2. This is used to set an initial code in each stage of the FF 23, and any code (other than all 0s) can be set. shift register FF,
When the codes of all stages of ~FF, , become 1 (this state occurs once in one period T of the Manchester code M series), an L level signal is generated from the NAND circuit 36, and the clock signal At the next rising edge of CK, the sign set in the initial phase setter 35 is transferred to shift register FF2. ~F
They are respectively loaded into each stage of F23.

As mentioned above, the outputs of the Manchester M-sequence generators 31 and 32, that is, the outputs of the EX-OR circuits 37 and 38, are given to the switching circuit 33, and are transmitted every period (data interval) T of the Manchester code M-series according to the transmission data TXD. A switching operation is performed. Further, the output of the NAND circuit 36 is given to a transmission data processing section (for example, a microprocessor) as a transmission request signal. Every time this transmission request signal is input, the transmission data processing section processes one bit of the transmission data TXD (
1 or O) and provides it to the switching circuit 33.

FIG. 4 shows a modification. Comparing with FIG. 2, we can see that EX-
The OR circuits 37 and 38 are removed, and instead, the output of the switching circuit 33 and the tarok signal C are connected to the output side of the switching circuit 33.
An EX-OR circuit 39 which receives K as an input is provided to create a Manchester code.

Reference numerals 31A and 32A each refer to an M-sequence generator, and their outputs (signs of the final stage of the shift register) are provided to a switching circuit 33, respectively. This modification has the advantage that the number of EX-OR circuits can be reduced by one.

Note that the output side of the switching circuit 33 in FIG. 2, EX- in FIG.
It is preferable to provide a one-clock latch circuit on the output side of the OR circuit 39 to shape the waveform of the transmission signal TXO.

(3) Configuration Example of Correlator Next, the configuration of the correlators 21 and 22 will be explained in detail with reference to FIG.

Each of the correlators 21 and 22 has nine stages of registers 41a.

41b, and these registers 41a, 41b.

Manchester M-sequence generator 31 included in modulation device 11
, 32 are respectively set in advance. The code length of the M sequence generated using an n-stage shift register is 2'-1 bits. Since the M sequence is Manchester encoded in the modulation device 11, the number of stages g of the registers 41a and 41b is Ω-2(2
'-1).

On the other hand, the digital reception signal RXI input from the reception interface 12B is branched into two branches and manually input to shift registers 42a and 42b provided in each correlator 21 and 22. These shift registers 42a and 42b also have N stages and are driven by a clock CK having twice the frequency of the clock signal in the modulation device 11.

In the correlator 21, the code of each set stage of the register 41a and the code of the received signal sent to the corresponding stage of the shift register 42a are respectively output to an EX-OR circuit 43.
Compare at a. The output signals of all EX-OR circuits 43a are given to an adder 44H and added together. Adder 4
The output signal 4a represents the degree of coincidence between the code of each stage of the register 41a and the code of each corresponding stage of the shift register 42a, and this is the correlation output R of one correlator 21.
It becomes 1. This is because the received signal RXI is sequentially shifted through the shift register 42a every clock signal CK.

The correlation output R8 also changes according to each clock signal CK.

Similarly, in the other correlator 22, the register 41
The EX-OR circuit 43b checks whether the sign of each stage set in b matches the sign of the received signal sent to the corresponding stage of the shift register 42b. The output signals of all EX-OR circuits 43b are sent to the adder 4
4b and is added. The adder 44b outputs a correlation output R indicating the degree of correlation between the Manchester M sequence set in the register 41b and the input digital received signal RXI.
5 will be output.

FIG. 6 shows a modification of the correlator 21. register 4
1a and the shift register 42a, the number of stages is ρXk.
(k is a positive integer of 2 or more) register 41A and shift register 42A are provided. The shift register 42A is driven by a clock signal CKk having twice the frequency of the clock signal CK. EX-OR circuit 43
gxk A are also provided, and the signs of the corresponding stages of the register 41A and shift register 42A are the same as each EX-OR circuit 43A.
Enter.

The adder 44A adds the output signals of all the EX-OR circuits 43A and outputs the result as a correlation output R6. In this way, by increasing the number of stages of registers and shift registers by m times, the accuracy of correlation calculation is improved.

It goes without saying that the correlator 22 can also be modified in the same way.

FIG. 7 shows yet another embodiment. Here, the shift register 42 to which the received signal RXI is input is the correlator 21.
and 22. By doing so, the number of shift registers can be reduced and the configuration can be simplified. It goes without saying that a shift register multiplied by the number of stages as shown in FIG. 6 can also be used as correlators 21 and 22 in the same way.

(4) Demodulator FIG. 8 shows an example of the configuration of the demodulator 23. Further, signal waveforms of each part in FIG. 8 are shown in FIG. 9. In this figure, the correlation outputs R, , Rb are drawn in analog form for easier understanding.

First, the principle of demodulating data based on correlation outputs R and R1 output from a pair of correlators 21 and 22 will be explained. Referring to FIG. 9, one data interval T (this is equivalent to one period of the Manchester M series) is divided into a central window part (referred to as the W part) and parts before and after it (this is referred to as the E part). Separate. The front and rear E portions are set at equal intervals.

However, it is not necessary to set the E sections before and after the W section equally, and the W section does not need to be set at the center of the data section. 0<
Using d that satisfies d<T.

The W part is an area from (T-d)/2 to (T+d)/2.

Part E is the section from 0 to (T-d)/2 and from (T+d)/2 to T.

It can be expressed as The W section is also called the observation section.

When data is being transmitted, a correlation peak appears in one of the correlation outputs R1 and R5 within the data interval T. In the synchronization control circuit 25, this correlation peak is detected, and a data section end signal ED is created which defines the end point of the data section so that the correlation peak is located at the center of the data section T. Then, based on this data section end signal ED, a window start pulse WL and a window start pulse WL, which define the start point and end point of the W section, respectively.
A stop pulse WH is generated by the synchronization control circuit 25.

The meanings of the symbols P 6w , p by -A-E, and A bE are defined as follows.

P, ,: Peak value (maximum value) at W portion of correlation output R1 P5. : Peak value (maximum value) of the correlation output R5 at the W section AaE: Total sum (added value) of the correlation output R1 at the E section A1. : Total sum (added value) of correlation output R5 in E part Demodulated data (received data RXD) is generated as follows.

If P by ・A, E> P 6w e A bg, the data is 1°Pbw・A IIE < P aw ”
A If hE, the data is O0 Theoretically speaking, p bw
> pay, the data is 1 degree; if the opposite, the data may be determined to be O. However, if noise is included, demodulation errors may occur when comparing peak values in correlation outputs. Generally, in a correlation output that has a correlation peak, the levels before and after the peak are smaller than the correlation level of a correlation output that does not have a correlation peak. For example, when the correlation output R1 has a correlation peak, the sum Adz before and after it is smaller than the sum AaB of the correlation output R1 without a correlation peak. Utilizing this property, in order to prevent demodulation errors as much as possible, the product of the peak value and the sum of mutually separate correlation outputs, that is, P b v - A a
This means that demodulated data is created by comparing the magnitudes of E and P ay' A bE. This makes it possible to perform stable demodulation even when the transmission characteristics of the transmission path are poor and noise is likely to occur.

Since the circuit shown in FIG. 8 is a digital circuit, it operates in synchronization with the clock signal CK or CK, but the illustration of the clock signal is omitted to simplify the explanation.

In this circuit, the correlation output R is latched by one clock in a latch circuit 51a, converted into an absolute value in an absolute value circuit 52a, and further provided to an adder circuit 55a and a maximum value hold circuit 54a. on the other hand.

A window start pulse WL and a window stop pulse WH are inputted to the window generating circuit 53, and a window signal WS which becomes H level at the W portion is outputted from this circuit 53. This window signal W
S is given as an operation control signal to the latch circuit 48 of the adder circuit 55a and the latch circuit 46 of the maximum value hold circuit 54a. In the adder circuit 55a, the latch circuit 48 operates only in the E section where the 2-into signal WS is at L level. .

Latch timing is of course defined by the clock signal. An adder 47 adds the correlation output R1, which is converted into an absolute value and is manually inputted, with the previous addition result given from the latch circuit 48 for each clock signal, and this addition result is latched by the latch circuit 48 again. In this way, data representing the sums A and E are obtained from the adder circuit 55a.
The signal is applied to a multiplier 56a.

The latch circuit 46 of the maximum value hold circuit 54a operates only in the W portion where the window signal WS is at H level. The comparator 45 compares the previous maximum value latched in the latch circuit 46 with the absolute value of the correlation value R1 input this time, and if the current correlation value is larger, the current correlation value is used as the new correlation value. It is latched in the latch circuit 46 as the maximum value. In this way, the peak value P is output from the maximum value hold circuit 54a.
Data representing 1w is obtained and applied to squaring multiplier 58b.

The same goes for the other correlation output R1.

A latch circuit 51b, an absolute value circuit 52b, a maximum value hold circuit 54b, and an adder circuit 55b are provided. Then, the peak value Pbw is output from the maximum value hold circuit 54b.
The summation AIIE is obtained from the adder circuit 55b and applied to 1 multipliers 56a and 56b.

The multiplier 58a multiplies Pbw・A, H by 1.
In b, multiplication of P, , -A)H is performed, respectively.

The multiplication result is given to comparator 57.

In the comparator 57, P, ・A, E and P a v 'A b
The magnitude of E is compared, and a signal representing 1 or 0 is output according to the comparison result, and a data section end signal E is output.
It is latched by the latch circuit 58 at timing D.

It is output as received data RXD. Addition circuits 55a and 55b are activated by this data section end signal ED.

Maximum value hold circuits 54a and 54b are reset.

(5) Carrier Detection Circuit FIG. 10 shows an example of the configuration of the carrier detection circuit 24. The carrier detection circuit 24 is a peak position detection circuit 26
．． Peak position determination circuit 27. Counting circuit 28 and m/
It is composed of an N determination circuit 29.

The peak position detection circuit 26 is a circuit for detecting at which position within the data interval T the peak of the correlation output is located, and as shown in FIG. 12, the peak position PP is the point at which the maximum value of the correlation output appears. A total of 1 TPI is defined as the time from the time to the data section end signal ED.

FIG. 11 shows an example of a peak position detection circuit, where the peak position is the position where the absolute value of the sum of the two correlation outputs R1 and R1 is the maximum value.

The two correlation outputs R1 and R1 are each given to an adder 61, added, and then converted into an absolute value by an absolute value circuit 64. This absolute value signal is applied to one input terminal of comparator 62 and latch circuit 63. When the signal ED indicating the end of the previous data section is applied to the latch circuit 63 as a latch timing signal via the OR circuit 85A, the output of the absolute value circuit 64 is latched as an initial value. The value latched in the latch circuit 63 is given as the other input of the comparator 62. Therefore, from then on, the value latched in the latch circuit 63 and the output value of the absolute value circuit 64 are sequentially compared in the comparison circuit 62 (every clock pulse of the clock signal CK), and When a large value output is obtained from the absolute value circuit 64,
The output of the comparator 62 passes through the OR circuit 65A to the latch circuit 6.
3, the output of the absolute value circuit 64 is latched into the latch circuit 63 as a new value. In this way, the maximum value is always latched in the latch circuit 63.

On the other hand, the counter 66 that counts the clock signal CK is
R circuit [Data section end signal ED input via i5B
Alternatively, it is reset (cleared) by the comparison output of the comparator 62 and starts counting again from zero. The count output of the counter 66 is latched by the latch circuit 67 when the next data period end signal ED is applied. The counter 66 counts the clock signal CK from the time when the peak value appears in the data interval T until the time when the signal ED indicating the end of the data interval T is applied. This count value is then latched by the latch circuit 67 and represents the peak position PP.

FIG. 13 shows another example of the peak position detection circuit.

Here, the one with the larger peak value in the absolute values of the two correlation outputs R,, R, is selected, and this selected peak position is output as the final peak position PP. In order to detect the peak position for each of the two correlation outputs R1 and R6.

Absolute value circuit 64 shown in FIG. Comparator 62. Latch circuit 63. OR circuits 85A, 85B and counter 66
is provided for each correlation output R-, Rb. 13th
In the figure, circuits corresponding to these are shown with the same reference numerals appended with a or b. Adder 61 is not provided.

The count values of counter 66a and counter 68b are provided to selector 69. Also, a latch circuit 63a.

[The maximum value latched in i3b is
8 and compared. Selector 69 is comparator 68
, and the correlation outputs R,,R.

The counter 66a or 66 which has a larger peak value
The count output of b is selected by the selector 69.

The signal is applied to the latch circuit 67. The latch circuit 67 latches the count output of the counter input through the selector 69 as the peak position PP at the time when the data section end signal ED is input.

FIG. 14 shows yet another example of the peak position detection circuit. The circuit shown in FIG. 14 differs from that shown in FIG. 11 only in that the adder 61 is not provided in FIG. Only a predetermined one of the correlation outputs R, , R, "is input to the peak position detection circuit shown in FIG. 14.

The peak position is detected by a synchronous peak position detection circuit,
Until synchronization is established, the above-mentioned C5K modulation device 11
At this point, transmission data of either 1 or 0 is sent out. That is, the switching circuit 33 is fixed to either side. In the peak position detection circuit shown in FIG.
or O) of the correlator corresponding to the correlation output (R, or R
, ) is selected as the human power.

Next, a specific example of the configuration of the peak position determination circuit 27 will be described in detail. The peak position determination circuit 27 is a circuit that divides one period (data section) T of the Manchester code M series into a plurality of areas and determines to which area the detected peak position PP belongs.

Many specific examples of how to divide a plurality of areas can be considered depending on the differences in the elements constituting one circuit. An area refers to a period (data interval) of a 1M sequence (PN sequence) divided into several intervals.

The size of the area can be any size that does not exceed one data interval, and the size of each area does not necessarily have to be the same, and each area may overlap with each other. .

FIG. 15 and FIG. 16 show a first example.

Here, as shown in FIG. 15, one data section T is equally divided into j (10) areas a-j so that the areas do not overlap each other. The starting position of each area,
The end positions are indicated by adding codes a-j representing areas to the codes LS and LE, respectively. For example, the start position of area a is LSa, and the end position is LEa. 1st
FIG. 6 shows a specific example of a peak position determination circuit configured using window comparators 718 to 7Ij. Each window comparator 71 (symbols 71a to 71
j is collectively represented by the reference numeral 71), the start position LS and end position LE of the corresponding area are set. Signals representing these positions LS and LE are created based on the data section end signal ED. The peak position PP detected by the peak position detection circuit 26 described above is provided to each window comparator 71. Each window/
The comparator 71 outputs an H level output signal (the output signal is also represented by a=j) when the input peak position PP is between the set start position LS and end position LE.

FIGS. 17 and 18 show a second example.

Here, one data section T is equally divided into j areas (10 areas) so that the areas do not overlap each other, as shown in FIG. 17. FIG. 18 shows a specific configuration of a peak position determination circuit using an AND circuit. Peak position P
P is expressed as a 4-bit binary number and only takes values from 0 to 9. Peak position determination circuit j AND circuits (
A 4-bit digital signal representing the peak position PP is input to each AND circuit 72. Each area a-j
are assigned addresses 9-0. As mentioned above, the peak position PP is counted from the data section end signal ED indicating the end of each data section T (see figure m12), so the address is area j as the starting address 0 and area a as the starting address.
is given as the end address 9. Each AND circuit 72a-72j is configured to output an H-level output signal (a-j) when the input peak position PP matches the address given to the corresponding area.

FIGS. 19 and 20 show a third example.

As shown in FIG. 19, the data section T is divided into j areas such that the area overlaps the adjacent area by 1/2 of the area length. ab each area.

Let be, ..., ja. FIG. 20 is composed of j window comparators 73 (ab and the like indicating areas are omitted). Each window comparator 7
3 is set with the start position LS and end position LE (ab, etc. indicating the area are omitted) of the corresponding area, and when the peak position PP is between these two positions, the H level is output from the corresponding window comparator 73. output signal (a b.

bc, etc.) are output.

FIG. 21 shows a fourth example, and this peak position determination circuit is constructed using an AND circuit and an OR circuit. The method of dividing the data section T is the same as that shown in FIG. The peak position determination circuit is the same AND circuit as shown in FIG.
It consists of a circuit 72 and j OR circuits 74 each receiving the outputs of two adjacent AND circuits 72 as inputs.

FIGS. 22 and 23 show a fifth example. As shown in FIG. 22, the data section T is divided into j areas such that 1/2 or more of the area length overlaps with the adjacent area. In the illustrated example, each area overlaps the adjacent area by 3/4. abed each area.

It is expressed as bcde etc. As shown in FIG. 23, the peak position determination circuit can be constructed of j window comparators 75 (numerals ad, ce, etc. that simply indicate areas are omitted). Needless to say, the start position and end position of each window comparator 75 are determined according to the corresponding area.

FIG. 24 shows a sixth example, and this peak position determination circuit is constructed using an AND circuit and an OR circuit. The method of dividing the data section T is the same as that shown in FIG. The peak position determination circuit is the same AND circuit as shown in FIG.
It is composed of a circuit 72 and j OR circuits 76 each receiving the output signals of four adjacent AND circuits 72 as inputs.

FIG. 25 shows a specific example of the configuration of the counting circuit 28 and the m/N determining circuit 29. These circuits.

A synchronization signal (carrier detection signal) is output when it is determined that the peak position PP belongs to one of the above areas a predetermined number of times (N≧m) during a predetermined N consecutive data cycles. be. For simplicity, the peak position determination circuit 27 shown in FIG. 16 or 18 is used, and its output is a.

Let b, c, ..., j.

Output signals a, b, c of the peak position determination circuit 27.

..., j, and a counter 84 for counting the number of elapsed data periods T are provided. Counters 80a to 80j take in an input signal for each data period end signal ED, and if it is at H level, increment the count value by one.

Counters 80a, 80b, 80c, -=,
The count value of 80j is determined by the comparator 81 to which a predetermined number m is set.
a, 81b.

81C1, . . . , 81j are compared with a predetermined number m, and when the count value reaches m, an H level signal is output from the comparator. The output signals of the comparators 81a to 81j are sent to the set input terminal of a flip-flop 83 via an OR circuit 82 (the output of the OR circuit 82 is referred to as a synchronization establishment signal).

On the other hand, the count value of the counter 84 is the data interval end signal ED.
is incremented by 1 for each input. The count value of the counter 84 is compared with a set number N in a comparator 85, and when the count value reaches N, the comparator 85 outputs an N data cycle end signal NEND at H level. This signal NEND passes through an OR circuit 86 to counters 80a to 80j and 84.
is given and these counters are reset. As a result, the counters 80a to 80j, 84 start counting from 0 again.

Therefore, before the end of N data periods, counter 8
When the count value of any one of 0a to 80j reaches m, the flip-flop 83 is set.

An L level synchronization signal will be output.

Since the output signal of the OR circuit 82 is also given to the OR circuit 86, the counters 80a to 80j and 84 will be reset if the synchronization signal is output even before N data periods have elapsed.

When the N data cycle end signal NEND is output, the count value of any of the counters 80a to 80j is m.
If the output of the OR circuit 82 has not reached the L level, this is inverted by the NOT circuit 87 and ANDed.
input to circuit 88; The AND circuit 88 has a signal NEND.
Because it is input.

The flip-flop 83 is reset by the output of the AND circuit 88. The output of the AND circuit 88 means an out-of-synchronization signal. As mentioned above, the counters 80a to 80j
, 84 are reset by the signal NEND, and the carrier detection operation is started again.

FIG. 25 shows, as mentioned above, the counting circuit 2 shown in FIG.
8 and m/N determination circuit 29, but if the circuit of FIG. 25 is forced to be classified into these two circuits.

Counters 80a to 80j and counter 84 belong to counting circuit 28, and other circuits belong to m/N determination circuit 29.

In the circuit shown in FIG. 25, when the count value of any one of the counters 80a to 80j reaches a predetermined number m, a synchronization signal (carrier detection signal) is output without waiting for N data periods to pass.

On the other hand, the circuit shown in FIG. 26 is modified to determine whether the count value of any one of the counters 80a to 80j is equal to or greater than a predetermined number m at the end of N data periods. It is.

An AND circuit 89 is connected between the OR circuit 82 and the set input terminal of the flip-flop 83. Further, the OR circuit 86 is omitted, and the counters 80a to 80j,
84 is reset only by the N data period end signal NEND. The output of the OR circuit 82 is applied to one input terminal of the AND circuit 89, and the N data period end signal NEND is applied to the other input terminal. Therefore, at the time when the N data period end signal NEND is output, if the output of the OR circuit 82 is at H level (that is, the count value of any one of the counters 80a to 80j is m
or above), the flip-flop 83 is set,
A synchronization establishment signal is output. The other configuration of the circuit shown in FIG. 26 is the same as that shown in FIG. 25.

FIG. 27 shows another embodiment of the carrier detection circuit. Peak position P detected by the peak position detection circuit
P is stored in the peak position storage section 9 for each data section end signal ED.
It is stored in o. This peak position storage section 90 sequentially stores peak positions PP for M data periods in the past. The predetermined number M may be equal to or greater than the predetermined number N described above.

The M times of peak position PP data stored in the peak position storage section 90 are given to a counter 91 . The predetermined number N is set in the counter 91. The counter 91 determines which area each given peak position belongs to which is divided into a predetermined number within the data interval, counts the number of peak positions belonging to each area, and calculates the number of peak positions that belong to each area. output the number and feed it to comparators 92 and 93.

The above predetermined number m is set in these comparators 92 and 93. The comparator 92 outputs a carrier detection signal when the maximum value of the count value at the peak position given by the counter 92 is greater than or equal to a predetermined number m. Further, the counter 93 is the counter 91
If the maximum value of the count values given by is less than m, a carrier disconnection detection signal is output.

The above operation is preferably performed every time the data interval end signal ED is generated. Counter 91 can be realized by, for example, a microprocessor.

FIG. 28 shows yet another embodiment of the carrier detection circuit. In FIG. 28, the same components as those shown in FIG. 27 are given the same reference numerals. In this embodiment, two counters 9
A switching circuit 94 for switching the predetermined number N set to 1 to N' and a switching circuit 95 for switching the predetermined number m set to the comparator 92 to m' are provided. It is controlled by a carrier presence/absence detection signal (carrier detection, carrier disconnection detection signal) output from 92.

When the comparator 92 detects the absence of a carrier, N and m are selected as the set numbers and provided to the counter 91 and the comparator 92, respectively. When comparator 92 detects the presence of a carrier, N' and m' are selected and applied to counter 91 and comparator 92, respectively. That is, the carrier detection operation is performed using the set numbers N and m, and the carrier disconnection detection operation is performed using the set numbers N' and m'. The number of these settings is N.

N', m, and m' can be set arbitrarily, but preferably m/N>m'/N'.

The idea of switching the set numbers N and m depending on the presence or absence of a carrier can also be applied to the circuits shown in FIGS. 25 and 26. FIG. 29 shows an embodiment in which this concept is applied to the circuit of FIG. 26. The set numbers N and N' given to the comparator 85 and the set numbers m and m' given to the comparators 8La to l1ilj are respectively switched in accordance with the carrier detection (or carrier disconnection detection) signal output from the flip-flop 83. Switched by circuits 94 and 95.

Finally, the circuit for generating the data section end signal ED will be briefly explained with reference to FIG.

In FIG. 30, a window type digital comparison circuit consisting of comparators 108, 109 and an AND circuit 110 is provided. This circuit determines whether the detected peak position PP is within the set W section (observation section). One comparator 108
is set with data representing the start position of the W portion, and data representing the stop (end) position of the W portion is set in the other comparator 109, and the data representing the peak position PP is set between these start and stop positions. Only when the signal is between the two positions, the AND circuit 100 outputs an H level determination signal.

Furthermore, two registers 102 and 103 are provided. Data representing the peak position PP is given to the register 102, and (3/2)T-P
Data representing P is set.

As described above, T is data representing the length (time) of the data section. On the other hand, data T is set in the register 103. The selector 104 selects one of the setting data of these registers 102 and 103 according to the state of the determination signal and applies it to one input of the digital comparator 105.

On the other hand, the counter 101 counts the clock signal CK and provides the count output to the other input of the digital comparator 105. Comparator 105 generates a data period end signal (match signal) ED when the count value of counter 101 becomes equal to the setting data applied through selector 104. The counter 101 is reset by this signal ED and starts counting again from zero.

Now, since the correlation output and the data section are not synchronized when the power is turned on, there may be no correlation peak in the W section. At this time, the determination signal outputted from the AND circuit 110 becomes L level, and the selector 104 selects the setting data of the register 102 and applies it to the comparator 105. This setting data (3/2) T-PP has a length (time) from the primary peak to the next data section end signal of T.
This is for generating the secondary data section end signal ED so that the signal becomes /2. In this way.

When the peak position is located within the W section, the determination signal becomes H level, and the selector 104 selects the register 103.
Since the setting data T is selected, the data section end signal ED will be generated at the period T from then on.

If necessary, a synchronization tracking circuit is further provided to determine the peak position PP.
It may be controlled so that it is always located approximately at the center of the W portion.

Effects of the Invention According to the present invention, the correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length is detected over a maximum of a first predetermined number N consecutive periods for each cycle of the code sequence. Ru. It is determined to which area the detected peak position belongs among the areas divided into a plurality of areas within the one cycle, and the number of detected peaks belonging to that area is counted for each area. Then, it is determined whether or not the detection peak count value in any one area has reached a second predetermined number m during the first predetermined number N periods at most, and if it has reached the second predetermined number m, carrier detection is determined. Ru.

According to this invention, carrier detection is determined if a peak is observed m times in N cycles in any of a plurality of areas divided within one cycle of the code sequence, so that the correlation peak position fluctuates. too.

As long as the carrier is continuously located near the position after the change, carrier detection can be performed, and carrier detection can be performed normally regardless of the deterioration of the characteristics of the transmission path.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a C3K communication system. FIG. 2 is a circuit diagram showing an example of the configuration of the modulation device, and FIG. 3 is a time chart showing its operation. FIG. 4 is a circuit diagram showing another example of the modulation device. FIG. 5 is a circuit diagram showing an example of the configuration of a pair of correlators. FIG. 6 is a circuit diagram showing a modification thereof, and FIG. 7 is a circuit diagram showing another example of the configuration of the correlator. FIG. 8 is a circuit diagram showing an example of the configuration of the demodulator, and FIG. 9 is a waveform diagram showing its operation. FIG. 10 is a plot diagram showing the configuration of the carrier detection circuit. FIG. 11 is a block diagram showing the configuration of the peak position detection circuit, and FIG. 12 is a waveform diagram showing the peak position detection operation. FIG. 13 is a block diagram showing another example of the peak position detection circuit, and FIG. 14 is a block diagram showing still another example of the same circuit. FIG. 15 is an explanatory diagram showing how one period of the M sequence is divided into a plurality of areas so as not to overlap. FIG. 16 is a circuit diagram showing an example of a peak position determination circuit suitable for the area division shown in FIG. 15. FIG. 17 is an explanatory diagram showing how one period of the M sequence is divided into multiple areas without overlapping, and FIG. 18 is a circuit diagram showing an example of a peak position determination circuit suitable for the area division in FIG. 17. be. FIG. 19 is an explanatory diagram showing how one period of the M sequence is divided into multiple areas so as to overlap 1/2 with the adjacent area;
This figure is a circuit diagram showing an example of a peak position determination circuit suitable for the area division shown in FIG. 19. FIG. 21 is a circuit diagram showing another example of the peak position determination circuit suitable for the area division shown in FIG. 19. Fig. 22 is an explanatory diagram showing how one period of the M sequence is divided into multiple areas so as to overlap with the neighboring area by 1/2 or more, and Fig. 23 is an illustration of a peak position determination circuit suitable for the area division in Fig. 22. FIG. 2 is a circuit diagram showing an example. FIG. 24 is a circuit diagram showing another example of the peak position determination circuit suitable for the area division shown in FIG. 22. FIG. 25 is a block diagram showing an example of a counting circuit and an m/N determination circuit, and FIG. 26 is a block diagram showing a modification thereof. FIG. 27 is a block diagram showing another embodiment of the carrier detection circuit, and FIG. 28 is a block diagram showing still another embodiment. FIG. 29 is a block diagram showing still another example of the counting circuit and m/N determination circuit. FIG. 30 is a block diagram showing an example of a circuit that generates the data section end signal ED. 31 and 32 show a conventional SS communication system, FIG. 31 is a circuit diagram showing the configuration, and FIG. 32 is a time chart showing its operation. 26...Peak position detection circuit. 27...Peak position determination circuit. 28... Counting circuit. 29...m/N judgment circuit. 90...Peak position storage unit. 91...Counter. 9293... Comparator. 94, 95...Switching circuit. that's all

Claims (21)

[Claims] (1) Detect the correlation peak position of a correlation signal between the received signal and a code sequence of a predetermined code length, for each period of the code sequence, for a maximum of a first predetermined number of consecutive N periods, and Determine which area the peak position belongs to among the areas divided into a plurality of areas within the one cycle, count the number of detected peaks belonging to that area for each area, and calculate the maximum number of detected peaks that belong to the area, A carrier detection method that determines whether the detected peak count value in any one area has reached a second predetermined number m during several N periods, and outputs a carrier detection signal if it has reached the second predetermined number m. (2) If the detected peak count value in any area does not reach the second predetermined number m during the first predetermined number N cycles, it is determined that carrier disconnection is detected. 1
).The carrier detection method described in ). (3) Maximum, if the detected peak count value in any area does not reach the second predetermined number m during the first predetermined number N cycles, the peak position detection and counting of the number of detected peaks is performed. The carrier detection method according to claim 1, wherein: is repeated for a maximum of the first predetermined number N cycles. (4) The carrier detection method according to claim 1, wherein the detected peak positions are stored over the first predetermined number of N cycles or more, and the peak number counting process is performed using the stored peak position data. (5) Two types are set as the first predetermined number and the second predetermined number, and in response to the carrier detection or the carrier disconnection detection, the two types of first and second predetermined numbers are set respectively. The carrier detection method according to claim 2, wherein the carrier detection method is switched. (6) The carrier detection method according to claim (1), wherein correlation signals between the received signal and two types of code sequences are respectively created, and a peak position of a sum signal of these two correlation signals is detected. (7) Claim (1) wherein correlation signals between the received signal and two types of code sequences are respectively created, and it is determined to which area the peak position of the larger of the peak values of these two correlation signals belongs. The carrier detection method described in . (8) The carrier detection method according to claim (1), wherein a correlation signal between the received signal and a predetermined one of two types of code sequences is created, and its peak position is detected. (9) The carrier detection method according to claim (1), wherein the plurality of areas are divided so that they do not overlap each other in one cycle of the code sequence. (10) The carrier detection method according to claim (1), wherein the plurality of areas are set to partially overlap with adjacent areas in one period of the code sequence. (11) A peak position detection circuit that detects a correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length every cycle of the code sequence, and the detected peak position is detected within the one cycle. A peak position determination circuit that determines which area it belongs to among a plurality of divided areas, and for each area, detects the number of detected peaks determined to belong to that area over a maximum of a first predetermined number of consecutive N periods. a counting circuit for counting, and a maximum of the first predetermined number N;
Determining whether the detected peak count value in any one area has reached a second predetermined number m during the period,
A carrier detection device comprising: an m/N determination circuit that outputs a carrier detection signal if the carrier detection signal is reached. (12) According to claim (11), further comprising a circuit that resets the count value of the counting circuit in response to a carrier detection signal or an N cycle end signal indicating that the first predetermined number of N cycles has passed. carrier detection device. (13) In response to the N period end signal indicating that the first predetermined number of N periods has elapsed, the generation of the carrier detection signal from the m/N determination circuit is controlled, and the count value of the counting circuit is controlled. Claims comprising a circuit for resetting (
11) The carrier detection device according to item 11). (14) A peak position detection circuit that detects a correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length for each period of the code sequence. storage means for storing detected peak positions over a first predetermined number N or more consecutive cycles; and storage means for storing detected peak positions over a first predetermined number N or more consecutive cycles; and storage means for storing detected peak positions for a first predetermined number N consecutive cycles; determine which area it belongs to among the areas divided into multiple areas, count the number of peak positions determined to belong to each area, and calculate the peak position count value in any one area to a second predetermined area. A second predetermined number m is determined.
A carrier detection device comprising: determining means for determining carrier detection if the above is the case. (15) A claim further comprising means for determining carrier disconnection detection if the detected peak count value in any area is equal to or less than a second predetermined number m in the first predetermined number N periods at maximum. 11) or the carrier detection device according to (14). (16) A claim further comprising switching means for switching between two types of predetermined numbers respectively set as the first predetermined number and the second predetermined number in response to the carrier detection or the carrier disconnection detection. (11) or (14)
). (17) Claim (11), wherein the peak position detection circuit detects the peak position of a sum signal of two correlated signals obtained by correlating the received signal with two types of code sequences. Or the carrier detection device according to (14). (18) The peak position detection circuit detects the peak position of the larger peak value of the two correlation signal peak values obtained by correlating the received signal with two types of code sequences. A carrier detection device according to claim (11) or (14). (19) Claim (11), wherein the peak position detection circuit detects the peak position of a correlation signal between the received signal and a predetermined one of two types of code sequences.
Or the carrier detection device according to (14). (20) The carrier detection device according to claim (11) or (14), wherein the plurality of areas are divided so that they do not overlap each other in one period of the code sequence. (21) The carrier detection device according to claim (11) or (14), wherein the plurality of areas are set to partially overlap with adjacent areas in one cycle of the code sequence.