JPH03207134A - Method and device for establishing synchronization - Google Patents

Abstract

PURPOSE:To enable accurate demodulation by observing a correlation peak for N cycles of a code sequence and generating a cycle signal so that the position of the correlation peak whose synchronized state is decided is in the center of a cycle of the code sequence. CONSTITUTION:A detecting circuit 26 detects the correlation peak position of the correlation signal between a reception signal and the code sequence with specific length for N continuous cycles in each cycle of the code sequence. A decision circuit 27 decides which of divided areas the detected peak position belongs to in one cycle and a counting circuit 28 counts detected peaks belonging to each area. Then an m/N decision circuit 29 decides whether or not the detected peak counted value of one of the areas reaches a specific number (m) in N cycles and considers that synchronism is established when the specific number (m) is reached. The cycle signal is so generated that the peak position reaching the specific number (m) is in the center of the cycle of the code sequence. Consequently, the accurate demodulation is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a method and apparatus for establishing synchronization in a receiving device for spread spectrum (SS) communications.

The conventional SS communication system has been widely applied to power line communication as well as satellite communication and mobile communication. The conventional SS communication system will be explained with reference to FIGS. 31 and 32. On the transmitting side, the output a of the PN (pseudo-noise) code sequence generator 1 is subjected to an EX-OR operation (signal C) with the transmission data b by an EX-OR circuit 2. The amplifier 3 sends it out to the transmission line as a transmission signal. On the receiving side, the received signal is amplified by an amplifier 4, then correlated with the output d of the synchronous PN code sequence generator 5 by a correlator 6, and the correlation value (signal e) is compared with a predetermined threshold value by a comparator 7. Demodulate the received data f.

The transmission path may be wireless, wired, or other transmission media. Therefore, the transmission signal is not only sent directly to the transmission medium, but also often converted into a signal suitable for transmission through the transmission medium before being sent. Also, power line communication requires an interface that separates it from commercial power. The connection portion with the transmission medium that performs such signal conversion and separation is hereinafter referred to as a reception interface and a transmission interface.

In the conventional communication system, the PN sequence generated by the synchronous PN code sequence generator 5 on the receiving side must be synchronized with the PN sequence on the transmitting side, and for this purpose, it is first necessary to search for a synchronization point. If there is no problem with the transmission characteristics of the transmission path, a peak is detected in the correlation waveform at the synchronization point. However, in power line communications, where the transmission characteristics are extremely poor and there are dip points within the transmission band, the correlation waveform deteriorates significantly, and the positive and negative relationships between correlation values are reversed, causing problems in data demodulation. This may result in an error. Another drawback was that synchronization could not be maintained due to waveform deterioration.

The inventors have developed a new CSK (Code Shift Key) that overcomes the drawbacks of the conventional SS communication method.
ng) communication system (Tsumura et al.; "High-performance electric line SS modem" Institute of Electronics, Information and Communication Engineers (IEICE) Spread Spectrum Technology and Its Applications Study Group March 22. 19
89SSTA89-8).

In the CSK communication system, on the transmitting side, two binary PN code sequences with low cross-correlation and the same code length are generated at a fixed cycle, and at each fixed cycle, the above two PN code sequences are generated depending on whether the transmitted data is 1 or 0. One of the different PN code sequences is selected and sent as a transmission signal. On the other hand, on the receiving side, two correlation outputs are obtained by correlating the received signal with the two PN code sequences used on the transmitting side. A correlation peak always appears in one of the two correlation outputs at each of the above-mentioned fixed periods. Therefore, 2
Demodulated data of 1 or O is created based on the comparison of the peak values of the two correlation outputs.

In such a CSK communication system, two correlation outputs are compared on the receiving side. Since 0 or 1 of the received data is assigned depending on the magnitude of the peak value, the code sequence on the receiving side does not need to be strictly synchronized with that on the transmitting side. Furthermore, if the absolute value is taken as the output of the correlator, there is an effect that data demodulation errors will not occur even in the case of a transmission line with deteriorated characteristics such that the sign of the transmission peak value is reversed.

As described above, a correlation peak appears in one of the two correlation outputs at each of the above-mentioned fixed periods. In order to correctly detect this correlation peak on the receiving side, it is necessary to synchronize the operation of the receiving side device with the received signal so that the correlation peak appears periodically within a certain interval. especially,
In the case of power line communication, transmission characteristics may change rapidly in poor transmission lines such as commercial AC power lines, and the peak position may fluctuate greatly.

In the CSK communication system described above, a correlation peak of a correlation signal between a received signal and a code sequence of a predetermined code length is detected, and a position of this correlation peak within a data interval of a period corresponding to the code length is detected. Then, it is determined whether this peak position is within the observation interval set within the data interval. Then, when it is determined that the peak position exists within the observation interval a predetermined number of times consecutively, it is determined that carrier detection, that is, synchronization has been established.

In this way, in the CSK communication system proposed by the inventors, it is determined that a carrier is present when the correlation peak of a correlation signal is detected a predetermined number of times in a row within a predetermined observation interval. When the correlation worsens, the correlation peak position changes,
It has been found that even though carriers are present, carrier detection may not be performed normally because the correlation peak position deviates from the observation interval.

Problems to be Solved by the Invention Therefore, the inventors proposed a carrier detection method and device that can solve the above problems (December 1999).
Patent application filed on March 12, filed by the same applicant and agent as the present application, title of the invention "Carrier detection method and device").

This carrier detection method detects the correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length over a maximum of a first predetermined number N periods for each cycle of the code sequence, and It determines which area the position belongs to among the multiple areas divided within one cycle with overlap allowed, and counts the number of detected peaks belonging to that area for each area. Determine whether or not the detected peak count value in any one area has reached a second predetermined number m during the first predetermined number N periods at maximum, and output a carrier detection signal if it has reached the second predetermined number m. It is something.

Therefore, in one of the multiple areas divided by allowing overlap within one period of the code sequence, m out of N periods
If a peak is observed, carrier detection is determined, so even if the correlation peak position fluctuates, carrier detection is possible as long as the correlation peak is continuously located near the position after the fluctuation, and the characteristics of the transmission path may deteriorate. Carrier detection can now be performed normally regardless of the situation.

Assuming such a carrier detection method, in order to perform accurate demodulation on the receiving side, it is necessary to create a signal that is correctly synchronized with the correlation peak position detected as described above.

This invention observes N periods. The present invention provides a method and apparatus for creating a periodic signal for demodulation suitable for establishing synchronization when the peak position is within the same area m or more times.

Means for Solving the Problems A synchronization establishment method according to the first invention sets the correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length to a maximum value for each cycle of the code sequence. Detection is performed over a first predetermined number of N periods, and it is determined to which area the detected peak position belongs among a plurality of areas divided with overlap allowed within the one period, and for each area,
Count the number of detected peaks belonging to that area. At maximum, during the first predetermined number N cycles, it is determined whether the detected peak count value in any one area has reached the second predetermined number m, and if it has, synchronization is established and synchronization is performed. is established, a periodic signal representing the period is created such that the peak position at which the detected peak count reaches a second predetermined number m is located at the center of the period of the code sequence. .

A synchronization establishment device according to a second invention includes a peak position detection circuit that detects a correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length for each cycle of the code sequence; However, the peak position determination circuit determines which area it belongs to among the plurality of areas divided by allowing overlap within one cycle, and for each area, the maximum number of detected peaks determined to belong to that area is calculated. , 1st
a counting circuit that counts over a predetermined number of N cycles, and determines whether the detected peak count value in any one area has reached a second predetermined number of m during the first predetermined number of N cycles; An m/M determination circuit that outputs a synchronization establishment signal if it has been reached. and the peak position where the detected peak count value has reached a second predetermined number m, and
/ When the synchronization establishment signal is output from the N judgment circuit,
The present invention is characterized in that it includes a periodic signal generation circuit that generates and outputs a periodic signal representing the period so that the stored peak position is at the center of the period of the code sequence.

The synchronization establishment method according to the third invention detects a correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length every cycle of the code sequence, and converts the detected peak position into a first predetermined number of signals. For each of the peak positions of the first predetermined number of N cycles that are stored over N cycles, to which area they belong among the plurality of areas divided with overlap allowed within the one cycle? and counting the number of peak positions determined to belong to each area, and determining whether the peak position count value in at least one of the areas is equal to or greater than a second predetermined number m;
If it is equal to or greater than the second predetermined number m, it is determined that synchronization has been established, and a weighted average peak position with respect to the stored peak position is calculated, and when it is determined that synchronization is established, the calculated weighted average peak position has the above sign. The method is characterized in that a periodic signal representing the period is created so as to be centered within the period of the series.

A synchronization establishment device according to a fourth aspect of the present invention includes a peak checking means for detecting a correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length every cycle of the code sequence; For each of the stored peak positions for a predetermined number of N cycles of the first predetermined number of N cycles, each of them is divided into a plurality of areas that are allowed to overlap within one cycle. Determine which area it belongs to, count the number of peak positions determined to belong to each area, and check whether the peak position count value in at least one of the areas is equal to or greater than a second predetermined number m. determining means for determining that synchronization has been established if the second predetermined number m or more; calculating means for calculating a weighted average peak position with respect to the peak position stored in the storage means; and when it is determined that synchronization has been established. The present invention is characterized by comprising periodic signal generating means for generating and outputting a periodic signal representing the period so that the weighted average peak position calculated by the calculation means is located at the center within the period of the code sequence. do.

There are various ways to calculate the weighted average peak position, as will become clear from the examples shown later.

According to the first and second inventions, the correlation peak position of the correlation signal between the received signal and the code sequence of a predetermined code length is maintained for a maximum of the first predetermined number of N periods for each period of the code sequence. Detected. It is determined to which area the detected peak position belongs among the multiple areas divided within one period with overlap allowed, and for each area,
The number of detected peaks belonging to that area is counted. At most, it is determined whether the detected peak count value in any one area has reached the second predetermined number m during the first predetermined number N cycles, and if it has reached the second predetermined number m, it is considered that synchronization has been established. Then, when synchronization is established, a periodic signal representing the period is created and output such that the peak position where the detected peak count reaches a second predetermined number m is at the center of the period of the code sequence. be done.

According to the third and fourth inventions, the correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length is detected every cycle of the code sequence.

The detected peak positions are stored over a first predetermined number N periods. For each of the stored peak positions for the first predetermined number of N periods, it is determined to which area they belong among the plurality of areas divided with overlap allowed within the one period, and each of the peak positions is determined. The number of peak positions determined to belong to the area is counted. It is determined whether the peak position count value in at least one area is greater than or equal to a second predetermined number m, and the second predetermined number m is determined.
If this is the case, it is determined that synchronization has been established. On the other hand, a weighted average peak position regarding the stored peak positions is calculated. Then, when it is determined that synchronization is established, a periodic signal representing the period is created and output so that the calculated weighted average peak position is at the center of the period of the code sequence.

Embodiment Overall configuration of mcsx communication system FIG. 1 shows the overall configuration of a CSK type communication system using the Manchester code M sequence.

On the transmitting side, the modulating device (transmitting device > 11) uses a Manchester code M with low cross correlation and the same code length.
Two Manchester M's each generated by synchronizing the series.
Sequence generator 31. 32 are provided, and their code outputs are given to a switching circuit 33. This switching circuit 33 is controlled according to the binary transmission data (1 or O). For example, when the transmission data is 0, the code output of the generator 31 is
When the signal is 1, each code output of the generator 32 is selected. The code output signal selected by this switching circuit 33 becomes the transmission signal TXO. Switching control in the switching circuit 33 is performed in synchronization with the cycle of the generated Manchester code M series, and one piece of binary data (1 or O) is expressed by one cycle of the Manchester code M series.

This modulation method is called code shift keying (CSK) because the switching or selection of two different Manchester code M sequences is performed depending on the code (1 or 0) of the data to be transmitted.

Of course, CSK is not limited to the Manchester M sequence, and other PN code sequences may be used.

The transmission signal TXO is sent out to the transmission line or transmission medium via the transmission interface 12A. As shown in the "Prior Art" section, the transmission interface 12A is a connection section in a broad sense, and is a section that performs carrier modulation, mixing processing into a power line, and the like.

The reception interface 12B also performs carrier demodulation, separation from the power line, A/D conversion, etc., and converts the signal input from the transmission path or transmission medium into a digital reception signal RX.
Convert to I and output.

The receiving device on the receiving side includes two correlators 21 and 22, a demodulator 23, a carrier detection circuit 24, and a synchronization control circuit 25.
etc. are included. The digital reception signal RXI output from the reception interface 12B is branched into two parts, each of which is sent to a correlator 21. 22. One correlator 2l
A Manchester code M sequence generated from one Manchester M sequence generator 31 is set in , and the correlation between this set sequence and the received signal RXI is taken. Similarly, the other Manchester M-sequence generator 3 is connected to the other correlator 22.
A Manchester code 'M sequence generated from 2 is set, and the correlation between this set sequence and the received signal RXI is taken. These correlators 21. The correlation output obtained from 22 is given to a demodulator 23, in which a demodulated signal 1 or 0 is assigned depending on the correlation value. It is output as received data RXD. That is, the correlator 21
If the correlator 2l shows a larger correlation peak value among the correlation outputs of received data are generated respectively.

The correlation output is also input to the carrier detection circuit 24 and the synchronization control circuit 25. The carrier detection circuit 24 detects the presence or absence of a carrier based on the correlation output, and provides the detection signal to the synchronization control circuit 25. The presence or absence of a carrier is determined by the received signal RX.
This is used to determine whether or not I is being received. When a carrier is detected, the synchronization control circuit 25 generates a timing signal for demodulation and carrier detection (a data interval end signal ED to be described later) based on the correlation output.
) is created and provided to the demodulator 23 and carrier detection circuit 24.

As described above, in the CSK communication system, two correlation outputs are compared on the receiving side, and the received data is zeroed depending on the magnitude.
Since the Manchester M sequence on the receiving side does not need to be strictly synchronized with that on the transmitting side. Also, if you take the absolute value as the output of the correlator. Demodulation errors will not occur even in the case of a transmission line with deteriorated characteristics such that the sign of the transmission peak value is reversed. Furthermore, by using the Manchester code M sequence, it is possible to reduce the low frequency components of the received signal and to suppress the coupling loss with the transmission path.

(2) Configuration example of CSK modulation device FIG. 2 shows a specific configuration example of the CSK modulation device 11. Further, output signal waveforms of each part of this circuit are shown in FIG.

In this embodiment, each Manchester M-sequence generator 31. 3
2 is a three-stage (n-3) shift register FF,, ~FFl
3, FF21 to FF2, and these shift registers receive the clock signal C output from the clock generator 34.
A data shift operation is performed at timing K. The feedback circuits of these shift registers are different from each other. In other words, in shift registers FF, ...FF13, the codes of cells in the second and third stages are determined by exclusive OR circuit
OR) 31a to the human power side, whereas in the shift register FF2+-FF23, the codes of the cells in the first and third stages are fed back through the EX-OR circuit 32a. There is. The shift register and its feedback circuit are connected to an M-sequence generator (PN code generator, PN code-Pseud
eNoise Code (Pseudo Noise Code). Then, the exclusive OR of the code outputs PNI, PN2 of the final stage of each shift register and the clock signal CK is determined by the EX-OR circuit 37. 38 to create a Manchester code.

When one Manchester M-sequence generator 3l has a specific phase (all 1), the other Manchester M-sequence generator 32
A phase synchronization circuit is provided so that the phase always remains constant (initial phase). This phase synchronization circuit includes a NAND circuit 3B and an initial phase setter 35. The initial phase setter 35 is for setting an initial code in each stage of the shift registers FF2 to FF23, and can set any code (a code other than all 0). shift register FF
,, ~F F . When the codes of all stages of 3 become 1 (this state occurs once in one period T of the Manchester code M series), an L level signal is generated from the NAND circuit 36, and the next signal of the clock signal CK is generated. The sign set in the initial phase setter 35 at the rising edge of the shift register FF
2, to FF2, respectively.

Manchester M-sequence generator 31. as described above. 32 output, that is, the EX-OR circuit 37. The output of 38 is given to a switching circuit 33, and a switching operation is performed every period (data interval) T of the Manchester code M sequence according to the transmission data TXD. Further, the output of the NAND circuit 3B is given to a transmission data processing section (for example, a microprocessor) as a transmission request signal. The transmission data processing section outputs one bit (1 or 0) of the transmission data TXD each time the transmission request signal is inputted, and supplies it to the switching circuit 33.

FIG. 4 shows a modification. Compare with Figure 2. Manchester M-sequence generator 31. EX each from 32
-OR circuit 37. 38 was removed. Instead, an EX-OR circuit 39 is provided on the output side of the switching circuit 33, and receives the output of the switching circuit 33 and the clock signal CK.
A Manchester code is created.

Reference numerals 31A and 32A each refer to an M-sequence generator, and their outputs (signs of the final stage of the shift register) are provided to a switching circuit 33, respectively. This modification has the advantage that the number of EX-OR circuits can be reduced by one.

Note that the output side of the switching circuit 33 in FIG. 2 and the EX- in FIG.
It is preferable to provide a one-clock latch circuit on the output side of the OR circuit 39 to shape the waveform of the transmission signal TXO.

(3) Configuration example of correlator Next, correlator 21. The configuration of 22 will be explained in detail with reference to FIG.

Correlator 21. 22 are p-stage registers 41a,
4lb, and these registers 41a and 4lb contain the Manchester M-sequence generator 3 included in the modulation device 11.
1. The Manchester code M sequences generated in 32 are set in advance. The code length of the M sequence generated using an n-stage shift register is 2''-1 bits. Since the M sequence is Manchester encoded in the modulator 1l, the number of stages g of the registers 41a and 4lb is N-2.
(2'-1).

On the other hand, the digital reception signal RXI input from the reception interface 12B is branched into two, and each correlator 21. 22
The signals are input to shift registers 42a and 42b provided in These shift registers 42a and 42b are also p-stage and are driven by a clock CK having twice the frequency of the clock signal in the modulation device 11.

In the correlator 21, the code of each set stage of the register 41a and the code of the received signal sent to the corresponding stage of the shift register 42a are respectively output to an EX-OR circuit 43.
Compare at a. The output signals of all EX-OR circuits 43a are given to an adder 44a and added. Adder 4
The output signal 4a represents the degree of coincidence between the code of each stage of the register 41a and the code of each corresponding stage of the shift register 42a, and this is the correlation output R of one correlator 21.
．． becomes. Since the received signal RXI is sequentially shifted through the shift register 42a every clock signal CK, the correlation output R. also changes according to each clock signal CK.

Similarly, in the other correlator 22, the register 4l
The EX-OR circuit 43b checks whether the sign of each stage set in b matches the sign of the received signal sent to the corresponding stage of the shift register 42b. The output signals of all EX-OR circuits 43b are sent to the adder 4
4b and is added. The adder 44b outputs a correlation output R indicating the degree of correlation between the Manchester M sequence set in the register 4lb and the input digital received signal RXI.
．． will be output.

FIG. 6 shows a modification of the correlator 21. register 4
1a and shift register 42a, the number of stages is gXk.
(k is a positive integer of 2 or more) register 41A and shift register 42A are provided. shift register 4
2A is a clock signal CK.2A having a frequency k times that of the clock signal CK. driven by. EX-OR circuit 43A
The codes of the corresponding stages of the register 41A and shift register 42A are manually input to each EX-OR circuit 43A.

The adder 44A adds the output signals of all the EX-OR circuits 43A and generates a correlation output R. Bind and output. In this way, by increasing the number of stages of registers and shift registers by m times, the accuracy of correlation calculation is improved.

It goes without saying that the correlator 22 can also be modified in the same way.

Furthermore, in FIG. 6, a shift register 42a shown in FIG. 5 may be provided in place of the shift register 42A. In this case, k lines are extracted from each stage of the shift register 42a and the corresponding EX-OR circuit 43A
Connect to.

FIG. 7 shows yet another embodiment. Here, the shift register 42 to which the received signal RXI is input is the correlator 21.
and 22. By doing so, the number of shift registers can be reduced and the configuration can be simplified. As shown in Figure 6, a shift register with the number of stages multiplied by k is constructed. It goes without saying that the correlators 21 and 22 can be used in the same way.

(4) Demodulator FIG. 8 shows an example of the configuration of the demodulator 23. Further, signal waveforms of each part in FIG. 8 are shown in FIG. 9. In this figure, the correlation output R. , R b are drawn analogously for easier understanding.

A pair of correlators 21. The correlation output R.22 is output from R.22.
The principle of demodulating data based on and R will be explained first. Referring to FIG. 9, the 21 data section T (which is equivalent to one period of the Manchester M series) is divided into a central window portion (referred to as W portion) and portions before and after it (referred to as E portion). The front and rear E portions are set at equal intervals.

However, it is not necessary to set the E sections before and after the W section equally, and the W section does not need to be set at the center of the data section. 0<
Using d that satisfies d<T, the W part is (T-d)/2~
The section E can be expressed as an interval of (T+d)/2, and an interval of 0 to (T-d)/2 and (T1d)/2 to T. The W section is also called the observation section.

When data is being transmitted, within the data interval T, the correlation output R. and R. A correlation peak appears on either side. The synchronization control circuit 25 detects this correlation peak, and creates a data interval end signal ED that defines the end point of the data interval so that the correlation peak is at the center of the data interval T (Creation of data interval end signal ED (will be discussed later). Then, based on this data section end signal ED, a window start pulse WL and a window start pulse WL and a window start pulse WL and a window start pulse WL and a window start pulse WL and
A stop pulse WH is created by the synchronous control circuit 25.

Code P ay r P bw * A I11! lA
The meaning of bw is defined as follows.

P. ．． : Correlation output R. Peak value (maximum value) at W part of P by: Correlation output R. Peak value (maximum value) at W part of A. ．． : Correlation output R. The sum (added value) in the E part of A, E: the sum (added value) of the correlation output R, in the E part The demodulated data (received data RXD) is generated as follows.

If P b v-A a g > P a v AbB, the data is 1, Pl, v-A. l! If P0/AbB, the data is 0.

Theoretically speaking, if P by > P sw, the data is 1
, if the opposite is true, the data may be determined to be O. However, if noise is included, demodulation errors may occur when comparing peak values in correlation outputs. Generally, in a correlation output that has a correlation peak, the levels before and after the peak are smaller than the correlation level of a correlation output that does not have a correlation peak. For example, if the correlation output R has a correlation peak, the sum ABB before and after it is the correlation output R with no correlation peak. The sum of A. smaller than E. Utilizing this property, in order to prevent demodulation errors as much as possible, the product of the peak value and the sum of mutually separate correlation outputs, that is, P. , · AsE and P0 · Abz are compared in magnitude to create demodulated data. As a result,
Stable demodulation is possible even when the transmission characteristics of the transmission path are poor and noise is likely to occur.

Since the circuit shown in FIG. 8 is a digital circuit, the clock signal CK or CK. The clock signal is not shown in the figure to simplify the explanation.

In this circuit, the correlation output R. is latched by the latch circuit 51a for one clock, converted into an absolute value by the absolute value circuit 52a, and further provided to the adder circuit 55a and the maximum value hold circuit 54a. On the other hand, a window ● start pulse WL and a window stop pulse WH are inputted to the window generating circuit 53, and a window signal WS which becomes H level at the W portion is outputted from this circuit 53. This window signal WS is applied to the adder circuit 55m.
In the adder circuit 55a, the latch circuit 48 receives the window signal WS and the latch circuit 4B of the maximum value hold circuit 54a as an operation control signal.
It operates only in the E part where is at L level.

Latch timing is of course defined by the clock signal. The absolute value correlation output R. is input sequentially. is added by the adder 47 to the previous addition result given from the latch circuit 48 for each clock signal. This addition result is latched in the latch circuit 48 again. In this way, the sum A. is output from the adder circuit 55a. I! Data representing is obtained and applied to multiplier 58a.

The latch circuit 46 of the maximum value hold circuit 54g operates only in the W portion where the window signal WS is at H level. The maximum value latched in the latch circuit 46 up to the previous time and the correlation value R manually input this time. The comparator 45 compares the current correlation value with the absolute value of the current correlation value, and if the current correlation value is larger, the current correlation value is latched into the latch circuit 46 as a new maximum value. In this way, the peak value P is output from the maximum value hold circuit 54a.
．． Data representing is obtained and applied to multiplier 56b.

Similarly, for the other correlation output R, a latch circuit 5lb, an absolute value circuit 52b, and a maximum value hold circuit 54b are used.
and an adder circuit 55b. Then, the peak value Pbw is output from the maximum value hold circuit 54b to the adder circuit 5.
Sum 1 from 5b. are obtained respectively, and the multiplier 5[ia,
58b.

In the multiplier 58a, P.・The multiplication of AaE is performed by the multiplier 56b.
Then, the multiplications of p at and AbE are performed, and the multiplication results are given to the comparator 57.

In the comparator 57, P.A. A comparison is made between B and P0/AbB, and a signal representing 1 or O is output depending on the comparison result, which is latched by the latch circuit 58 at the timing of the data interval end signal ED and output as received data RXD. . In response to this data section end signal ED, the adder circuits 55a, 55b, maximum value hold circuit 54a,
54b is reset.

(5) Carrier Detection Circuit FIG. 10 shows an example of the configuration of the carrier detection circuit 24. The carrier detection circuit 24 is a peak position detection circuit 2B.
, peak position determination circuit 27, counting circuit 28 and m
/N determination circuit 29.

The peak position detection circuit 2B is a circuit for detecting at which position within the data interval T the peak of the correlation output is located, and as shown in FIG. 12, the peak position PP is the point at which the maximum value of the correlation output appears. It is measured as the time from to the data section end signal ED.

Figure 3811 shows an example of a peak position detection circuit, in which two correlation outputs R. The position where the absolute value of the sum of and R shows the maximum value is defined as the peak position.

Two correlation outputs R. and Rb are respectively applied to an adder 6l, and after being added, are converted into absolute values by an absolute value circuit 64. This absolute value signal is applied to one input terminal of comparator 62 and latch circuit 63. When the signal ED indicating the end of the previous data section is applied to the latch circuit 63 as a latch timing signal via the OR circuit 65A, the output of the absolute value circuit 64 is latched as an initial value. The value latched in the latch circuit 63 is given as the other input to the comparator 62. So after that. The value latched in the latch circuit 63 and the output value of the absolute value circuit B4 are sequentially compared in the comparator circuit 62 (for each clock pulse of the clock signal CK), and the output value larger than the latched value is When obtained from the absolute value circuit 64,
The output of the comparator 62 passes through the OR circuit 65A to the latch circuit 6.
3, the output of the absolute value circuit 64 is latched into the latch circuit 63 as a new value. In this way, the maximum value is always latched in the latch circuit 63.

On the other hand, the counter 8B that counts the clock signal CK is
Reset (clear) by data section end signal ED input via R circuit 65B or comparison output of comparator 62
and starts counting again from zero. The count output of the counter 6B is latched by the latch circuit 67 when the next data period end signal ED is applied. The counter 66 counts the clock signal CK from the time when the peak value appears in the data interval T until the time when the signal ED indicating the end of the data interval T is applied. This count value is then latched by the latch circuit 67 and represents the peak position PP.

FIG. 13 shows another example of the peak position detection circuit.

Here, two correlation outputs R. , Rb (7) The one with the larger peak value in absolute value is selected, and this selected peak position is output as the final peak position PP. Two correlation outputs R. and R. In order to detect the peak position for each, the absolute value circuit 6 shown in FIG.
4, comparator 62, latch circuit 63, OR circuit 65A,
85B and counter 66 output correlation output R.85B. , Rh. In FIG. 13, the corresponding circuits are shown with the same reference numerals with a or b added.

Adder 61 is not provided.

The count values of counter 66a and counter B6b are provided to selector 69. Further, the maximum values latched in the latch circuits 63a and 63b are provided to the comparator 68 and compared. Selector 69 is controlled by the output of comparator 68. Correlation output R. , R, of the counter 86a or 66b having the larger peak value is selected by the selector 69 and provided to the latch circuit 67. The latch circuit 67 latches the count output of the manually operated counter through the selector 69 as the peak position PP when the data section end signal ED is inputted manually.

FIG. 14 shows yet another example of the peak position detection circuit. The circuit shown in FIG. 14 differs from that shown in FIG. 11 only in that the adder 61 is not provided in FIG. The peak position detection circuit shown in FIG. 14 has a correlation output R. ,R. Only one of them, predetermined, inputs.

The peak position is detected by the synchronous peak position detection circuit,
Until synchronization is established, the above-mentioned CSK modulator 11
At this point, either 1 or O transmission data is sent. That is, the switching circuit 33 is fixed to either side. In the peak position detection circuit shown in Fig. 14. Correlator 21. Out of 22 transmission data (
1 or 0) of the correlator is selected as its input.

Next, a specific example of the configuration of the peak position determination circuit 27 will be described in detail. The peak position determination circuit 27 is a circuit that divides one period (data section) T of the Manchester code M series into a plurality of areas that allow overlap, and determines to which area the detected peak position PP belongs. Many specific examples can be considered depending on the method of dividing multiple areas that allow overlap and the differences in the elements that make up the circuit. The area is the M series (
Refers to one period (data interval) of a PN sequence that is divided into several intervals. The size of the area can be any size that does not exceed one data interval, and the size of each area does not necessarily have to be equal, and the areas may overlap each other.

Figures 15 and 16 show the first example.

Here, as shown in FIG. 15, one data section T is equally divided into j (10) areas aj so that the areas do not overlap each other. The start position and end position of each area are represented by the symbols LS and LE, respectively, with the symbols a-j representing the area added. For example, the starting position of area a is LS. , the end position is LE. It is. FIG. 16 shows a specific example of a peak position determination circuit configured using window converters 71a to 71j. A start position LS and an end position LE of the corresponding area are set in each window converter 71 (numerals 71a to 71j are collectively represented by the reference numeral 71).

Signals representing these positions LS and LE are created based on the data section end signal ED. The peak position PP detected by the peak position detection circuit 26 described above is provided to each window converter 71. Each window comparator 71 is activated when the input peak position PP is between the set start position LS and end position LE.
H level output signal (output signal is also represented by a - j)
Output.

Figures 17 and 18 show a second example.

Here, one data section T is equally divided into j areas (10 areas) so that the areas do not overlap each other, as shown in FIG. 17. FIG. 18 shows a specific configuration of a peak position determination circuit using an AND circuit. Peak position P
P is expressed as a 4-bit binary number and only takes values from 0 to 9. Peak position determination circuit j AND circuits (
A 4-bit digital signal representing the peak position PP is input to each AND circuit 72. Each area a -
Addresses 9 to 0 are assigned to j. As mentioned above, the peak position PP is counted from the data interval end signal ED indicating the end of each data interval T (see Figure 12), so the addresses are such that area j is the start address O and area a is the end address 9. given as. Each AND circuit 72a-72j is configured to output an H-level output signal (a-j) when the input peak position PP matches the address given to the corresponding area.

FIGS. 19 and 20 show a third example.

As shown in FIG. 19, the data section T is divided into j areas such that the area overlaps with the adjacent area by 1/2 of the area length. Let each area be ab, bc, ..., ja. FIG. 20 is composed of j window converters 73 (ab, etc. indicating areas are omitted). Each window converter 73 is set with a start position LS and an end position WLE (ab, etc. indicating the area are omitted) of the corresponding area. When the peak position PP is between these two positions, the corresponding window comparator 73 outputs an H level output signal (ab, bc, etc.).

Figure 21 shows the fourth example. This peak position determination circuit is constructed using an AND circuit and an OR circuit. The method of dividing the data section T is the same as that shown in FIG. The peak position determination circuit is the same AND as shown in Figure 18.
The circuit 72 and . It is composed of j OR circuits 74 each receiving the outputs of two adjacent AND circuits 72 as inputs.

FIGS. 22 and 23 show a fifth example. As shown in FIG. 22, the data section T is divided into j areas such that 1/2 or more of the area length overlaps with the adjacent area. In the illustrated example, each area overlaps the adjacent area by 3/4. Each area is expressed as abed, bcde, etc. As shown in FIG.
ce and the like are omitted). Needless to say, the start position and end position of each window converter 75 are determined according to the corresponding area.

FIG. 24 shows a sixth example, and this peak position determination circuit is constructed using an AND circuit and an OR circuit. The method of dividing the data section T is the same as that shown in FIG. The peak position determination circuit is the same AND as shown in Figure 18.
It consists of a circuit 72 and j OR circuits 76 each receiving the output signals of four adjacent AND circuits 72 as inputs.

FIG. 25 shows a specific example of the configuration of the counting circuit 2B and the m/N determination circuit 29. These circuits generate a synchronization signal (carrier detection signal) when it is determined that the peak position PP belongs to one of the above areas a predetermined number of times (N≧m) or more during a predetermined N consecutive data cycles. ) is output.

For simplicity, the peak position determination circuit 27 shown in FIG. 16 or 18 is used, and its output is expressed as a, b,
Let c, ..., j.

Output signal a l b l of peak position determination circuit 27
' Counters 80a, 80b, 80c, -, 80j for counting the output circuits of 1...,j, respectively
and a counter 84 for counting the number of times the data period T has passed. Counters 8Da to 80j take in an input signal for each data period end signal ED, and if it is at H level, increment the count value by one.

Counters 80a, 80b, 80c, -, 8
The count value of 0j is calculated by a comparator 81a to which a predetermined number m is set,
8lb, 81C, . . . , 81j are compared with a predetermined number m, and when the count value reaches m, an H level signal is output from the comparator. Comparators 81a-8
The output signal of 1j is applied to one input terminal of an AND circuit 89 via an OR circuit 82. The output of the OR circuit 82 is .
When a peak appears m times in any of areas a to j, the level becomes H level. The output signal of OR circuit 82 is represented by PPEN.

On the other hand, the count value of the counter 84 is the data interval end signal ED.
is incremented by 1 for each input. The count value of the counter 84 is compared with a set number N in a comparator 85, and when the count value reaches N, the comparator 85 outputs an N data period end signal NEND at H level. This signal NEND passes through an OR circuit 86 to counters 80a to 80j and 84.
is given and these counters are reset. As a result, the counters 80a to 80j. 84 starts the counting operation from O again.

Also, the N data period end signal NEND is output from the AND circuit 89.
is also applied to the other input terminal of . Therefore, when the N data period end signal NEND is output, if the output of the OR circuit 82 (signal PPEN) is at H level (that is, if the count value of any one of the counters 80a to 80j is m or more) ), the flip-flop 83 is set, and a synchronizing signal (carrier detection signal) (L level) is output. The output of the AND circuit 89 is especially used as a synchronization establishment signal (
TRACK).

When the N data period end signal NEND is output, the count value of any of the counters 80a to 80j is m.
Since the output of the OR circuit 82 is at the L level when the
Input to circuit 8B. The AND circuit 88 has a signal NEND.
Since this is done manually, the flip-flop 83 is reset by the output of the AND circuit 88. AND circuit 88
The output means an out-of-synchronization signal. As described above, the counters 80a to 80j, 84 are reset by the signal NEND, and the carrier detection operation is started again.

FIG. 26 shows another embodiment of the carrier detection circuit. In FIG. 26, the same components as those shown in FIG. 25 are given the same reference numerals. In this embodiment, a switching circuit 94 for switching the predetermined number N given to the comparator 85 to N'
and the predetermined number m given to the comparators 81a to 81j is m'
A switching circuit 95 for switching is provided, and this switching is controlled by a carrier detection signal output from the flip-flop 83. When the carrier detection signal is at H level, N and m are selected as the set numbers and are provided to comparator 85 and comparators 81a to 81j, respectively. When the flip-flop 83 is set (carrier detection) and the carrier detection signal goes to L level, N' and m' are selected. Comparator 85 and comparators 81a to 81, respectively.
given to j. In other words. The carrier detection operation depends on the set numbers N and m, and the carrier disconnection detection operation depends on the set numbers N' and m.
’ respectively. Number of these settings N, N
', m, m' can be set arbitrarily. Preferably, it is set to (m/N)>(m'/N').

(6) Data section end signal generation circuit FIG. 27 shows an example of a data section end signal generation circuit included in the synchronization control circuit 25. This circuit uses the signals PPEN and TRACK output from the carrier detection circuit described above.

The peak position PP detected by the peak position detection circuit 26 is given to the latch circuit 108, and this latch circuit 106 receives the input peak position P for each input of the data section end signal ED.
Latch P. Signal PPEN is applied to latch circuit 10B as an enable signal via NOT circuit 107. Therefore, when the signal PPEN is at L level, the latch circuit 10B performs a latching operation at the peak position PP,
When the signal PPEN goes to H level (that is, when the peak position appears m times in any of the divided areas within the data interval T), the latch circuit 10B holds the last latched peak position PP, and thereafter Do not latch the input peak position. In this way, the peak position that appears m-th time in any area within the data section T is finally latched in the latch circuit 10B.

On the other hand, two registers 102 and 108 are provided. Data representing the peak position PP is given to the register 102 from the latch circuit 10B, and data representing (3/2)T-PP is set in this register 102. T
As mentioned above, is data representing the length (time) of the data section. On the other hand, data T is set in the register 103. The selector 104 receives the synchronization establishment signal TRAC.
Depending on the state of K. When the signal TRACK is at the H level, the setting data of the register 1-02 is applied to one input of the digital comparator 105, and when the signal TRACK is at the L level, the setting data of the register 103 is applied to one input of the digital comparator 105.

On the other hand, the counter 1 counts the clock signal CK and provides the count output to the other input of the digital comparator 105. Comparator 105 generates a data period end signal (match signal) ED when the count value of counter 101 becomes equal to the setting data applied through selector 104. The counter 101 is reset by this signal ED and starts counting again from zero.

Now, since the signal TRACK is at the L level until synchronization is established, the setting data T of the register 103 is applied to the comparator 105 through the selector 104. Therefore, regardless of the peak position of the correlation output, this circuit generates the data interval end signal ED at the period T. When the peak position of the correlation output appears m times in any area within the data interval T, the peak position is detected by the latch circuit 10B.
is finally latched and provided to the register 102.

When N data cycles are completed, the synchronization establishment signal TR
Since ACK becomes H level, the setting data (3/2) T-PP of the register 102 is given to the converter via the selector 104. This setting data (3/2)
T-PP is. This is to generate the next data section end signal ED so that the length (time) from the next peak to the next data section end signal is T/2. In this way, the data section end signal ED is generated such that the peak position is at the center of the data section T. After the synchronization is established, the selector 104 selects the register 103 again, so the data section end signal ED is generated at the cycle T again.

If necessary, a synchronization tracking circuit is further provided to determine the peak position PP.
It may be controlled so that it is always located approximately at the center of the W portion.

Refer to Figure 28. The operation of the data section end signal generation circuit shown in FIG. 27 will be specifically explained. For simplicity, the set number is assumed to be Nm5, m-3.

When the synchronization establishment signal TRACK is at L level, the selector 104 selects the setting data T of the register 103, and the data section end signal ED is generated every cycle T. Each time the data period end signal ED is generated, the latch circuit {06 latches the peak position rIIPP.

Three peak positions PP1, PP2, PP4 (m-
Suppose that the peaks in 3) appear in the same area. Signal P
PEN becomes H level at time T1. This signal PPEN
When signal PPEN becomes H level, the latch circuit 106 does not latch the input peak position and holds the peak position PP4 immediately before signal PPEN becomes H level. When the five (N-5) data interval observations are completed (time T2), the N data period end signal NEND becomes H level. At this time, the signal PP
Since EN is at H level, the synchronization establishment signal TRACK becomes H level. As a result, selector 1ro 4 selects the setting data (3/2) T-PP4 of register 102,
Since it is applied to the comparator 105, the data section end signal ED is output when the time of (3/2)T-PP4 has elapsed (time T3). This establishes synchronization, and henceforth the peak position is corrected so that it is always at the center of the data interval. Since the counters (84.80a to 80j) are reset as described above by the signal NEND, the signals PPEN, NEND, TRAC
K returns to L level.

By removing the AND circuit 89 in FIGS. 25 and 26, if the count value of any one of the counters 80a to 80j reaches m before the end of N data periods, the flip-flop 83 is set. , L level synchronization signals are output. In this case, the output signal PPEN and signal NEND of the OR circuit 82 are applied to the counters 84, 80a to 80j through the OR circuit, and if the signal PPEN is output even before N data periods have elapsed, the counters 80a to 80j, 84 are reset. I'll do what I do. A carrier detection circuit having such a configuration can also be used for the data period end signal generation circuit shown in FIG.

FIG. 29 shows the carrier detection circuit 24 and the synchronization control circuit 2.
5 is shown.

Correlation output R. and R. is given to the beak inspection section 110. The peak inspection unit 110 detects the peak position PP in the same way as the peak detection circuit 26, and also detects the level L.
Detect. The peak from which the position and level are detected may be the peak of either one of the correlation outputs R - or Rh, or the peak of their sum, whichever is larger. Either is fine. Peak position P detected by peak inspection unit 110
P and its level L are given to the storage section 111 and stored in the storage section 11l for each data section end signal ED. The storage unit 111 stores at least the peak position PP and peak level L for the latest N data cycles.

On the other hand, the detected peak position PP is also given to the m/N determining section 113, and this determining section 113 takes in the peak position PP for each data section end signal ED.

Predetermined numbers m and N are set in the m/N determination unit 113. These predetermined numbers m, N are set as m/... according to the synchronization signal (signal indicating presence/absence of carrier detection) as described above. N
You may switch between 7 and 7. m/N determination unit 11
3 determines which area divided into a predetermined number within the data interval each given peak position PP belongs to, and counts the number of peak positions PP belonging to each area over N data periods. and. If there is an area where a predetermined number m or more of peak positions appear in N data cycles, a synchronization signal, a synchronization establishment signal TRACK
occurs. The synchronization establishment signal TRACK is applied to the select terminal of the selector 104 described above. The m/N determination unit 113 also outputs the determination result (data indicating an area where a predetermined number m or more peak positions have appeared), the signal PPEN or TR described above.
data representing ACK, etc.) is given to the calculation unit 112.

When the arithmetic unit 112 is given data indicating that synchronization has been established from the m/N determination unit 113, The weighted average is calculated using the peak position data stored in the storage unit 111, peak level data if necessary, and data indicating areas where m or more peak positions have appeared given by the m/N determination unit 113. The peak position Po is calculated and given to the register 102.

As a result, when synchronization is established, the selector 104 selects the setting data (3/2) T-PO of the register 102 and provides it to the comparator 105, so that the weighted average peak position P is set. The data section end signal ED is generated at a timing when ED comes to the center of the data section.

There are various methods of calculating the weighted average peak position PO. Typical examples of these are as follows.

(Part 1) Among the j areas divided into one data section T, N
Assume that there are r areas in which m or more peak positions appear in the data period. The starting position of those areas is LS. ,LE,.

Weighted average peak position P. is calculated using the following formula.

pom[Σ(LS+ +LE+)] /2 r −
(1) Here, Σ means addition for areas where m or more peak positions appear.

(Part 2) Let j be the number of areas divided within one data section T.

The number of times the peak position appears in each area i (i-1 to j) is expressed as PN. shall be. Let the start position and end position of each area i be LSL E +. Weighted average peak position P. is calculated using the following formula.

Po-=[Σ(LS,+LE+)-PN,]/2
N...(2) Here, Σ means addition for all areas.

M):NrinΣPN. It is.

FIG. 30 illustrates this weighted average peak position calculation method. For simplicity, j-5, that is, 1 data interval T
Assume that the area is divided into five areas a to e. Set the start position and end position of each area to L.
S. -0, LE. -LS. -1, LE. -LS. -2,
LEe-LS, -3, LE, -LS. -4,LE,-5
shall be. Also, the number of times the peak position appears in areas a, b, c, d, and e is 3, 30, and 15, respectively.
3 and 0. The model is N-51. Substituting these data into equation (2.) gives P. -1.
Get 115.

(Part 3) Of the j areas divided within one data section T, N
Assume that there are r areas in which peak positions appear at mm or more in the data period. Let the start position and end position of these areas be LSI and LE-, respectively. Also,
The sum of the peak levels in each of these areas is P
Let it be L+.

The weighted average peak position IPo is calculated using the following formula.

Here, Σ means addition for areas where m or more peak positions appear.

(Part 4) Let j be the number of areas divided within one data section T.

The number of times the peak position appears in each area i (i-1 to j) is expressed as PN. shall be. Let the start position and end position of each area i be Ls, LE + , respectively. Further, the sum of the peak levels of peaks appearing in each area l is assumed to be PL.

The weighted average peak position Po is calculated using the following formula.

...(4) Here, Σ means addition for all areas.

Also, N-ΣPNl.

In the configuration shown in FIG. 29, the peak inspection section I10, the storage section 11l, the calculation section 112, and the m/N determination section 113 can be realized by computer software.

Effects of the Invention According to the first and second inventions, the correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length is at most a first predetermined number of consecutive signals per cycle of the code sequence. Detected over N periods.

It is determined to which area the detected peak position belongs among the plurality of areas divided with overlap allowed within one cycle, and the number of detected peaks belonging to that area is counted for each area. Ru. At most, it is determined whether the detected peak count value in any one area has reached the second predetermined number m during the first predetermined number N cycles, and if it has reached the second predetermined number m, it is considered that synchronization has been established. Then, when synchronization is established, the detected peak count value increases to a second predetermined number m.
A periodic signal representing the period is created and output so that the peak position reached is at the center of the period of the code sequence.

In this way, according to the first and second inventions, correlation peaks are observed over N periods of the code sequence, and when m or more correlation peaks appear in the same area, it is determined that synchronization has been established. When we adopted . Since a periodic signal is created such that the correlation peak position determined to be synchronized is at the center of the period of the code sequence, accurate demodulation can be performed using this periodic signal.

According to the third and fourth inventions, the correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length is detected every cycle of the code sequence.

The detected peak positions are stored over a first predetermined number N periods. For each of the stored peak positions for the first predetermined number of N periods, it is determined to which area they belong among the plurality of areas divided with overlap allowed within the one period, and each of the peak positions is determined. The number of peak positions determined to belong to the area is counted. It is determined whether the peak position count value in at least one area is greater than or equal to a second predetermined number m, and the second predetermined number m is determined.
If this is the case, it is determined that synchronization has been established. On the other hand, a weighted average peak position regarding the stored peak positions is calculated. When it is determined that synchronization has been established, a periodic signal representing the period of the code sequence is generated and output so that the calculated weighted average peak position is at the center of the period of the code sequence.

In this way, according to the third and fourth inventions, correlation peaks are observed over N cycles of the code sequence, and when m or more correlation peaks are detected in the same area, it is determined that synchronization has been established. When adopting the method,
A periodic signal is created such that the weighted average peak position of the peak positions appearing in the observed N periods is located at the center of the period of the code sequence. Since the weighted average peak position represents the average of the peak positions that appear, even if the peak appears at a slightly different position due to sudden noise or changes in the transmission path condition, the above period will not change. It becomes possible to perform accurate demodulation using the signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a CSK communication system. FIG. 2 is a circuit diagram showing an example of the configuration of the modulation device, and FIG. 3 is a time chart showing its operation. FIG. 4 is a circuit diagram showing another example of the modulation device. FIG. 5 is a circuit diagram showing an example of the structure of a pair of correlators, FIG. 6 is a circuit diagram showing a modification thereof, and FIG. 7 is a circuit diagram showing another example of the structure of the correlators. FIG. 8 is a circuit diagram showing an example of the configuration of the demodulator, and FIG. 9 is a waveform diagram showing its operation. FIG. 10 is a block diagram showing the configuration of the carrier detection circuit. Figure 11 is a block diagram showing the configuration of the peak position detection circuit. FIG. 12 is a waveform diagram showing the peak position detection operation. FIG. 13 is a block diagram showing another example of the peak position detection circuit. FIG. 14 is a block diagram showing still another example of the same circuit. FIG. 15 is an explanatory diagram showing how one cycle of the M sequence is divided into multiple areas without overlapping, and FIG. 16 is a circuit showing an example of a peak position determination circuit suitable for the area division in FIG. 15. It is a diagram. Fig. 17 is an explanatory diagram showing how one cycle of the M sequence is divided into multiple areas without overlapping, and Fig. 18 is a circuit diagram showing an example of a peak position determination circuit suitable for the area division of Fig. 17. be. FIG. 19 is an explanatory diagram showing how one cycle of the M sequence is divided into multiple areas so as to overlap by 1/2 with the adjacent area. 20th
This figure is a circuit diagram showing an example of a peak position determination circuit suitable for the area division shown in FIG. 19. FIG. 21 is a circuit diagram showing another example of the peak position determination circuit suitable for the area division shown in FIG. 19. Figure 22 is an explanatory diagram showing how one period of the M sequence is divided into multiple areas so that they overlap with the adjacent area by more than half, and Figure 23 is a diagram of a peak position determination circuit suitable for the area division shown in Figure 22. FIG. 2 is a circuit diagram showing an example. FIG. 24 is a circuit diagram showing another example of the peak position determination circuit suitable for the area division shown in FIG. 22. FIG. 25 is a block diagram showing an example of a counting circuit and an m/N determining circuit, and FIG. 26 is a block diagram showing a modification thereof. FIG. 27 is a block diagram showing an example of a data section end signal generation circuit included in the synchronization control circuit, and FIG. 28 is a waveform diagram showing an example of its operation. FIG. 29 is a block diagram showing another example of a synchronous control circuit including a carrier detection circuit and a data interval end signal generation circuit, and FIG. 30 is a graph showing an example of its operation, particularly an example of weighted average peak position calculation processing. be. Figures 31 and 32 show the conventional SS communication system. FIG. 31 is a circuit diagram showing the configuration, and FIG. 32 is a time chart showing its operation. 24...Carrier detection circuit, 25...Synchronization control circuit, 26...Peak position detection circuit, 27...Peak position determination circuit, 28...Counting circuit, 29...m/N determination circuit , 110...Peak inspection section. 111...Storage unit, 112...Calculation unit, 11B...m/N determination unit.

Claims (12)

[Claims] (1) Detecting a correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length, for each period of the code sequence, for a maximum of a first predetermined number N periods, and detecting the peak position determines which area it belongs to among the plurality of areas divided by allowing overlap within the above one cycle, and counts the number of detected peaks belonging to that area for each area, During a predetermined number of N cycles, it is determined whether the detected peak count value in any one area has reached a second predetermined number m, and if it has, it is determined that synchronization is established, and when synchronization is established. A synchronization establishment method, comprising: creating a periodic signal representing the period of the code sequence so that the peak position at which the detected peak count reaches a second predetermined number m is located at the center of the period of the code sequence. (2) a peak position detection circuit that detects a correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length every cycle of the code sequence; A peak position determination circuit determines which area it belongs to among a plurality of areas divided by allowing overlap; a counting circuit that counts over a number of N cycles; determining whether the detected peak count value in any one area has reached a second predetermined number m during the first predetermined number of N cycles; If the m/N determination circuit has reached a second predetermined number m, the m/N determination circuit outputs a synchronization establishment signal, and the peak position at which the detected peak count value has reached a second predetermined number m is memorized, and the synchronization establishment signal is output from the m/N determination circuit. A synchronization establishment device comprising: a periodic signal generation circuit that generates and outputs a periodic signal representing the period of the code sequence so that the stored peak position is at the center of the period of the code sequence when the signal is output. (3) Detecting a correlation peak position of a correlation signal between the received signal and a code sequence of a predetermined code length for each period of the code sequence, storing the detected peak position over a first predetermined number N periods, and storing it. For each of the peak positions for the first predetermined number of N cycles, it is determined to which area they belong among the plurality of areas divided with overlap allowed within the one cycle, and each area is count the number of peak positions determined to belong to the area, determine whether the peak position count value in at least one area is equal to or greater than a second predetermined number m, If synchronization is determined to be established, the weighted average peak position is calculated for the stored peak position, and when it is determined that synchronization is established, the calculated weighted average peak position is located at the center of the cycle of the code sequence. A synchronization establishment method that creates a periodic signal representing the above period. (4) Synchronization establishment according to claim (3), wherein when there are a plurality of areas in which the peak position count value is equal to or greater than the second predetermined number m, the average position of the center positions of these areas is set as the weighted average peak position. Method. (5) Regarding all areas included within the above one cycle,
The synchronization establishment method according to claim 3, wherein the weighted average peak position is calculated based on the sum of the products of the center position of the area and the number of peak appearances. (6) In addition to the correlation peak position, its peak level is detected and stored, and when there are multiple areas where the peak position count value is greater than or equal to the second predetermined number m, the center position of each area and the Calculate the product of the detected peak level and the total sum,
The synchronization establishment method according to claim 3, wherein a weighted average peak position is calculated using the result of adding this product for the plurality of areas. (7) Detect and store the peak level in addition to the correlation peak position, and calculate the sum of the products of the center position of the area and the sum of the peak levels in that area for all areas included in the above one cycle. The synchronization establishment method according to claim 3, wherein the weighted average peak position is calculated based on. (8) Peak inspection means for detecting a correlation peak position of a correlation signal between a received signal and a code sequence of a predetermined code length every cycle of the code sequence, and storing the detected peak position over a first predetermined number N periods. storage means for determining, for each of the stored peak positions for the first predetermined number of N periods, to which area they belong among the plurality of areas divided by allowing overlap within the one period; and counting the number of peak positions determined to belong to each area, determining whether the peak position count value in at least one of the areas is equal to or greater than a second predetermined number m, and counting the number of peak positions determined to belong to each area. a determining means that determines that synchronization is established if it is several meters or more; a calculating means that calculates a weighted average peak position with respect to the peak position stored in the storage means; and a calculating means that calculates by the calculating means when it is determined that synchronization is established. A synchronization establishment device comprising: a periodic signal generating means for generating and outputting a periodic signal representing the period so that the weighted average peak position of the code sequence is at the center of the period of the code sequence. (9) Claim (8) wherein, when there are a plurality of areas in which the peak position count value is equal to or greater than a second predetermined number m, the calculation means calculates the average position of the center positions of these areas as the weighted average peak position. ) synchronization establishment device described in ). (10) Claim (8) wherein the calculation means calculates the weighted average peak position based on the sum of the products of the center position of the area and the number of peak appearances for all areas included in the one period. ) synchronization establishment device described in ). (11) The peak inspection means detects the peak level in addition to the correlation peak position, and the storage means stores the peak level in relation to the correlation peak position. The calculation means calculates the product of the center position of each area and the total sum of peak levels detected in that area when there are multiple areas in which the peak position count value is equal to or greater than a second predetermined number m; The synchronization establishment device according to claim 8, wherein the weighted average peak position is calculated using the result of adding the products for the plurality of areas. (12) The peak inspection means detects the peak level in addition to the correlation peak position, and the storage means stores the peak level in relation to the correlation peak position; The calculation means calculates a weighted average peak position for all areas included in the one cycle based on the sum of products of the center position of the area and the total sum of peak levels in that area. The synchronization establishment device according to (8).