JP2756010B2 - Synchronization establishment method and apparatus - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method and an apparatus for establishing synchronization in a receiving apparatus for spread spectrum (SS) communication.

[Prior Art] The SS communication method has been widely applied to power line communication in addition to satellite communication and mobile communication. A conventional SS communication system will be described with reference to FIGS. 31 and 32. On the transmitting side, the output a of the PN (pseudo noise) code sequence generator 1 is subjected to an EX-OR operation (signal c) by the EX-OR circuit 2 with the transmission data b, and then transmitted by the amplifier 3 to the transmission path as a transmission signal. On the receiving side, the received signal is amplified by the amplifier 4 and then synchronized by the correlator 6.
Correlate with the output d of the code sequence generator 5. The comparator 7 compares the correlation value (signal e) with a predetermined threshold and demodulates the received data f.

The transmission path may be a wireless, wired, or other transmission medium. Therefore, in many cases, the transmission signal is not only sent directly to the transmission medium, but also converted into a signal suitable for transmitting the transmission medium and sent. Also, power line communication requires an interface that is separated from commercial power. In the following, a connection portion with a transmission medium that performs such signal conversion and separation functions is referred to as a reception interface or a transmission interface.

In the conventional communication system, the PN sequence generated by the synchronous PN code sequence generator 5 on the receiving side must be synchronized with the PN sequence on the communication side. For this purpose, it is necessary to first search for a synchronization point. If there is no problem in the transmission characteristics of the transmission path, a peak is detected in the correlation waveform at the synchronization point. However, on lines where transmission characteristics are extremely poor, such as power line communication, and where there are dip points in the transmission band, the correlation waveform is significantly degraded, and the positive and negative relationships of the correlation values are reversed, causing data demodulation to fail. Error may occur. Further, there was a point that synchronization could not be maintained due to deterioration of the waveform.

The present inventors have proposed a new CSK (Code shift Keying) communication method which overcomes the above-mentioned drawbacks of the conventional SS communication method (Tsumura et al., "High Performance Power Line SS Modem" IEICE (IE).
ICE) Spread Spectrum Technology and Its Application Study Group March 22,19
89 SSTA89-8).

In the CSK communication method, on the transmitting side, two binary PN code sequences having the same code length with a low cross-correlation are respectively generated at a fixed period, and at each of the fixed periods, the two PN code sequences are generated in accordance with 1 or 0 of the transmission data. One of the different PN code sequences is selected and transmitted as a transmission signal. On the receiving side, on the other hand, two correlation outputs are obtained by calculating the correlation between the received signal and the two PN code sequences used on the transmitting side. A correlation peak always appears in one of these two correlation outputs at the above-mentioned fixed period. Therefore, demodulated data of 1 or 0 is created based on a comparison between the peak values of the two correlation outputs.

In such a CSK communication system, two correlation outputs are compared on the receiving side, and 0 or 1 of the received data is assigned according to the magnitude of the peak value. There is no need to strictly synchronize with it. If an absolute value is taken as the output of the correlator, there is an effect that data demodulation errors do not occur even in the case of a transmission line with characteristic deterioration such that the positive and negative of the transmission peak value are reversed.

As described above, a correlation peak appears at any one of the two correlation outputs at the above-mentioned fixed period. On the receiving side, in order to correctly detect the correlation peak, it is necessary to synchronize the operation of the receiving-side device with the received signal so that the correlation peak periodically appears within a certain section. In particular, in a poor transmission path such as a commercial AC power line such as when performing power line communication, the transmission characteristics may fluctuate rapidly and the peak position may fluctuate significantly.

In the above CSK communication method, a correlation peak of a correlation signal between a received signal and a code sequence having a predetermined code length is detected, and a position of the correlation peak in a data section having a cycle corresponding to the code length is detected. Then, it is determined whether or not this peak position is within the observation section set in the data section. Then, when it is determined that the peak position exists in the observation section or when the peak position is continuously determined a plurality of times, it is determined that the carrier is detected, that is, synchronization is established.

As described above, in the CSK communication system proposed earlier by the inventors, it is determined that a carrier is present when a correlation peak of a correlation signal is continuously detected a predetermined number of times within a predetermined observation interval. Is worse, the correlation peak position fluctuates,
In spite of the presence of the carrier, it was found that the carrier detection could not be performed normally because the correlation peak position deviated from the observation section.

[Problems to be Solved by the Invention] Therefore, the present inventors have proposed a carrier detection method and apparatus capable of solving the above-described problems (December, 2001)
Patent application and title of invention by the same applicant and the same agent as the present application filed on March 12, "Carrier detection method and apparatus").

This carrier detection method detects a correlation peak position of a correlation signal between a received signal and a code sequence having a predetermined code length for each cycle of the code sequence, and at most, for a predetermined number N of cycles, and detects the detected peak position. Determines the area to which a plurality of areas divided while allowing overlap in one cycle belong, and counts the number of correlation peaks belonging to the area for each area. During the several N cycles, it is determined whether or not the correlation peak count value in any one area has reached a predetermined number m, and if so, a carrier detection signal is output.

Therefore, if a peak is observed m times in N periods in any of a plurality of areas divided and allowed to overlap within one cycle of the code sequence, it is determined that carrier detection has been performed. However, carrier detection is possible as long as the carrier is continuously located near the position after the change, so that carrier detection can be performed normally regardless of deterioration in transmission path characteristics.

Assuming such a carrier detection method, in order to perform accurate demodulation on the receiving side, it is necessary to generate a signal correctly synchronized with the correlation peak position detected as described above.

In the present invention, N periods are observed, and the peak position is m
It is an object of the present invention to provide a method and an apparatus for generating a periodic signal for demodulation suitable for a method of establishing synchronization when it is in the same area more than once.

[Means for Solving the Problems] In a synchronization establishing method according to a first aspect of the present invention, two PN code sequences having the same code length and having a low cross-correlation, generated at a constant period, are transmitted with a transmission data of 1 or 0 every fixed period. Receiving a signal transmitted from the transmitting side in correspondence with any one of the above, performing a correlation operation on the received signal using the same two PN code sequences used on the transmitting side, and calculating a correlation peak appearing in two correlation outputs. Is detected over a predetermined number N of cycles determined by an integer of 1 or more at the maximum in each cycle of the PN code sequence, and the detected peak positions are duplicated within the one cycle. It is determined which of the plurality of divided areas belongs, and the number of correlation peaks detected for each area is counted. In the area It is determined whether or not the correlation peak count value has reached a predetermined number m defined by an integer of 1 or more and N or less, and if so, synchronization is established. When synchronization is established, the correlation peak count value becomes the predetermined number. It is characterized in that a periodic signal that defines the period is created such that the peak position that has reached m is in the center of the period of the PN code sequence.

According to a second aspect of the present invention, there is provided a synchronization determining apparatus which transmits two PN code sequences having the same code length and having a low cross-correlation generated at a fixed period, in correspondence with one of transmission data 1 or 0 at the fixed period. Receiving the signal transmitted from the transmitting side, performing a correlation operation on the received signal using the same two PN code sequences used on the transmitting side, and calculating the peak position indicating the position of the correlation peak appearing in the two correlation outputs, A peak position detection circuit for detecting a predetermined number of N cycles determined by an integer of 1 or more at the maximum in each cycle of the PN code sequence, and dividing the detected peak positions in the one cycle while allowing overlap; A peak position determining circuit for determining which of the plurality of areas belongs to, and the number of correlation peaks detected for each of the areas is set to the predetermined number N
A counting circuit for counting over a period; and determining whether or not the correlation peak count value in any one area has reached a predetermined number m defined by an integer of 2 or more and N or less during the predetermined number N periods. If the m / N determination circuit outputs a synchronization establishment signal, and the correlation peak count value is the predetermined number m
Is stored, and when the period establishment signal is output from the m / N determination circuit, the period is set so that the stored peak position is at the center of the period of the PN code sequence. And a periodic signal generating circuit for generating and outputting a periodic signal defining the following.

According to a third aspect of the present invention, there is provided the synchronization establishment method, wherein two PN code sequences having the same code length and having a low cross-correlation generated at a fixed period are transmitted in correspondence with either 1 or 0 of the transmission data at the fixed period. Receiving the signal transmitted from the transmitting side, performing a correlation operation on the received signal using the same two PN code sequences used on the transmitting side, and calculating the peak position indicating the position of the correlation peak appearing in the two correlation outputs, The PN code sequence is detected for each cycle, and is stored over a predetermined number N cycles determined by an integer of 1 or more at the maximum, and for each of the stored peak positions for the predetermined number N cycles, Along with determining which area among a plurality of areas divided by allowing overlap in one cycle, the number of correlation peaks detected for each area is counted, and during the predetermined number N cycles, , One of It is determined whether the correlation peak count value in the area has reached a predetermined number m defined by an integer of 1 or more and N or less, and if it has reached, synchronization is established, and the stored peak position is multiplied by a predetermined load. Calculate the load average peak position obtained by arithmetic averaging, and when it is determined that synchronization is established, a period that defines the period such that the calculated load average peak position is located at the center of the period of the code sequence. It is characterized by generating a signal.

A synchronization establishing apparatus according to a fourth aspect of the present invention transmits two PN code sequences having the same code length and having a low cross-correlation generated at a constant period, corresponding to either 1 or 0 of the transmission data at the constant period. Receiving the signal transmitted from the transmitting side, performing a correlation operation on the received signal using the same two PN code sequences used on the transmitting side, and calculating the peak position indicating the position of the correlation peak appearing in the two correlation outputs, Peak inspection means for detecting every one cycle of the PN code sequence, storage means for storing the detected peak positions over a predetermined number N cycles defined by an integer of 1 or more at most, and the stored predetermined number of peaks For each of the peak positions for N cycles, it is determined which of the plurality of areas divided in the one cycle is allowed to overlap, and the correlation detected for each area is determined. Counting the number of over-click, the during a predetermined number N cycles, a predetermined number of correlation peak count is determined with an integer 1 or more N in any one area m
It is determined whether or not the synchronization has been established. If the determination has been made, it is determined that synchronization has been established, the calculation means for calculating the load average peak position related to the peak position stored in the storage means, and the synchronization has been determined to be established. And a periodic signal generating means for generating and outputting a periodic signal defining the cycle such that the load average peak position calculated by the arithmetic means is located at the center of the cycle of the PN code sequence. It is characterized by the following.

According to the first and second aspects of the invention, correlation peaks are observed over N periods of the PN code sequence, and when m or more correlation peaks appear in the same area, synchronization establishment is determined, and synchronization is determined. The correlation peak position determined to be established is
A periodic signal can be created so as to be at the center of the period of the PN code sequence. According to the third and fourth aspects of the present invention, the correlation peak is observed over N periods of the PN code sequence, and when m or more correlation peaks are detected in the same area, it is determined that synchronization is established. N
The load average peak at the peak position that appeared in the cycle is PN
A periodic signal can be created so as to be at the center of the cycle of the code sequence.

Embodiment (1) Overall Configuration of CSK Communication System FIG. 1 shows the overall configuration of a CSK communication system using a Manchester code M sequence.

On the sending side. The modulation device (transmission device) 11 is provided with two Manchester M-sequence generators 31 and 32 for synchronizing and generating Manchester M-sequences having a low cross-correlation and the same code length, respectively. It is provided to the switching circuit 33. The switching circuit 33 is controlled according to the binary transmission data (1 or 0). For example, when the transmission data is 0, the code output of the generator 31 is selected, and when the transmission data is 1, the code output of the generator 32 is selected. This switching circuit
The code output signal selected by 33 becomes the transmission signal TXO. The switching control in the switching circuit 33 is performed in synchronization with the cycle of the generated Manchester code M series, and one binary data (1 or 0) is converted into one cycle of the Manchester code M.
Expressed by a sequence.

Switching or selection of two different Manchester code M sequences is performed according to the code (1 or 0) of data to be transmitted.
Called keying (CSK). Of course, the CSK is not limited to the Manchester M sequence, and other PN code sequences may be used.

The transmission signal TXO is transmitted to a transmission path or a transmission medium via the transmission interface 12A. Transmission interface 12A
Is a connection part in a broad sense, as shown in the section of "Prior Art", and is a part for performing modulation of a carrier or mixing to a power line.

The reception interface 12B also performs demodulation of a carrier, separation from a power line, A / D conversion, and the like, and converts a signal input from a transmission path or a transmission medium into a digital reception signal RXI and outputs the signal.

The receiving device on the receiving side includes two correlators 21 and 22, a demodulation device 23, a carrier detection circuit 24, a synchronization control circuit 25, and the like. The digital reception signal RXI output from the reception interface 12B branches into two, and is correlated with the correlators 21 and 22 respectively.
To enter. One correlator 21 has one Manchester M
A Manchester code M sequence generated from the sequence generator 31 is set, and the set sequence is correlated with the received signal RXI. Similarly, the other correlator 22 has a Manchester code M generated from the other Manchester M-sequence generator 32.
A sequence is set, and the set sequence is correlated with the received signal RXI. Correlation outputs obtained from these correlators 21 and 22 are provided to a demodulation device 23, where a demodulation signal 1 or 0 is assigned according to the correlation value.
Output as receive data RXD. That is, the correlator 21
When the correlator 21 shows a thicker correlation peak value among the correlation outputs of and 22, the received data of 0 is conversely
If 22 indicates a larger correlation peak value, one piece of received data is generated.

The correlation output is also input to a carrier detection circuit 24 and a synchronization control circuit 25. The carrier detection circuit 24 detects the presence or absence of a carrier based on the correlation output, and supplies the detection signal to the synchronization control circuit 25. The presence or absence of the carrier is used to determine whether or not the received signal RXI is being received. When the carrier is detected, the synchronization control circuit 25 creates a timing signal (including a data section end signal ED described later) for demodulation and carrier detection based on the correlation output, and This is given to the detection circuit 24.

As described above, in the CSK communication method, the two correlation outputs are compared on the receiving side, and the 0 of the received data is determined according to the magnitude.
Alternatively, since 1 is assigned, the Manchester M sequence on the receiving side does not need to be strictly synchronized with that on the transmitting side. If an absolute value is taken as the output of the correlator, a demodulation error does not occur even in the case of a transmission line whose characteristics are deteriorated such that the positive and negative of the transmission peak value are reversed. Further, by using the Manchester code M-sequence, it is possible to reduce the reduction component of the received signal and suppress the coupling loss with the transmission line.

(2) Configuration Example of CSK Modulator FIG. 2 shows a specific configuration example of the CSK modulator 11. FIG. 3 shows the output signal waveform of each part of this circuit.

In this embodiment, each Manchester M-sequence generator 31, 32
Are three-stage (n = 3) shift registers FF _{11 to} FF ₁₃ and FF _{21 to} F
Comprises F _23, the shift registers are clock generator 3
Data shift operation is performed at the timing of the clock signal CK output from 4. The feedback circuits of these shift registers are different from each other. That is, shift register FF
_{In 11 to} FF ₁₃ , the signs of the cells in the second and third stages are fed back to their input sides via an exclusive-OR circuit (EX-OR) 31a, whereas the shift registers FF _{21 to} FF _{At 23} , the signs of the cells in the first and third stages are fed back via the EX-OR circuit 32a. The shift register and its feedback circuit are an M-sequence generator (PN
A code generator and a PN code = Pseude Noise Code = pseudo noise code) are each configured. The EX-OR circuits 37 and 38 detect the exclusive OR of the code outputs PN1 and PN2 of the last stage of each shift register and the clock signal CK, respectively, to create a Manchester code.

A phase synchronization circuit is provided so that the other Manchester M-sequence generator 32 always has a constant phase (initial phase) when one Manchester M-sequence generator 31 has a specific phase (all 1s). This phase synchronization circuit includes a NAND circuit 36 and an initial phase setting unit 35. Initial phase setting device 35 is for setting an initial code in each stage of the shift register FF ₂₁ ~FF _23, can be set arbitrary code (all non-zero code). When the sign of all the stages of the shift register FF ₁₁ to ff ₁₃ becomes 1 (this state is caused once a period T of the Manchester code M series) L-level signal from the NAND circuit 36 is generated The sign set in the initial phase setting unit 35 at the time of the next rising of the clock signal CK is the shift register.
To each stage of the FF ₂₁ ~FF ₂₃ is loaded.

As described above, the outputs of the Manchester M-sequence generators 31 and 32, that is, the outputs of the EX-OR circuits 37 and 38, are provided to the switching circuit 33, and are transmitted by the transmission data TXD for each cycle (data section) T of the Manchester code M-sequence. A switching operation is performed.
The output of the NAND circuit 36 is provided to a transmission data processing unit (for example, a microprocessor) as a transmission request signal.
The transmission data processing section outputs one bit (1 or 0) of the transmission data TXD every time this transmission request signal is input, and gives it to the switching circuit 33.

FIG. 4 shows a modification. Compared to Fig. 2,
EX-OR circuit from Manchester M-sequence generators 31 and 32 respectively
37 and 38 are removed, and the output of the switching circuit 33 and the clock signal CK are input to the output side of the switching circuit 33 instead.
An EX-OR circuit 39 is provided to create a Manchester code. Reference numerals 31A and 32A indicate M-sequence generators, respectively.
These outputs (signs of the last stage of the shift register) are given to the switching circuit 33, respectively. This variant is
This has the advantage that the number of EX-OR circuits can be reduced by one.

The output side of the switching circuit 33 in FIG. 2 and the EX-OR in FIG.
It is preferable to provide a one-clock latch circuit on the output side of the circuit 39 so as to shape the waveform of the transmission signal TXO.

(3) Configuration Example of Correlator Next, the configuration of the correlators 21 and 22 will be described in detail with reference to FIG.

The correlators 21 and 22 are respectively provided with l-stage registers 41a and 41b. These registers 41a and 41b store in advance the Manchester code M sequences generated by the Manchester M sequence generators 31 and 32 included in the modulator 11, respectively. Is set. The code length of the M sequence generated using the n-stage shift register is 2 ⁿ -1 bits. In the modulation device 11, since the M-sequence is Manchester encoded, the registers 41a and 41b
Is 1 = 2 (2 ⁿ -1).

On the other hand, the digital reception signal RXI input from the reception interface 12B is branched into two and input to the shift registers 42a and 42b provided in the correlators 21 and 22, respectively. These shift registers 42a and 42b also have one stage, and are driven by a clock CK having a frequency twice the frequency of the clock signal in the modulation device 11.

In the correlator 21, the EX-OR circuit 43a compares the sign of each stage set in the register 41a with the sign of the received signal sent to the corresponding stage of the shift register 42a. The output signals of all the EX-OR circuits 43a are provided to an adder 44a and added. The output signal of adder 44a is
1a represents the degree of coincidence between the code of each stage corresponding code and the shift register 42a of each stage, this becomes the correlation output R _a of one of the correlator 21. Since the reception signal RXI is sequentially shifted in the shift register 42a for each clock signal CK, the correlation output _Ra also changes for each clock signal CK.

Similarly, in the other correlator 22, the register 41b
The EX-OR circuit 43b checks whether or not the sign of each stage set in the register and the sign of the received signal sent to the corresponding stage of the shift register 42b match. All EX
The output signal of the -OR circuit 43b is provided to the adder 44b and added. The adder 44b outputs _a correlation output Ra indicating the degree of correlation between the Manchester M sequence set in the register 41b and the input digital received signal RXI.

FIG. 6 shows a modification of the correlator 21. Register 41
Instead of a and the shift register 42a, a register 41A and a shift register 42A having l × k (k is a positive integer of 2 or more) are provided. Shift register 42A is driven by the clock signal CK _k of k times the frequency of the clock signal CK. 1 × k EX-OR circuits 43A are also provided, and the sign of the corresponding stage of the register 41A and the shift register 42A is indicated by each EX-O circuit.
Input to R circuit 43A. Adder 44A is connected to all EX-OR circuits 43
By adding the output signal of the A and outputs a response signal R _a. As described above, the accuracy of the correlation operation is increased by increasing the number of stages of the register and the shift register by m times. It goes without saying that the correlator 22 can be similarly modified.

Further, in FIG. 6, a shift register 42a shown in FIG. 5 may be provided instead of the shift register 42A. In this case, k from each stage of the shift register 42a
Pull out these lines and connect them to the corresponding EX-OR circuit 43A.

FIG. 7 shows still another embodiment. Here, the shift register 42 to which the received signal RXI is input is correlated with the correlators 21 and 22.
And is also used in. By doing so, the number of shift registers can be reduced and the configuration can be simplified. It goes without saying that the shift register whose number of stages is k times as shown in FIG. 6 can be shared by the correlators 21 and 22 in the same manner.

(4) Demodulator FIG. 8 shows a configuration example of the demodulator 28. FIG. 9 shows the signal waveform of each part in FIG. In this figure, the correlation outputs R _a and R _b are drawn in analog form for easier understanding.

Correlation outputs R _a and R _b output from a pair of correlators 21 and 22
First, the principle of demodulating data based on the above will be described. Referring to FIG. 9, one data section T (which is equal to one cycle of the Manchester M series) is divided into a central window portion (referred to as W portion) and portions before and after the central window portion (referred to as E portion).
And divided into The last part E is set at equal intervals. However, it is not necessary to set the E section before and after the W section equally, and the W section need not be set at the center of the data section.
Here, d that satisfies 0 <d <T is used, the W section is a section of (T−d) / 2 to (T + D) / 2, and the E section is 0 to (T−d) / 2 and (T + d). ) / 2 to T interval. The W section is also called an observation section.

If data is being transmitted, data section T
, A correlation peak appears in one of the correlation outputs _Ra and _Rb . In the synchronization control circuit 25, the correlation peak is detected, and a data section end signal ED defining the end point of the data section is created so that the correlation peak is located at the center of the data section T (creation of the data section end signal ED). Will be described later). Then, based on the data section end signal ED, the window control pulse 25 and the window start pulse WL and the window stop pulse WH respectively defining the start point and the end point of the W section are generated.

Determining code _{P aW, P bW, A aE} , the meaning of A _bE as follows.

P _aW: peak value in W part of the correlation output R _a (maximum value) P _bW: peak value in W part of the correlation output R _b (maximum value) A _aE: sum (addition value) of the E part of the correlation output R _a A _bE : Sum (addition value) of the correlation output _{Rb in} the E section Demodulated data (received data RXD) is generated as follows.

_{P bW · A aE> P aW} · A bE data is _{1, P bW · A aE <} P aW · A bE if data is 0.

Theoretically, if P _bW > P _aW , the data may be determined to be 1, and vice versa. However,
Considering the case where noise is included, a demodulation error may occur in the comparison of peak values in the correlation output.
In general, in a correlation output having a correlation peak, the level before and after the peak is smaller than the correlation level of a correlation output having no correlation peak. For example, if there is a correlation peak in the correlation output R _b, the sum A _bE before and after is less than the sum A _aE of no correlation peak correlation output R _a. Utilizing this property, the product of the peak value and the sum of the correlation outputs that are separate from each other, that is, P _bW ·
_That is, the demodulation data is created by comparing the magnitudes of A _aE and P _aW · A _bE . This enables stable demodulation even when the transmission characteristics of the transmission path or the like are poor and noise or the like is likely to occur.

Although the circuit shown in FIG. 8 operates in synchronization with a clock signal CK or CK _m from a digital circuit, shown in the clock signal for simplicity of explanation are omitted.

In this circuit, the correlation output _Ra is 1 at the latch circuit 51a.
After being latched for the clock, the absolute value circuit 52a converts the value into an insulation value.
Given to 4a. On the other hand, the window generating circuit 53 has a window start pulse WL and a window stop pulse.
The pulse WH is input, and from the circuit 58, the H
The window signal WS which becomes the level is output. The window signal WS is supplied as an operation control signal to the latch circuit 48 of the adder circuit 55a and the latch circuit 46 of the maximum value hold circuit 54a.

In the addition circuit 55a, the latch circuit 48 operates only in the E section where the window signal WS is at the L level.

Latch timing is, of course, defined by the clock signal. Absolute value correlation output R _a sequentially input
Is added by the adder 47 to the previous addition result given from the latch circuit 48 for each clock signal, and the addition result is latched by the latch circuit 48 again. In this way, the addition circuit
Data representing the sum A _aE is obtained from 55a.
Given to.

The latch circuit 46 of the maximum value hold circuit 54a operates only in the W section where the window signal WS is at the H level. Latch circuit 46
Maximum value up to the previous latched in and the current absolute value of the input correlation value R _a and are compared by the comparator 45, the maximum value correlation value of the current is new if the larger of the current correlation value Is latched by the latch circuit 46. In this way,
Data representing the peak value _PaW is obtained from the maximum value hold circuit 54a, and _supplied to the multiplier 56b.

Similarly, for the other correlation output _Rb , a latch circuit 51b, an absolute value circuit 52b, a maximum value hold circuit 54b, and an addition circuit 55b are provided. The peak value P _bW from the maximum value hold circuit 54b is obtained from the sum A _bE from the adder circuit 55b.
Are obtained and supplied to multipliers 56a and 56b.

The multiplier 56a performs multiplication of P _bW · A _aE , and the multiplier 56b performs multiplication of Pa
The multiplication of W · _AbE is performed, and the result of the multiplication is given to the comparator 57.

Magnitude comparison of the comparator 57 P _bW · A _aE and P _aW · A _bE is performed. A signal representing 1 or 0 is output according to the comparison result, latched by the latch circuit 58 at the timing of the data section end signal ED, and output as received data RXD. This data section end signal ED causes the addition circuits 55a, 55
b, the maximum value hold circuits 54a and 54b are reset.

(5) Carrier detection circuit FIG. 10 shows a configuration example of the carrier detection circuit 24. The carrier detection circuit 24 includes a peak position detection circuit 26, a peak position determination circuit 27, a counting circuit 28, and an m / N determination circuit 29.

The peak position detection circuit 26 is a circuit for detecting the position of the peak of the correlation output in the data section T. As shown in FIG. 12, the peak position PP is determined when the maximum value of the correlation output appears. Is measured as the time from to the data section end signal ED.

FIG. 11 shows an example of a peak position detecting circuit. Here, the position where the absolute value of the sum of the two correlation outputs _Ra and _Rb has the maximum value is the peak position.

The two correlation outputs R _a and R _b are respectively supplied to an adder 61, where they are added and then converted into absolute values by an insulation value circuit 64. This absolute value signal is applied to one input terminal of comparator 62 and latch circuit 63. Signal indicating the end of the previous data section
When ED is supplied to the latch circuit 63 as a latch timing signal via the OR circuit 65A, the output of the absolute value circuit 64 is latched as an initial value. The value latched by the latch circuit 63 is provided as the other input of the comparator 62. Therefore, thereafter, the value latched by the latch circuit 63 and the output value of the absolute value circuit 64 are sequentially compared by the comparison circuit 62 (for each clock pulse of the clock signal CK), and are compared with the latched values. When a large value output is obtained from the absolute value circuit 64, the output of the comparator 62 is given to the latch circuit 63 via the OR circuit 65A, so that the output of the absolute value circuit 64 is sent to the latch circuit 63 as a new value. Latched. Thus, the maximum value is always latched in the latch circuit 63.

On the other hand, the counter 86 that counts the clock signal CK is reset (cleared) by the data section end signal ED input through the OR circuit 65B or the comparison output of the comparator 62, and starts counting from zero again. The count output of the counter 66 is latched by the latch circuit 67 when the next data section end signal ED is given. The counter 66 counts the clock signal CK from the time when the peak value appears in the data section T to the time when the signal ED indicating the end of the data section T is given. Then, this count value is latched by the latch circuit 67 and represents the peak position PP.

FIG. 13 shows another example of the peak position detection circuit.
Here, the larger peak value of the absolute values of the two correlation outputs R _a and R _b is selected, and the selected peak position is output as the final peak position PP. In order to detect the peak position of each of the two correlation outputs _Ra and _Rb , the absolute value circuit 64, the comparator 62, the latch circuit 63, the OR circuits 65A and 65B, and the counter 66 shown in FIG. _a and _Rb . In FIG. 13, the circuits corresponding to these have the same reference numerals with a or b added. The adder 61 is not provided.

The count value of the counter 66a and the counter 66b is
Given to. The maximum values latched by the latch circuits 63a and 63b are given to the comparator 68 and compared. The selector 69 is controlled by the output of the comparator 68, and the counter 66a having the larger peak value among the correlation outputs R _a and R _b.
Or the counting output of 66b is selected by the selector 69,
This is provided to a latch circuit 67. The latch circuit 67 latches the count output of the counter whose position is input through the selector 69 as the peak position PP when the data section end signal ED is input.

FIG. 14 shows still another example of the peak position detection circuit. The circuit shown in FIG. 14 differs from the circuit shown in FIG. 11 only in that the adder 61 is not provided in FIG. Only a predetermined one of the correlation outputs R _a and R _b is input to the peak position detection circuit shown in FIG.

Until the peak position is detected by the synchronous peak position detection circuit and synchronization is established, the above-described CSK modulator 11
, One of the transmission data, 1 or 0, is transmitted. That is, the switching circuit 33 is fixed to one side. In the peak position detection circuit shown in FIG. 14, the correlation output ( _Ra or _Rb ) of the correlator corresponding to the transmission data (1 or 0) among the correlators 21 and 22 is selected as the input. You.

Next, a specific configuration example of the peak position determination circuit 27 will be described in detail. The peak position determination circuit 27 uses the Manchester code M
A circuit that divides one cycle (data section) T of a sequence into a plurality of areas where duplication is permitted and determines to which area the detected peak position PP belongs. Many specific examples are conceivable depending on the method and the difference of the elements constituting the circuit. The area refers to one period (data section) of the M sequence (PN sequence) divided into several sections. The size of the area can be any size not exceeding one data section, and the size of each area does not necessarily have to be equal, and the areas may overlap each other.

FIG. 15 and FIG. 18 show a first example. Here, as shown in FIG. 15, one (1) data section T is divided into j (10) areas a to a so that the areas do not overlap each other.
j. The start position and end position of each area are represented by adding codes a to j representing the area to codes LS and LE, respectively. For example, the start position of area a is LS
_a , the end position is LE _a . FIG. 16 shows a specific example of a peak position determination circuit formed by using window comparators 71a to 71j. Each window comparator
A start position LS and an end position LE of a corresponding area are set at 71 (the reference numerals 71a to 71j are collectively represented by reference numeral 71). Signals representing these positions LS and LE are created based on the data section end signal ED. The peak position PP detected by the above-described peak position detection circuit 26 is given to each window comparator 71. Each window comparator 71 outputs an H-level output signal (output signals are also represented by a to j) when the input peak position PP is between the set start position LS and end position LE.

FIG. 17 and FIG. 18 show a second example. Here, as shown in FIG. 17, one data section T is equally divided into J pieces (ten pieces) so that the areas do not overlap each other. FIG. 18 shows a specific configuration of a peak position determination circuit using an AND circuit. Peak position PP is 4 bits 2
It is represented by a base number and takes only values from 0 to 9.
The peak position determination circuit is composed of J AND circuits (general reference numerals 72a to 72j are represented by reference numeral 72), and a 4-bit digital signal representing the peak position PP is input to each AND circuit 72. Addresses 9 to 0 are assigned to the areas a to j. As described above, the peak position PP is counted from the data section end signal ED indicating the end of each data section T (12th
Address), the area j is the start address 0
And given as area a and end address 9. Each of the AND circuits 72a to 72j is configured to output an H-level output signal (a to j) when the input peak position PP matches the address given to the corresponding area.

FIG. 19 and FIG. 20 show a third example. No.
As shown in FIG. 19, the data section T is divided into j areas such that the data section T overlaps an adjacent area by half the area length.
Each area is ab, bc, ..., ja. FIG. 20 shows j window comparators 73 (ab and the like indicating the area are omitted).
It is composed of Each window comparator 73 has a start position LS and an end position LE of the corresponding area.
(Ab, etc. indicating the area) is set, and when the peak position PP is between these two positions, the H-level output signal (ab, bc) is output from the corresponding window comparator 78.
Etc.) are output.

FIG. 21 shows a fourth example.
It is configured using an AND circuit and an OR circuit. The method of dividing the data section T is the same as that shown in FIG. The peak position determination circuit has the same AND circuit 72 as that shown in FIG. 18,
It is composed of j OR circuits 74 each having the output of two adjacent AND circuits 72 as inputs.

FIG. 22 and FIG. 23 show a fifth example. As shown in FIG. 22, the data section T is a half of the adjacent area and the area length.
It is divided into j areas so that the above overlaps. In the illustrated example, each area overlaps with the adjacent area by 3/4.
Each area is represented by abcd, bcde, etc. The peak position judging circuit has j window comparators as shown in FIG.
75 (symbols such as ad, ce, etc., which indicate the area are omitted)
Can be configured by Needless to say, the start position and the end position of each window comparator 75 are determined according to the corresponding area.

FIG. 24 shows a sixth example.
It is configured using an AND circuit and an OR circuit. The method of dividing the data section T is the same as that shown in FIG. The peak position determination circuit has the same AND circuit 72 as that shown in FIG. 18,
It is composed of j OR circuits 76 each having output signals of four adjacent AND circuits 72 as inputs.

FIG. 25 shows a specific configuration example of the counting circuit 28 and the m / N determination circuit 29. These circuits perform a synchronization signal (carrier detection signal) when it is determined that the peak position PP belongs to any of the above areas a predetermined number of m times (N ≧ m) or more during a predetermined predetermined N data periods. ) Is output. For simplicity, the one shown in FIG. 16 or FIG. 18 is used for the peak position determination circuit 27, and its output is a, b, c,
…, J.

Counters 80a, 80b, 80c,..., 8 for counting the output circuits of the output signals a, b, c,.
0j and a counter 84 for counting the number of elapsed data periods T are provided. The counters 80a to 80j take in the input signal for each data section end signal ED, and if it is at the H level, increment the count value by one. Counter 80a,
The count values of 80b, 80c,..., 80j are respectively compared with the predetermined number m in comparators 81a, 81b, 81c,. The H level signal is output from the device. The output signals of the comparators 81a to 81j are OR
The signal is supplied to one input terminal of an AND circuit 89 via a circuit 82. The output of the OR circuit 82 goes high when a peak appears m times in any of the areas a to j. OR circuit
The output signal of 82 is represented by PPEN.

On the other hand, the count value of the counter 84 is incremented by one every time the data section end signal ED is input. The count value of the counter 84 is compared with a set number N in a comparator 85, and the count value is set to N
, The comparator 85 outputs an H-level N data cycle end signal NEND. This signal NEND is supplied to counters 80a to 80j and 84 via OR circuit 86, and these counters are reset. Thereby, the counters 80a to 80j, 84
Starts counting operation from 0 again.

The N data cycle end signal NEND is also supplied to the other input terminal of the AND circuit 89. Therefore, if the output of the OR circuit 82 (signal PPEN) is at the H level at the time when the N data cycle end signal NEND is output (that is, the counters 80a to 80a).
If any of 0j is equal to or more than m), flip-flop 83 is set and a synchronization signal (carrier detection signal) (L level) is output. The output of the AND circuit 89 is particularly called a synchronization establishment signal (TRACK).

If the count value of any of the counters 80a to 80j has not reached m when the N data cycle end signal NEND is output, the output of the OR circuit 82 is at L level.
This is inverted by the NOT circuit 87 and input to the AND circuit 88. AN
Since the signal NEND is input to the D circuit 88, the flip-flop 83 is reset by the output of the AND circuit 88. AN
The output of the D circuit 88 indicates an out-of-sync signal. As described above, the counters 80a to 80j and 84 are reset by the signal NEND, and the carrier detection operation is started again.

FIG. 26 shows another embodiment of the carrier detection circuit. 26, the same components as those shown in FIG. 25 are denoted by the same reference numerals. In this embodiment, a switching circuit 94 for switching a predetermined number N given to the comparator 85 to N 'and a switching circuit 95 for switching a predetermined number m given to the comparators 81a to 81j to m' are provided. This switching is controlled by a carrier detection signal output from the flip-flop 83. When the carrier detection signal is at the H level, N and m are selected as set numbers, which are provided to the comparator 85 and the comparators 81a to 81j, respectively. When the flip-flop 83 is set (carrier detection) and the carrier detection signal goes to L level, N 'and m' are selected and applied to the comparator 85 and the comparators 81a to 81j, respectively. That is, the carrier detection operation is performed by the set numbers N and m, and the carrier disconnection detection operation is performed by the set numbers N 'and m'. These set numbers N, N ', m, m' can be set arbitrarily, but are preferably set to (m / N)> (m '/ N').

(6) Data section end signal generation circuit FIG. 27 shows an example of a data section end signal generation circuit included in the synchronization control circuit 25. In this circuit, the signals PPEN and TRAC output from the carrier detection circuit
K is used.

The peak position PP detected by the peak position detection circuit 28 is supplied to a latch circuit 106, and the latch circuit 106 latches the input peak position PP every time the data section end signal ED is input. The signal PPEN is supplied to the latch circuit 106 as an enable signal via the NOT circuit 107. Therefore, when signal PPEN is at L level, latch circuit 106 performs a latch operation at peak position PP. When the signal PPEN becomes H level (that is, when the peak position appears m times in any of the divided areas in the data section T), the latch circuit 106 holds the last latched peak position PP as it is, and thereafter, Do not latch the input peak position. In this way,
The latch circuit 106 finally latches the m-th peak position in any area in the data section T.

On the other hand, two registers 102 and 103 are provided. Data representing the peak position PP is supplied to the register 102 from the latch circuit 106, and (3/2) T-PP
Is set. As described above, T is data representing the length (time) of the data section. on the other hand,
Data T is set in the register 108. Selector 1
04 indicates that the signal TRACK is H according to the state of the synchronization establishment signal TRACK.
When the level is at the level, the setting data of the register 102 is supplied to one input of the digital comparator 105 when the level is at the L level.

On the other hand, the counter 111 counts the clock signal CK and provides its count output to the other input of the digital comparator 105. The comparator 105 generates a data section end signal (coincidence signal) E when the count value of the counter 101 becomes equal to the setting data provided through the selector 104. Counter 10
1 is reset by this signal ED and starts counting from zero again.

Since the signal TRACK is at the L level until the synchronization is determined, the setting data T in the register 103 is
Through to the comparator 105. Therefore,
Regardless of the peak position of the correlation output, this circuit generates a data section end signal ED at period T. When the peak position of the correlation output appears m times in any area in the data section T, the peak position is finally latched by the latch circuit 106 and given to the register 102. Then, when the N data period ends, the synchronization establishment signal TRACK becomes H level, so the setting data (3/2) T-PP of the register 102 is supplied to the comparator through the selector 104. This setting data (3/2) T-PP is used to generate the next data section end signal ED so that the length (time) from the next peak to the next data section end signal becomes T / 2. Things.
Thus, the data section end signal ED is generated such that the peak position is located at the center of the data section T. After the synchronization is established, the select 104 selects the register 103 again, so that the data section end signal ED is generated again in the cycle T.

If necessary, add a cycle tracking circuit and set the peak position PP
May always be controlled to be substantially at the center of the W portion.

The operation of the data section end signal generation circuit shown in FIG. 27 will be specifically described with reference to FIG. For the sake of simplicity, the set numbers are N = 5 and m = 3.

When the synchronization establishment signal TRACK is at L level, the selector 104
Selects the set data T of the register 103, and the data section end signal ED is generated every period T. Each time the data section end signal ED is generated, the latch circuit 108 latches the peak position PP. Assuming that three (m = 3) peaks at the peak positions PP ₁ , PP ₂ , PP ₃ appear in the same area, the signal PPEN becomes H level at the time T ₁ . Latch circuit 106 when this signal PPEN becomes H level will not latch the input peak position, signal PPEN holds the peak position PP ₄ as just before the H level. When the observation of five data sections (N = 5) is completed (time T ₂ ), the N data cycle end signal NEND becomes H level. At this time, since the signal PPEN is at the H level, the synchronization establishment signal TRACK goes to the H level. By this select 1
04 selects the setting data (3/2) T-PP ₄ of the register 102 and supplies it to the comparator 105, so that the data section end signal ED is output when the time of (3/2) T-PP ₄ has elapsed. (Time T ₃ ). As a result, a cycle is established, and thereafter, the peak position is corrected so as to be always at the center of the data section. Since the counters (84, 80a to 80j) are reset by the signal NEND as described above, the signal PPE
N, NEND, and TRACK return to the L level.

By removing the AND circuit 89 in FIGS. 25 and 28, the counter 80a
When the count value of any one of .about.80j reaches m, the flip-flop 83 is set and an L-level synchronization signal is output. In this case, the output signal of the OR circuit 82
PPEN and signal NEND are passed through OR circuit to counters 84 and 80a to 80
j, the counters 80a to 80j, 84 are reset if the signal PPEN is output even before the lapse of N data periods. The carrier detection circuit having such a configuration can also be used for the data section end signal generation circuit shown in FIG.

FIG. 29 shows another embodiment of the carrier detection circuit 24 and the synchronization control circuit 25.

The correlation outputs _Ra and _Rb are provided to the peak inspection unit 110. The peak inspection section 110 detects the peak position PP and the level L thereof in the same manner as the peak detection circuit 26. The peak at which the position and the level are detected is either the peak of the correlation output R _a or R _b , the peak of the sum of the peaks, or the larger one of the peaks. Or any of them. Peak inspection unit
The peak position PP detected at 110 and its level L are stored in the storage unit 1
11 and stored in the storage unit 111 for each data section final signal ED.
Is stored. The storage unit 111 stores at least a peak position PP and a peak level L for the latest N data periods.

On the other hand, the detected peak position PP is also provided to the m / N determination unit 113, and the determination unit 113 captures the peak position PP for each data section end signal ED. The m / N determination unit 113 has a predetermined number m
And N are set. The predetermined numbers m and N may be switched between m 'and N' according to the synchronization signal (signal indicating the presence or absence of carrier detection) as described above. m / N determination unit 113,
In addition to determining to which area the given peak position PP belongs to a predetermined number in the data section,
The number of peak positions PP belonging to each area is counted over the data period. Then, when there is an area where a predetermined number m or more peak positions appear in the N data periods, a synchronization signal and a synchronization establishment signal TRACK are generated. The synchronization establishment signal TRACK is provided to the select terminal of the selector 104 described above. Further, the m / N determination unit 113 provides the calculation unit 112 with a determination result (data indicating an area in which a predetermined number m or more peak positions have appeared, data indicating the above-described signals PPEN and TRACK, etc.).

The arithmetic unit 112 receives the peak position data and, if necessary, the peak level data stored in the storage unit 111 and the m / N The weight average peak position Po is calculated using data indicating the area where m or more peak positions appear from the determination unit 113 and the like, and the calculated average load position Po is given to the register 102.

Thus, when synchronization is established, select 104 is set to register 1
Since the setting data (3/2) T-Po of 02 is selected and given to the comparator 105, the data section end signal ED is generated at such a timing that the load average peak position Po comes to the center of the data section. .

There are various methods for calculating the load average peak position Po. Typical examples are as follows.

(Part 1) Of J areas divided in one data section T,
It is assumed that there are r areas where m or more peak positions appear in the N data periods. Let the start positions of those areas be LSi, LEi. The load average peak position Po is calculated by the following equation.

Here, the sum Σ up to r means addition for an area where m or more peak positions have appeared.

(Part 2) The number of areas divided in one data section T is j. The number of appearances of the peak position in each area i (i = 1 to j) is PNi. The start position and end position of each area i are LSi and LEi, respectively. Load average peak position P
o is calculated by the following equation.

Here, the sum Σ up to j means addition for all areas. Also, It is.

FIG. 30 illustrates this method of calculating the load average peak position. For simplicity, j = 5, ie, one data section T
Is divided into five areas a to e. The start position and end position of each area are respectively LS _a =
0, LE _a = LS _b = 1, LE _b = LS _c = 2, LE _c = LS _d = 3, LE _d = LS _e = 4,
LE _d = 5s. In addition, the numbers of peak positions appearing in the areas a, b, c, d, and e are 3, 30, 15, 3, and 0, respectively. And N = 51. Substituting these data into equation (2) yields Po = 1.85.

(Part 3) Of the areas divided into j in one data section T,
It is assumed that there are r areas where m or more peak positions appear in the N data periods. The start position and the end position of those areas are LSi and LEi, respectively. Also, the sum of the peak levels in each of these areas is defined as PLi. The load average peak position Po is calculated by the following equation.

Here, the sum Σ up to r means addition for an area where m or more peak positions have appeared.

(Part 4) The number of areas divided in one data section T is j. The number of appearances of the peak position in each area i (i = 1 to j) is PNi. The start position and end position of each area i are LSi and LEi, respectively. Also, the sum of the peak levels of the peaks appearing in each area i is defined as PLi. The load average peak position Po is calculated by the following equation.

Here, the sum Σ up to j means addition for all areas. Also, It is.

In the configuration shown in FIG. The peak inspection unit 110, the storage unit 111, the calculation unit 112, and the m / N determination unit 113
It can be realized by software.

According to the first and second aspects of the invention, correlation peaks are observed over N periods of the PN code sequence, and when m or more correlation peaks appear in the same area, it is determined that synchronization has been established, and , The correlation peak position determined to be synchronized
Since the periodic signal is generated so as to be at the center of the center of the period of the PN code sequence, the synchronization establishment state can be quantitatively determined, and accurate demodulation can be performed using the periodic signal that maintains the synchronization establishment state. And so on.

According to the third and fourth aspects of the present invention, the correlation peak is observed over N periods of the code sequence, and when m or more correlation peaks are detected in the same area, it is determined that synchronization has been established. Since the periodic signal is generated such that the weighted average peak position of the peak position that appears in the N cycles is located at the center of the period of the PN code sequence, synchronization that focuses on the load average peak position obtained as the weighted average of the peak positions that appear. Due to the establishment, even when a correlation peak appears at a slightly different position due to a sudden noise or a change in the state of a transmission line, an excellent effect such as accurate demodulation using the above periodic signal can be performed. To play.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of the CSK communication system. FIG. 2 is a circuit diagram showing a configuration example of a modulation device,
FIG. 3 is a time chart showing the operation. FIG. 4 is a circuit diagram showing another example of the modulation device. FIG. 5 is a circuit diagram showing a configuration example of a pair of correlators, FIG. 6 is a circuit diagram showing a modification example thereof, and FIG. 7 is a circuit diagram showing another configuration example of the correlator. FIG. 8 is a circuit diagram showing a configuration example of the demodulation device, and FIG. 9 is a waveform diagram showing its operation. No.
FIG. 10 is a block diagram showing a configuration of the carrier detection circuit. FIG. 11 is a block diagram showing a configuration of a peak position detecting circuit, and FIG. 12 is a waveform diagram showing a peak position detecting operation. FIG. 13 is a block diagram showing another example of the peak position detection circuit, and FIG. 14 is a block diagram showing still another example of the circuit. FIG. 15 is an explanatory diagram showing a state in which one cycle of the M sequence is divided into a plurality of areas so as not to overlap. No.
FIG. 16 is a circuit diagram showing an example of a peak position determination circuit suitable for the area division shown in FIG. FIG. 17 is an explanatory diagram showing a state in which one cycle of the M-sequence is divided into a plurality of areas so as not to overlap, and FIG. 18 is a circuit showing an example of a peak position determination circuit suitable for the area division in FIG. FIG. FIG.
FIG. 20 is an explanatory diagram showing a state in which one cycle of the M sequence is divided into a plurality of areas so as to overlap with an adjacent area by half. FIG. 20 shows an example of a peak position determination circuit suitable for the area division shown in FIG. It is a circuit diagram. FIG. 21 is a circuit diagram showing another example of the peak position determination circuit suitable for the area division shown in FIG. 22nd
FIG. 4 is an explanatory diagram showing a state in which one cycle of an M sequence is divided into a plurality of areas so as to overlap an adjacent area by 1/2 or more. FIG. 23 is a circuit diagram showing an example of a peak position determination circuit suitable for the area division shown in FIG. FIG. 24 is a circuit diagram showing another example of the peak position determination circuit suitable for the area division shown in FIG. FIG. 25 is a block diagram showing an example of a counting circuit and an m / N determination circuit, and FIG. 26 is a block diagram showing a modification thereof. FIG. 27 is a block diagram showing an example of a circuit for generating a data section end signal included in the synchronization control circuit.
FIG. 9 is a waveform chart showing an operation example thereof. FIG. 29 is a block diagram showing another example of a synchronization control circuit including a carrier detection circuit and a data section end signal generation circuit, and FIG. 30 shows an example of the operation thereof, particularly an example of a load average peak position calculation process. It is a graph. FIG. 31 and FIG. 32 show a conventional SS communication method. FIG. 31 is a circuit diagram showing a configuration, and FIG. 32 is a time chart showing the operation thereof. 24 Carrier detection circuit 25 Synchronous control circuit 26 Peak position detection circuit 27 Peak position determination circuit 28 Count circuit 29 m / N determination circuit 110 Peak inspection unit 111 Storage unit 112 Calculation unit 113 m / N judgment unit

 ──────────────────────────────────────────────────続 き Continuation of the front page Examiner Kenichi Ishii (56) References JP-A-3-192836 (JP, A) JP-A-60-5637 (JP, A) JP-A-2-114431 (JP, A) JP-A-2-24639 (JP, A) JP-A-2-246548 (JP, A)

Claims (12)

(57) [Claims] 1. A PN code sequence having a low cross-correlation and having the same code length, which is generated at a fixed period, is transmitted from the transmitting side in correspondence with one of transmission data 1 and 0 at the fixed period. A signal is received, the received signal is correlated with the same two PN code sequences used on the transmission side, and a peak position indicating the position of a correlation peak appearing in the two correlation outputs is set to one of the PN code sequences. 1 per cycle, most often
Detection is performed over a predetermined number N cycles defined by the above integers, and it is determined which of a plurality of areas where the detected peak position is allowed to overlap within the one cycle belongs to, and The number of correlation peaks detected for each area is counted, and during the predetermined number N cycles, the correlation peak count value in any one area is 1 or more and N
It is determined whether or not a predetermined number m determined by the following integer has been reached, and if it has reached, synchronization has been established, and when synchronization has been established, the peak position at which the correlation peak count value has reached the predetermined number m, A method for establishing synchronization, characterized by generating a periodic signal that defines the period so as to be at the center of the period of the PN code sequence. 2. A PN code sequence having the same code length and having a low cross-correlation generated at a constant period is transmitted from the transmitting side in correspondence with one of transmission data 1 and 0 at the constant period. A signal is received, the received signal is correlated with the same two PN code sequences used on the transmission side, and a peak position indicating the position of a correlation peak appearing in the two correlation outputs is set to one of the PN code sequences. 1 per cycle, most often
A peak position detection circuit for detecting over a predetermined number N cycles defined by the above integers, and determining to which of a plurality of areas the detected peak positions belong while being allowed to overlap within the one cycle A peak position determination circuit, a counting circuit that counts the number of correlation peaks detected for each of the areas over the predetermined number N cycles at the maximum, and any one of the predetermined number N cycles. It is determined whether the correlation peak count value in the area has reached a predetermined number m defined by an integer of 1 or more and N or less,
An m / N determination circuit that outputs a synchronization establishment signal if it has reached,
The peak position at which the correlation peak count value has reached the predetermined number m is stored, and when the synchronization establishment signal is output from the m / N determination circuit, the stored peak position is the period of the PN code sequence. And a periodic signal generating circuit for generating and outputting a periodic signal defining the cycle so as to be located at the center of the synchronization establishing apparatus. 3. A PN code sequence having the same code length and having a low cross-correlation generated at a constant period is transmitted from the transmitting side in correspondence with either 1 or 0 of transmission data at the constant period. A signal is received, the received signal is correlated with the same two PN code sequences used on the transmission side, and a peak position indicating the position of a correlation peak appearing in the two correlation outputs is set to one of the PN code sequences. Detected for each cycle, and stored for a predetermined number N cycles determined by an integer of 1 or more in the case of the largest number, and for each of the stored peak positions for the predetermined number N cycles, the overlap is permitted within the one cycle. It is determined which of the plurality of divided areas belongs to, the number of correlation peaks detected for each area is counted, and the number of correlation peaks in any one area is counted during the predetermined number N cycles. Peak count value to determine if it has reached the predetermined number m which defines with an integer 1 or more N,
If the synchronization has been reached, it is assumed that synchronization has been established, and a load average peak position obtained by multiplying the stored peak position by a predetermined load and arithmetically averaging is calculated. When it is determined that synchronization has been established, the calculated load average is calculated. A method for establishing synchronization, wherein a periodic signal that defines the period is created such that a peak position is located at the center of the period of the code sequence. 4. The synchronization establishment according to claim 3, wherein, when there are a plurality of areas where the correlation peak count value is equal to or more than the predetermined number m, the average position of the center positions of these areas is set as the load average peak position. Method. 5. A load average peak position is calculated based on a sum of products of a center position of the area and the number of times of occurrence of a peak for all the areas included in one cycle.
Method for establishing synchronization. 6. In addition to the correlation peak position, the peak is detected and stored, and when there are a plurality of areas where the peak position count value is equal to or greater than a predetermined number n, the center position of each area and the detection at that area are performed. 4. A weight average peak position is calculated by calculating a product of the sum of peak levels and a sum of the products for the plurality of areas.
Method for establishing synchronization. 7. A correlation peak position is detected and stored in addition to a correlation peak position, and a center position of an area for all areas included in the one cycle and a peak position in the area are determined.
The synchronization establishing method according to claim 3, wherein the load average peak position is calculated based on a sum of products of the level sum. 8. A PN code sequence having the same code length and having a low cross-correlation generated at a fixed period is transmitted from the transmitting side in correspondence with one of transmission data 1 and 0 at the fixed period. A signal is received, the received signal is correlated with the same two PN code sequences used on the transmission side, and a peak position indicating the position of a correlation peak appearing in the two correlation outputs is set to one of the PN code sequences. Peak inspection means for detecting each cycle, storage means for storing the detected peak position over a predetermined number N cycles defined by an integer of 1 or more in the case of the largest, and peaks for the stored predetermined number N cycles For each of the positions, while determining which area among the plurality of areas divided to allow overlap within the one cycle, and counting the number of correlation peaks detected for each area, During the predetermined number N cycles, it is determined whether the correlation peak count value in any one area has reached a predetermined number m defined as an integer of 1 or more and N or less, and if it has reached, it is determined that synchronization has been established. Determining means, calculating means for calculating a load average peak position obtained by multiplying a peak position stored in the storage means by a predetermined load and arithmetically averaging, and calculating the synchronization when it is determined that synchronization is established; And a periodic signal generating means for generating and outputting a periodic signal defining the cycle so that the load average peak position calculated by the means is located at the center of the cycle of the PN code sequence. Establishing device. 9. When there are a plurality of areas having a correlation peak count value of a predetermined number m or more, the arithmetic means calculates an average position of the center positions of these areas as a load average peak position. Synchronization establishing device according to claim 1. 10. The calculation means calculates a load average peak position based on the sum of products of the center position of the area and the number of peak occurrences for all the areas included in the one cycle. The synchronization establishing device according to (8). 11. The peak inspection means detects a peak level in addition to a correlation peak position, and the storage means stores the peak level in relation to the correlation peak position.
When there are a plurality of areas where the correlation peak count value is equal to or greater than the predetermined number m, the calculating means calculates the center position of each area and the sum of the peak levels detected in the area. The synchronization establishing device according to claim 8, wherein a product of calculating the load average peak position is calculated by using a result of adding the product for the plurality of areas. 12. The peak inspection means detects a peak level in addition to a correlation peak position, and the storage means stores the peak level in relation to the correlation peak position.
The arithmetic means calculates the load average peak position based on the sum of the product of the center position of the area and the sum of the peak levels in the area with respect to all the areas included in the one cycle. The synchronization establishing device according to claim 8, wherein the synchronization is calculated.