JPH03192822A - Clock generator - Google Patents

Abstract

PURPOSE:To always extract a stable clock by providing a signal missing period detection means and a delay means and controlling the switching of a gate means synchronously with the leading edge of the clock detected just after an input digital signal is missing. CONSTITUTION:A logic arithmetic output signal (f) controlling directly the switching of gates 2, 3 is synchronized with the leading edge of a regenerating clock (a). As a result, a fault pulse disturbing the PLL operation does not appear in the output signal (h) of the gate 3 and the output signal (g) of the gate 2 at the time of starting and ending for dropout period. That is, a clock generator 10a applies switching control to the gates 2, 3 directly by a dropout signal (e). Then after a signal change in the dropout signal (e) is detected, the gates are subject to switch control synchronously with the timing of the leading edge of the succeeding recovered clock (a). Thus, the recovered clock (a) always stable is extracted together with the dropout period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock generation device, and more particularly to a clock generation device that extracts a clock component contained in an input digital signal and generates a clock.

[Prior Art] In a conventional digital signal reproducing device, a phase locked loop (hereinafter referred to as PL) is used to generate a clock for signal reproduction.
(referred to as L) is adopted.

The basic configuration of PLL is a phase comparator (hereinafter referred to as PD).
, a type of automatic control system consisting of a loop filter (hereinafter referred to as LF) and a voltage controlled oscillator (hereinafter referred to as CO), and the PLL synchronizes the phase of the output wave with the phase of the input wave. It works like this.

FIG. 3 is a schematic block diagram of a clock generator 10b applied to a conventional digital signal reproducing device.

The input signal of the illustrated clock generator 10b is a reproduced digital signal reproduced from a signal storage medium, and the output signal is a reproduced clock a extracted from the reproduced digital signal.

This extracted reproduction clock a is transmitted to the waveform extraction device 1.
It is given to the device connected to the next stage of 0b.

In the figure, clock generator 10b includes a PDI, gates 2 and 3, LF4, VCO5, and dropout detection circuit 6. Also, PDI, LF4 and VCO5
The above-mentioned PLL operation is realized by a closed loop having elements of . Furthermore, the clock generator 10b is provided with gates 2 and 3 at the output stage of the PDI to prevent the synchronization timing of the reproduction clock a from being shifted due to the PLL operation being changed during the dropout period of the supplied reproduction digital signal. However, the details will be explained later. In addition, VCO5
If no input signal is given, it oscillates at a predetermined center frequency (the frequency of the ideal reproduction clock a).

Here, dropout of digital signals will be explained.

Dropout refers to a brief loss of signal.

The causes of this dropout include the adhesion of dust and foreign matter to the magnetic tape or optical disk, which are signal storage media, and large irregularities on the surface.

If the reproduced digital signal includes dropouts, the reproduced signal cannot be recovered due to signal loss. In other words, in a digital signal, if even one bit of the signal is shifted or missing, it becomes completely different information. For this reason, the reproduced digital signal is divided into small blocks, so that even if the signal is disturbed, bit synchronization is applied when a new block arrives and the boundaries of the blocks can be determined. The clock generator 10b operates for this purpose, and extracts the clock (JIL quasi-interval that separates each digital pit) component contained in the given reproduced digital signal to generate the reproduced clock a. .

FIGS. 4(a) to 4(h) are timing charts showing human output signal waveforms at various parts of the clock generator 10b shown in FIG. 3 above.

FIG. 4(a) shows the waveform of an abnormal reproduction clock a1, which will be described later, and is output from the VCO 5 as an output signal of the clock generator 10b.

FIG. 4(b) shows the waveform of a normal reproduction clock a, which is output from the VCO 5 as an output signal of the clock generator 10b. FIG. 4(C) shows the waveform of the reproduced digital signal, which is input to the PDI as an input signal to the clock generator 10b.

As shown in FIG. 3, the PDI outputs two signals C and d, and FIG. 4(d) shows the first output signal C of the PDI.
FIG. 4(e) shows the second output signal d of the PDI. Fourth
FIG. 5(f) shows the waveform of a dropout signal e indicating the dropout period of the reproduced digital signal S, which is output from the dropout detection circuit 6. FIG. 4(g) shows the waveform of the output signal g of gate 2, and FIG.
) shows the waveform of the output signal of gate 3. Next, the third
The operation of the conventional clock generating device 10b shown in the figure will be explained with reference to FIGS. 3 and 4.

As shown in FIG. 3, the +lr raw digital signal containing the clock component applied to the clock generator 10b is
It is applied to PDI and dropout detection circuit 6 at the same time.

First, the PDI is given the reproduction clock a fed back from the output stage of the VCO 5 and the aforementioned reproduction digital signal S, and accordingly, the first output signal C is sent to the gate 2, and the second output signal d is sent to the gate 3. Output. To explain in detail, as shown in FIG. 4(d), PDI converts the first output signal C from the rising and falling edges of the reproduced digital signal S to the rising edge of the reproduced clock a detected immediately thereafter. The signal level is set to “HIGH” during the period t1 until
Set and output. That is, the pulse width of the first output signal C corresponds to the period t1. Further, the second output signal d is outputted so as to have a pulse width corresponding to the period t2 from the fall of the first output signal C to the rise of the reproduction clock a detected immediately thereafter. Therefore, the pulse width t1 of the first output signal C is equal to the length of 1/2 period of the reproduction clock a when the rising and falling edges of the reproduction digital signal S and the rising edges of the reproduction clock a are aligned. However, if the rise of the reproduction clock a lags behind the rise and fall of the reproduction digital signal S, the pulse width t1 of the first output signal C becomes longer than 1/2 period of the reproduction clock a, and conversely becomes faster. If the first
The pulse width t1 of the output signal C is 1/2 of the reproduction clock a.
shorter than the period. On the other hand, the pulse width t2 of the second output signal d of the PDI is always equal to the length of 1/2 cycle of the reproduction clock a, as shown in FIG. 4(d).

On the other hand, the dropout detection circuit 6 inputs the reproduced digital signal S and normally outputs the dropout signal e at signal level "HIC;H'. However, when a dropout is detected in the supplied reproduced digital signal, the dropout The signal level of the signal e is changed from "HIGH" to "LOW" and output.

To explain in detail, the dropout detection circuit 6 is as follows.
A digital signal pattern for detecting dropout is stored in advance, and if it is detected that the signal pattern of the supplied reproduced digital signal matches the stored digital signal pattern for dropout detection, the dropout signal e is detected. Change the signal level from “HIGH” to “
After that, when it is detected that the signal pattern of the reproduced digital signal has been restored to normal,
It operates to return the signal level of the dropout signal e from "LOW" to "HIGH".

Therefore, the gates 2 and 3 to which the dropout signal e indicating the dropout period is applied from the dropout detection circuit 6 are normally set to the open state, that is, during the period in which no dropout occurs in the reproduced digital signal, and are set to the open state. The first output signal C given from PDl of
and operates to pass the second output signal d. However, during the period in which dropout occurs in the reproduced digital signal, the gates 2 and 3 are set to the closed state by the dropout signal e, so that their output signals are both at the "LOW" level.

It is now assumed that the dropout detection circuit 6 does not detect any dropout in the reproduced digital signal and supplies the dropout signal e at the signal level "HIGH" to each gate 2 and 3. At this time, the first output signal C is
, and is given to LF4 as gate 2 output signal g. Similarly, the second output signal d passes through the gate 3 and is applied to the LF4 as the gate 3 output signal. Accordingly, LF4 outputs gate 2 output signal g and gate 3 output 16
Then, only the low frequency component of the subtraction result is applied to the next stage VCO 5 as a control voltage. In other words, LF4 is 1
This is a type of low-pass filter that filters the voltage waveform corresponding to the phase difference of the input signal and applies the control voltage obtained to the next stage VCO.
5 control terminal (not shown). Depending on the VCO5
generates and outputs a reproduction clock a.

Now, as mentioned above, the PLL operation operates to synchronize the phase of the reproduction clock a of the VCO 5, which oscillates at a predetermined center frequency, with the phase of the reproduction digital signal S, as shown in FIG. The pulse width (tl-
t2). In other words, P
1 of VCO5 in the direction that the phase difference between the input and output waves of LL is reduced.
The oscillation frequency of the 4th generation clock a changes. for example,
Regarding the pulse width, when (tl>t2), the oscillation operation of the VCO 5 is accelerated, and when (tl<t2), the oscillation operation of the VCO 5 is decelerated, and the pulse width is controlled to be (tl-t2). In this way, the phase is controlled so that the rising and falling edges of the reproduced digital signal S are aligned with the rising edges of the reproduced clock a, and a stable reproduced clock a is extracted from the reproduced digital signal S.

By the way, if it is assumed that the reproduced digital signal includes a dropout, the phase of the reproduced digital signal will be disturbed, the PLL operation will become unstable, and the synchronization of the reproduction clock a will also be lost.

To prevent this, dropout detection circuit 6 and gates 2 and 3 are provided.

The dropout detection circuit 6 detects a dropout period of the reproduced digital signal e, sets the dropout signal e to a signal level "LOW" during the dropout period, and
It is given to gates 2 and 3 in the next stage. Therefore, during the dropout period of the reproduced digital signal, gates 2 and 3 are set to the closed state, so that the PDI and gate 2
The phase comparison operation between the reproduced digital signal and the reproduced clock a carried out by 3 and 3 is stopped +1-, which is equivalent to the state in which the reproduced digital signal is not input, so that the VCO 5 is
First, it oscillates at a determined center frequency.

Therefore, the clock generator 10b can output the reproduction clock a even during the dropout period of the reproduction digital signal.

[Issue A to be Solved by the Invention] As described above, in the conventional clock generation bag 'K10b shown in FIG.
Since the opening/closing of gates 2 and 3 is directly controlled using the gate 2, as shown in FIG. Accordingly, the oscillation operation of the VCO 5 may be accelerated. Also, at the end of dropout, an abnormal pulse β2 appears in the gate 3 output signal,
Accordingly, the oscillation operation of the VCO 5 may be slowed down. In other words, as shown in FIG. 4(a), the regenerated clock a1 whose synchronization timing has shifted during the dropout period described above repeats phase advances and lags during the dropout period, and the phase of the regenerated clock a It can be seen that the oscillation is being adjusted to be synchronized with the oscillation. As described above, there is a problem that the synchronization timing of the PLL operation is shifted, and the reproduction clock a cannot be stably obtained during the dropout period.

Therefore, an object of the present invention is to provide a clock generation device that can always stably extract a reproduction clock from an input digital signal even during a dropout period from the start to the end of dropout of the input digital signal. It is to be.

[Means for Solving the Problems] A clock generation device according to the present invention is a clock generation device that generates a clock by extracting a clock component contained in an input digital signal. The configuration includes a phase-locked loop means for extracting a clock synchronized with the input digital signal, a signal missing period detecting means for detecting a missing period of the input digital signal, and a detection signal of the signal missing period detecting means. , a delay means for delaying the signal to a predetermined timing; and in response to the output of the signal loss period detecting means delayed by the delay means, maintaining a synchronization loop locked before the signal loss by the phase locked loop means. and means for gating.

[Function] Since the clock generating device according to the present invention is configured as described above, the opening/closing control of the first stage of the gater is synchronized with the rising edge of the clock detected immediately after the loss of the input digital signal occurs. By doing this, it is possible to maintain the locked synchronization loop before the signal loss period and extract a stable clock even during the signal loss period.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic block diagram of a clock generation device 10a applied to a digital signal 11f generation device according to an embodiment of the present invention. In the figure, a clock generator 10a has a PDI, a gate 1-
2 and 3, LF4, VC05 and dropout detection circuit 6. Furthermore, the clock generator 10a is r
It includes stabilized multivibrators (hereinafter referred to as MV) 7 and 8 and altruistic OR circuits (hereinafter referred to as FOR) 9a and 9b. Note that the PDI or dropout detection circuit 6 operates in the same manner as in the prior art. Also, MV
7 inputs the reproduction clock a and the dropout signal e, and generates a one-shot pulse in response to the fall of the dropout signal e, and MV8 inputs the reproduction clock a and the dropout signal e, and generates a one-shot pulse in response to the fall of the dropout signal e. Out signal e
A one-shot pulse is generated in response to the rising edge of the signal. Also, EOR9a and 9b are MV7 and MV8
The output signals f1 and f2 and the dropout signal e are inputted and subjected to a logical operation, and the output signal f is applied to the gates 2 and 3 of the next stage. Note that the logical operation output signal f is a signal for directly controlling the open/close states of the gates 2 and 3.

Here, input/output signals of each part shown in FIG. 1 will be explained.

FIGS. 2(a) to 2(j) are timing charts showing human output signal waveforms of each section shown in FIG. 1 above.

Figure 2 (a) shows the reproduction clock a which is the output of the VCO5.
1 Figure 2 (b) is the reproduced digital signal b1 Figure 2 (c)
is the first output signal C1 of the PDI. FIG. 2(d) is the second output signal d1 of the PDI. FIG. 2(e) is the dropout signal e1 which is the output of the dropout detection circuit 6. FIG. 2(f)
is the output signal f1 of MV7, FIG. 2(g) is the output signal f2 of MV8, FIG. 2(h) is the logic operation output signal f of EOR9a and 9b, and FIG. 2(i) is the gate 2 output signal g and FIG. 2(j) shows each wave 11 of the gate 3 output signal.

The operation of the clock generator 10a constructed as described above will be explained.

The clock generator 10a is a conventional clock generator 1.
Similarly to 0b, PLL operation is performed by a closed loop of PDI, LF4, and VCO5, and it operates so as to stably output the reproduction clock a from the supplied reproduction digital signal.

First, the dropout signal e detected by the dropout detection circuit 6 and indicating the dropout period of the reproduced digital signal is MV7 and MV8, and the EOR.
9b at the same time.

Accordingly, as shown in FIG. 2(f), MV7 rises in synchronization with the falling edge of the applied dropout signal (the start of the dropout period), and continues until the rising edge of the reproduction clock a detected immediately after. A one-shot pulse α1 having a pulse width of a period of is generated. Furthermore, MV8 rises in synchronization with the rise of the applied dropout signal e (the end of the dropout period) as shown in FIG. A one-shot pulse β1 having a pulse width of 0.055 ms is generated. One shot pulse α as above
Output signals f1 and β2 containing 1 and β1 are applied to the next stage FOR gate 9H.

Accordingly, the EOR gate 9a sets its output signal level to "HIGH" only during the input period of the pulse α1 of the signal f1 or the input period of the pulse β1 of the signal f2, and
It is given to gate 9b. FOR gate 9b is the previous stage FO
It is supplied with the output signal of the R gate 9a and the dropout signal e, and outputs a logic operation output signal f as shown in FIG. 2(h). This logic operation output signal f is gate 2
and 3 at the same time, and the open/close states of gates 2 and 3 are controlled accordingly.

By the way, as shown in FIG. 2(h), the logical operation output signal f that directly controls the opening and closing of gates 2 and 3 is 1
Since it is synchronized with the rising edge of the clock a for the 11th generation, there will be no abnormal noise that would disturb the PLL operation in the gate 2 output signal g and the gate 3 output signal at the start and end of the dropout period. . Therefore, the operation of LF4 and VCO5 from the next stage onward is stable, and there is no mud.
A stable reproduction clock a is extracted even during the bulge-out period. In other words, the clock generator 10a does not directly control the opening/closing of gates 2 and 3 using the dropout signal e; instead, the clock generator 10a does not directly control the opening and closing of the gates 2 and 3 using the dropout signal e. Opening/closing control is performed in synchronization with the timing of the rising edge of the signal.Therefore, the gate 2 output signal g and the gate 3 output signal, which are the output signals of the phase comparison operation, do not contain abnormal pulses.
The PLL operation is not disturbed by abnormal pulses (and a stable reproducing clock a can be extracted at all times, including during the idle/knob-out period).

[Effects of the Invention] As described above, according to the present invention, even if the input digital signal includes a dropout period, it is possible to always stably obtain the clock extracted from the input digital signal (No. 5). can.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a clock generation device applied to a digital signal reproducing device according to an embodiment of the present invention. FIG. 2 is a timing chart of input and output signals of each part of the clock generator shown in FIG. 1. FIG. 3 is a schematic block diagram of a clock generator applied to a conventional digital signal reproducing device. FIG. 4 is a timing chart of input/output signals of each part of the clock generator shown in FIG. 3. In the figure, 1 is a phase comparator (PD), 2 and 3 are gates, 4 is a Leboeuf filter (LF), 5 is a voltage controlled oscillator (VCO), 6 is a dropout detection circuit,
7 and 8 are monostable multi-by-break (MV), 9a
and 9b is exclusive OR circuit (EOR), a is +l
ll reciprocal lock, b is 1 the raw digital signal, e is the dropout signal and f is the logic operation output signal. In addition, in each figure, the same initial number indicates the same or corresponding part.隘−5ε こ 纺; ! 5 Self Fu^su^hahehehehe S 5 B 85℃ beg

Claims (1)

[Scope of Claims] A clock generation device that generates a clock by extracting a clock component included in an input digital signal, comprising: phase-locked loop means for extracting a clock synchronized with the input digital signal; Signal missing period detection means for detecting a missing period of an input digital signal; Delay means for delaying the detection signal of the signal missing period detection means to a predetermined timing; and the signal missing period delayed by the delay means. and means for gating, in response to the output of the detection means, so as to maintain the synchronization loop locked by the phase-locked loop means before the loss.