JPH03192722A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPH03192722A JPH03192722A JP33108789A JP33108789A JPH03192722A JP H03192722 A JPH03192722 A JP H03192722A JP 33108789 A JP33108789 A JP 33108789A JP 33108789 A JP33108789 A JP 33108789A JP H03192722 A JPH03192722 A JP H03192722A
- Authority
- JP
- Japan
- Prior art keywords
- layer wiring
- upper layer
- insulating film
- lower layer
- edges
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010410 layer Substances 0.000 claims abstract description 51
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 239000000155 melt Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 235000010627 Phaseolus vulgaris Nutrition 0.000 abstract 1
- 244000046052 Phaseolus vulgaris Species 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 229910018182 Al—Cu Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
ゲートアレイなどの半導体集積回路装置（セミカスタム
ＩＣ）の製造方法に関し、
半導体装置での多層配線で下層配線と上層配線との回路
上必要なコンタクトを、マスクおよび選択エツチング法
を用いないで上層配線の形成後に選択的に形成する方法
を提供することを目的とし、半導体基板上に下層配線を
形成し；該下層配線上に複数のコンタクトホールが形成
された眉間絶縁膜を形成すること及び該層間絶縁膜上に
上層配線を形成することを行い、該コンタクトホールの
縁部に該上層配線の縁部が位置するようにし；コンタク
トをとるべきコンタクトホールの縁部に位置する該上層
配線の縁部に選択的にレーザを照射して前記上層配線の
縁部を溶融し、コンタクトホール内へ流し込むことで下
層配線と前記上層配線とを選択的に導通するように構成
する。[Detailed Description of the Invention] [Summary] Regarding a method of manufacturing a semiconductor integrated circuit device (semi-custom IC) such as a gate array, the present invention relates to a method for manufacturing a semiconductor integrated circuit device (semi-custom IC) such as a gate array, and a method for making contacts necessary for the circuit between lower layer wiring and upper layer wiring in multilayer wiring in a semiconductor device. The present invention aims to provide a method for selectively forming an upper layer wiring after forming an upper layer wiring without using a mask and a selective etching method, and a lower layer wiring is formed on a semiconductor substrate; a plurality of contact holes are formed on the lower layer wiring. forming a glabellar insulating film and forming an upper layer wiring on the interlayer insulating film so that the edge of the upper layer wiring is located at the edge of the contact hole; Selectively irradiating the edge of the upper layer wiring located at the edge with a laser to melt the edge of the upper layer wiring and pouring it into the contact hole to selectively conduct the lower layer wiring and the upper layer wiring. Configure it as follows.
本発明は、ゲートアレイなどの半導体装置（セミカスタ
ムＩＣ）の製造方法に関する。The present invention relates to a method of manufacturing a semiconductor device (semi-custom IC) such as a gate array.
近年のセミカスタムＩＣの生産においては、ユーザーと
の契約から納入までの期間（納期）の短縮化の要求に伴
い、配線工程も簡略化が求められている。In recent years, in the production of semi-custom ICs, there is a need to simplify the wiring process as well as to shorten the period from signing a contract with a user to delivery (delivery date).
〔従来の技術］
半導体装置製造における配線形成工程では、−種類の半
導体装置（ＩＣ）毎に何枚ものマスク（リソグラフィ用
マスク）を用いていた。このマスクの設計、製作に時間
がかかり、納期を長びかせる要因となっている。[Prior Art] In the wiring formation process in semiconductor device manufacturing, a number of masks (lithography masks) are used for each type of semiconductor device (IC). It takes time to design and manufacture these masks, which is a factor that lengthens delivery times.
一種類の半導体装置毎にコンタクトホール用マスク、配
線パターン用マスクなどを設計、製作するのではなく、
これらマスクを規格化して広く適用するようにしてマス
ク製作期間を短かくすることが可能である。それでも配
線を半導体装置毎に所定ＩＣ回路となるようにする必要
がある。Rather than designing and manufacturing contact hole masks, wiring pattern masks, etc. for each type of semiconductor device,
By standardizing these masks and making them widely applicable, it is possible to shorten the mask manufacturing period. Even so, it is necessary to arrange the wiring to form a predetermined IC circuit for each semiconductor device.
本発明の目的は、半導体装置での多層配線で下層配線と
上層配線との回路上必要なコンタクトを、マスクおよび
選択エツチング法を用いないで上層配線の形成後に選択
的に形成する方法を提供することである。An object of the present invention is to provide a method for selectively forming circuit-required contacts between lower-layer wiring and upper-layer wiring in multilayer wiring in a semiconductor device after forming the upper-layer wiring without using a mask or selective etching method. That's true.
上述の目的が、半導体基板上に下層配線を形成し；該下
層配線上に複数のコンタクトホールが形成された眉間絶
縁膜を形成すること及び該層間絶縁膜上に上層配線を形
成することを行い、該コンタクトホールの縁部に該上層
配線の縁部が位置するようにし；コンタクトをとるべき
コンタクトホールの縁部に位置する該上層配線の縁部に
選択的にレーザを照射して前記上層配線の縁部を溶融し
、コンタクトホール内へ流し込むことで下層配線と前記
上層配線とを選択的に導通ずることを特徴とする半導体
集積回路装置の製造方法によって達成される。The above purpose is to form a lower layer wiring on a semiconductor substrate; to form a glabellar insulating film in which a plurality of contact holes are formed on the lower layer wiring, and to form an upper layer wiring on the interlayer insulating film. , the edge of the upper layer wiring is positioned at the edge of the contact hole; the edge of the upper layer wiring located at the edge of the contact hole to be contacted is selectively irradiated with a laser to remove the upper layer wiring; This is achieved by a method of manufacturing a semiconductor integrated circuit device, which is characterized in that the lower layer wiring and the upper layer wiring are selectively electrically connected by melting the edge of the layer and pouring it into the contact hole.
上層配線には、アルミニウム（Ａｆｆｉ）ないしその合
金ＣＡＲ−Ｃｕ、Ａｊｌ！−３ｉ、Ａｌ１−３ｉ Ｃ
ｕ）等の金属が好ましい。For upper layer wiring, aluminum (Affi) or its alloy CAR-Cu, Ajl! -3i, Al1-3i C
Metals such as u) are preferred.
本発明のコンタクトホールを形成するために、絶縁膜を
２層構造にして、その下層側絶縁膜（例えば、Ｐ Ｓ
Ｇ１１ｌｌりのエッチレートを上層側絶縁膜（例えば、
ＳｉＯ□膜）よりも速いものとする。上層側絶縁膜を異
方性エツチングし、下層側絶縁膜を等方性エツチングす
ることが好ましい。In order to form the contact hole of the present invention, the insulating film has a two-layer structure, and the lower insulating film (for example, P S
An etch rate of about G11ll is applied to the upper insulating film (for example,
(SiO□ film). Preferably, the upper insulating film is anisotropically etched and the lower insulating film is isotropically etched.
以下、添付図面を参照して、本発明の実施態様例によっ
て本発明の詳細な説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail by way of embodiments with reference to the accompanying drawings.
第１Ａ図〜第１Ｄ図は、本発明に係る層間コンタクト形
成方法工程での半導体集積回路装置の部分断面図である
。1A to 1D are partial cross-sectional views of a semiconductor integrated circuit device in steps of an interlayer contact forming method according to the present invention.
先ず、第１Ａ図に示すように、半導体基板（シリコンウ
ェハ）１の上に熱酸化法又はＣＶＤ法によって絶縁膜（
例えば、Ｓｉｎ、膜）２を形成する。First, as shown in FIG. 1A, an insulating film (
For example, a Sin (film) 2 is formed.
その上に下層メタル膜（例えば、Ａ２合金）３をスパッ
タリング法又は真空蒸着法によって全面形成する。次に
、レジスト膜（図示せず）を塗布し、所定の規格化（標
準化）されたマスクを用いて露光し、現像してから、こ
のレジスト膜をマスクとして下層メタル膜３を選択エツ
チングして所定配線パターンにする。レジスト膜除去後
に、下層側絶縁膜（例えば、ＰＳＧ膜、２００ｎｍ厚さ
）４を、続いて上層側絶縁膜（例えば、５ｉ（ｈ膜、８
００ｎｍ厚さ）５をＣＶＤ法によって全面形成する。こ
れら絶縁膜４，５が一体となって眉間絶縁膜となる。A lower metal film (for example, A2 alloy) 3 is formed thereon over the entire surface by sputtering or vacuum evaporation. Next, a resist film (not shown) is applied, exposed using a predetermined standardized mask, developed, and then the lower metal film 3 is selectively etched using this resist film as a mask. Create a specified wiring pattern. After removing the resist film, a lower insulating film (e.g., PSG film, 200 nm thick) 4 is formed, and then an upper insulating film (e.g., 5i (h film, 8
00 nm thick) 5 is formed on the entire surface by CVD method. These insulating films 4 and 5 together form a glabellar insulating film.
第１Ｂ図に示すように、レジスト膜６を塗布形成し、所
定の規格化（標準化）されたマスクを用いて露光し、現
像してコンタクトホールに相当する開ロアを有するレジ
ストマスク膜６を形成する。As shown in FIG. 1B, a resist film 6 is coated, exposed using a predetermined standardized mask, and developed to form a resist mask film 6 having an open lower portion corresponding to a contact hole. do.
ＲＩＥなどの異方性エツチングによって上層側絶縁膜５
をさらに下層側絶縁膜４の７部をも除去し、次に、下層
側絶縁膜４のエッチレートが上層側絶縁膜５のエッチレ
ートよりも大幅に速い条件の等方性エツチングによって
下層側絶縁膜４を第１Ｂ図に示すようなコンタクトホー
ル８となるように部分的に除去する。コンタクトホール
８の上層側絶縁膜５での直径を、例えば、２μｍとなる
ようにし、下層側絶縁膜４の上面での直径は約２．４μ
ｍとなる。The upper insulating film 5 is etched by anisotropic etching such as RIE.
Further, 7 parts of the lower insulating film 4 are removed, and then the lower insulating film 4 is etched by isotropic etching under conditions where the etch rate of the lower insulating film 4 is much faster than the etch rate of the upper insulating film 5. The film 4 is partially removed to form a contact hole 8 as shown in FIG. 1B. The diameter of the contact hole 8 at the upper insulating film 5 is, for example, 2 μm, and the diameter at the upper surface of the lower insulating film 4 is approximately 2.4 μm.
m.
レジスト膜６の除去後に、スパッタリング法又は真空蒸
着法によって上層メタル膜（例えば、Ａ ｌ −Ｃｕ合
金膜、８００ｎｍ厚さ）１０Ａを上層側絶縁膜５上に形
成し、同時にコンタクトホール内にメタル部分１０Ｂが
形成される。このときに、コンタクトホール８において
上層側絶縁膜５がオーバーハング状になっているので、
上層メタル膜１０Ａと下層メタル膜３とが確実に断線状
態（接続しない状態）になっている。上層メタル膜１０
Ａはコンタクトホール８の直径よりも内側へ少し突出し
てオーバーハング状になっている。次に、レジスト膜（
図示せず）を塗布し、所定の規格化されたマスクを用い
て露光し、現像してから、このレジスト膜をマスクとし
て上層メタル層１０Ａを選択エツチングして所定配線パ
ターンにする。この配線パターンでコンタクトホールの
周囲には同心円状に大きめ（例えば、直径約４μｍ）の
円形部分とする。レジスト膜除去後に、バスルレーサＡ
、 Ｂ（例えば、スポット径：４μｍ、エネルギー：２
８．３μＪ）をコンタクトをとる必要箇所のみにコンタ
クトホールと同心状に照射する。したがって、レーザ照
射されないコンタクトホールが多数存在しており、所定
回路構成に必要なコンタクトホールが選択的に照射され
るわけである。After removing the resist film 6, an upper metal film (e.g., Al-Cu alloy film, 800 nm thick) 10A is formed on the upper insulating film 5 by sputtering or vacuum evaporation, and at the same time a metal portion is formed in the contact hole. 10B is formed. At this time, since the upper insulating film 5 has an overhang shape in the contact hole 8,
The upper metal film 10A and the lower metal film 3 are definitely in a disconnected state (not connected). Upper metal film 10
Point A projects slightly inward from the diameter of the contact hole 8 and has an overhang shape. Next, resist film (
(not shown) is applied, exposed to light using a predetermined standardized mask, and developed. Using this resist film as a mask, the upper metal layer 10A is selectively etched to form a predetermined wiring pattern. In this wiring pattern, a large (for example, about 4 μm in diameter) circular portion is formed concentrically around the contact hole. After removing the resist film, Bustle Laser A
, B (e.g., spot diameter: 4 μm, energy: 2
8.3 μJ) is irradiated concentrically with the contact hole only to the area where contact is required. Therefore, there are many contact holes that are not irradiated with the laser, and those contact holes that are necessary for a predetermined circuit configuration are selectively irradiated.
レーザ照射された上層メタル膜１０Ａおよびメタル部分
１０Ｂが溶解され、上層メタル膜１０Ａのオーバハング
状部分を含めコンタクトホール周囲部分が、第１Ｄ図に
示すように、コンタクトホール内へ流動し、凝固して下
層メタル膜３と上層メタル膜１０Ａとがコンタクト部分
１０Ｃにて接続（導通）される。このようにして、所定
回路が半導体装置製品に応じて形成できる。The upper metal film 10A and metal portion 10B irradiated with the laser are melted, and the surrounding portion of the contact hole, including the overhanging portion of the upper metal film 10A, flows into the contact hole and solidifies, as shown in FIG. 1D. The lower metal film 3 and the upper metal film 10A are connected (conducted) at the contact portion 10C. In this way, a predetermined circuit can be formed depending on the semiconductor device product.
以上説明した様に、本発明によれば、配線形成が規格化
されたマスクを用いかつ配線層間コンタクトが上層配線
の形成後にレーザ照射で回路設計に応じて容易かつ確実
に形成できるので、セミカムタムＩＣ（ゲートアレイ）
の生産期間（納期）を短縮化するに大きく寄与する。As explained above, according to the present invention, wiring formation can be easily and reliably formed using a standardized mask and by laser irradiation after forming the upper layer wiring according to the circuit design. (gate array)
This greatly contributes to shortening the production period (delivery time).
第１Ａ図〜第１Ｄ図は、本発明に係る方法にしたがって
眉間コンタクトを形成する工程を説明する半導体装置の
部分断面図である。
３・・・下層メタル膜、
４・・・下層側絶縁膜、
５・・・上層側絶縁膜、
６・・・レジスト膜、
８・・・コンタクトホール、
１０Ａ・・・上層メタル膜、
Ａ、Ｂ・・・レーザ。
第１Ａ図1A to 1D are partial cross-sectional views of a semiconductor device illustrating the process of forming a glabella contact according to the method according to the present invention. 3... Lower layer metal film, 4... Lower layer side insulating film, 5... Upper layer side insulating film, 6... Resist film, 8... Contact hole, 10A... Upper layer metal film, A, B... Laser. Figure 1A
Claims (1)
間絶縁膜を形成すること及び該層間絶縁膜上に上層配線
を形成することを行い、該コンタクトホールの縁部に該
上層配線の縁部が位置するようにし； コンタクトをとるべきコンタクトホールの縁部に位置す
る該上層配線の縁部に選択的にレーザを照射して前記上
層配線の縁部を溶融し、コンタクトホール内へ流し込む
ことで下層配線と前記上層配線とを選択的に導通するこ
とを特徴とする半導体集積回路装置の製造方法。[Claims] 1. Forming a lower layer wiring on a semiconductor substrate; forming an interlayer insulating film in which a plurality of contact holes are formed on the lower layer wiring; and forming an upper layer wiring on the interlayer insulating film. by selectively irradiating the edge of the upper layer wiring located at the edge of the contact hole where contact is to be made with a laser; A method of manufacturing a semiconductor integrated circuit device, characterized in that the lower layer wiring and the upper layer wiring are selectively electrically connected by melting an edge of the upper layer wiring and pouring the melt into a contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33108789A JPH03192722A (en) | 1989-12-22 | 1989-12-22 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33108789A JPH03192722A (en) | 1989-12-22 | 1989-12-22 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03192722A true JPH03192722A (en) | 1991-08-22 |
Family
ID=18239708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33108789A Pending JPH03192722A (en) | 1989-12-22 | 1989-12-22 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03192722A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH088346A (en) * | 1994-06-16 | 1996-01-12 | Lg Semicon Co Ltd | Programmable semiconductor element having antifuse structureand manufacture thereof |
-
1989
- 1989-12-22 JP JP33108789A patent/JPH03192722A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH088346A (en) * | 1994-06-16 | 1996-01-12 | Lg Semicon Co Ltd | Programmable semiconductor element having antifuse structureand manufacture thereof |
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