JPH0319048A - Processor capable of extension of memory - Google Patents

Abstract

PURPOSE:To accurately designate addresses for prevention of misoperation and at the same time to eliminate the operating complicacy by detecting the connectors connected with memories and selecting the extended memories to successively designate the addresses to these memories. CONSTITUTION:The memories M1 - M3 to be extended are connected to the optional one of connectors CN1 - CN3. The detection means a1, a2 and a3 detect the connectors CN1 - CN3 to which the memories M1 - M3 are extended. Thus a processing means 12 selects the extended memories M1 - M3 to successively designate the addresses to these memories. Then the means 12 performs at least a reading or writing operation to the memories M1 - M3 to give accesses to them and carries out the processing operations. Therefore an address is accurately designated to each memory when the memories M1 - M3 are connected to the optional one of connectors CN1 - CN3. As a result, an accurate address is automatically designated and no malfunction is produced at all.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a processing device with an expandable memory.
The present invention relates to a processing device in which the memory capacity can be increased depending on the purpose used by the user, such as in ion (abbreviated as EWS) and office automation (abbreviated as OA) processors.

Conventional technology A typical prior art is shown in FIG.

The processing device main body 1 is equipped with a processing circuit 2, which outputs an address signal to a memory control circuit 3 via a line 4. A basic memory MIO is connected to this memory control circuit 3 via a line 5. A plurality of connectors CN 11-CN13 are also connected to the processing device 1, and addressing signals are led to the memory control circuit 3 via lines 6.7.8. Connectors CN11 to CN13 have
The memories Mll to M13 to be added are selectively removably connected. Memories MIO to M13 have the same configuration. For the connector/lid CN11 to CNl3,
Memory Mll to M1 in order starting from the lowest number
Install 3. When the memory capacity of the memories M10 to M13 is, for example, 4 megabytes, the memories Mll to M1
By adding 3, the capacity can be increased to a maximum of 16 megabytes. When addresses 0 to 4A-1 shown in Table 1 are derived from processing circuit 2, lines 5 to 8 are given addresses of 4 megabytes each. At this time, A=4 megabytes.

Table 1 In the prior art shown in FIG. 4, the processing circuit 2
The addresses derived from lines 5.6 and 7.8 are fixed as shown in Table 1. Therefore, for example, to add just one memory, the memory M11 must be inserted and connected to the connector CNII, and when using the second memory M12, it must be connected to the connector CN12. Similarly, connector CN
It is necessary to expand the memories by sequentially inserting and connecting the memories Mll to M13 to CN11 to CN13 in this order.

Therefore, in the prior art shown in FIG. 4,
Connect the memory M11 to M13 to connector CNll to be expanded.
- Since they must be inserted and connected to the CN13 in the correct order, errors are likely to occur during shipping or repair service.

Another prior art is shown in No. 5 (21), and corresponding parts are given the same reference numerals. In this prior art, memories Mll to M1 to be added to connectors CN11 to CN13
3 may be inserted and connected in any order, but in order to ensure that the address signal derived from the processing circuit 2 via the line 4 is given to the additional memories Mll to M13 and access is performed. , a switch circuit 9 must be interposed between the memory control circuit 3 and the connectors CN11 to CN13 to change the connections of the switches 9a, 9b, and 9c.

Problems to be Solved by the Invention In the prior art shown in FIG. 5, when adding a total of two memories, Mll and M12,
1. Set the switching states of the switches 9a and 9b of the switch circuit 9, and set the added memory Ml. M
12 must be operated in such a way that it is addressed correctly, therefore, the switch circuit 9 must be operated, and there is a risk of erroneous operation.

An object of the present invention is to provide a processing device capable of expanding memory, which enables accurate address specification when memory is expanded, and enables accurate access to the expanded memory. The goal is to provide the following.

Means for Solving the Problems The present invention includes a plurality of connectors, a detecting means for detecting that memory is connected to each connector and added, and selecting the added memory in response to the output of the detecting means. This is a processing device capable of adding a memory, characterized in that it includes means for performing processing operations by sequentially specifying addresses and performing read/write operations.

Function According to the present invention, the memory to be added is connected to any one of the plurality of connectors. The detection means detects the connector with additional memory, and the processing means thereby
Select the added memory and address it sequentially,
The expanded memory is accessed by reading and/or writing, and processing operations are performed.
Correct addressing is automatically possible since each memory is correctly addressed and used when E is done, thus connecting the memory to any connector.

This prevents malfunctions, and there is no risk of malfunctions occurring, for example, during shipping or collection service.

Practical ItA Example FIG. 1 is a block diagram of one embodiment of the present invention. A processing device 11, for example an EWS and an OA processor, is equipped with a processing circuit 12 realized by a microcomputer or the like, from which addressing signals are derived via a line 13. This processing device 11 is provided with connectors CNI to CN3, and each connector CN
Memories M1 to M3 to be expanded are connected to I to CN3. Each memory M1 to M3 is connected by inserting the required number into any connector CNI to CN3, and the memory that is connected and expanded at this time is connected. M1-M3 are precisely addressed and accessed to perform reads and/or writes to accomplish processing operations. Memory M
1 to M3 have memory elements 15 16 17 realized by semiconductor integrated circuits or the like. In the memory M1, the memory element 15 is provided with an addressing signal via a line b11, is supplied with power via lines dll and ell, and has a grounded line a11. The remaining memory M2. M3 has a similar configuration and is shown in FIG. 1 with reference numerals having corresponding suffixes.

The connector CNI is provided with a line b1 to which an addressing signal is applied, and a line di for power supply.
, el, and a line a1 for detecting whether the memory M1 is connected to the connector CNI.
is provided. These lines bl, di, el, rt
l is the line bll, dll, ell, al of memory M1
can be connected to l. Remaining connector CN2.
CN3 also has a similar structure and has been orally handed down with a corresponding subscript. Line a1 is connected to the positive terminal 20 of DC current R19 via resistor R1, and similarly lines a2 and il3 are connected via resistors R2 and R3. This positive terminal 20 is connected to the line d1d2. d3 respectively. A negative terminal 21 of the DC power supply 19 is grounded. For example, when the memory M1 is connected to the first core and lid CNI and expanded, the line a1 becomes the ground potential, and the memory control circuit 23
Detects that memory Ml is connected to NI. Connection
When memory M2 is not connected to lid CN2,
Line a2 is at a high level due to the action of resistor R2. Further, when the memory M3 is connected to the connector/lid CN3, the line a3 becomes a low level which is the ground potential. In this way, the memory control circuit 23 operates on lines al, a2 . a3
Connector CNI as described above.
It is detected that memories M1 and M3 are connected to CN3. The memory control circuit 23 controls these lines a1 to a3.
in response to the outputs of their connectors C
For the memories M1-M3 connected to NI-CN3 the line l: +1. b2. b3 respectively.

The processing circuit 11 is also provided with a basic memory MO, which has a similar configuration to the memories M1 to M3 described above and has a memory element 24, which is connected via the line bO. Addressed, controlled and powered by power supply 19.

FIG. 2 is a simplified block diagram for explaining the operation of the memory control circuit 23. For example, in this embodiment, the memories M1 and M3 are connected to the connectors CNI and CN3 for expansion, and therefore the logical value rloIJ indicated by the second [2ff diagonal line] is selected. Therefore, regarding the addressing signal applied from the processing circuit 12 via the line 13, when the memory capacity of each of the memories MO to M3 is, for example, A megabyte, when the addressing signal is 0 to A-1, the memory control circuit 23 teeth,
When the addressing signal is applied to the memory MO, and likewise the addressing signal A~2A-1 from line 13, the memory M connected to the connector CNI
1 is specified and the addressing signal on line 13 is 2A to 3A-1, the memory M3 connected to the core/lid CN3 is addressed. Note that when memory M2 is connected to connector CN2,
When addressing signals 2A-3A-1 are applied to line 13, memory M2 is addressed, and when addressing signals 3A-4A-1h' are applied to line 13, memory M3 is addressed.

The operation of the above-mentioned memory control circuit 23 will be further explained with reference to FIG. Moving from Stella 7 n 1 to step port 2, the memory control circuit 23 discriminates the levels of lines a1 to a3 and sets the memory M to the memories CN1 to CN3, for example.
Detects that 1 to M3 are connected. step n
3. n5. As shown by n7゜n9, the memories MO to 4A1 correspond to each A megabyte of address designation signals 0 to 4A1.
M3 is selected. In this embodiment, when it is assumed that the memory M2 is not connected to the connector CN2,
Even when addressing signals 3A-4A-1 are derived from processing circuit 12, no access operation is performed.

Although the memory MO-M3 may be a memory realized by a semiconductor integrated circuit, it may also be a memory having another configuration, such as a floppy disk.

Effects of the Invention As described above, according to the present invention, memory is expanded by connecting it to any one of a plurality of connectors, the connector to which the memory is connected is detected by the detection means, and the expanded memory is expanded. Selective and sequential addressing makes it possible to accurately address memory added to any connector without causing the operational errors mentioned in connection with the prior art mentioned above. Also, the troublesome operation is eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a simplified block diagram for explaining the operation of the memory control circuit 23, and FIG. 3 is a flowchart for explaining the operation of the memory control circuit 23. , FIG. 4 is a block diagram of the prior art,
FIG. 5 is a block diagram of another prior art. 11... Processing device, 12... Processing circuit, one...
DC power supply, 23... memory control circuit, CNI to CN3
...Connector, MO~M3...Memory

Claims (1)

[Claims] A plurality of connectors, a detection means for detecting that memory is connected to each connector and added, and in response to an output of the detection means, selecting and sequentially selecting the added memory. 1. A processing device capable of adding memory, characterized in that it includes means for performing processing operations by specifying an address and performing reading/writing.