JPH03187585A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To obtain the solid state image pickup element of good handlability and high paracticability by simultaneous-integrating a two-dimensional filtering function together with a photoelectric converting part, and obtaining its filtering output at real time. CONSTITUTION:The two-dimensional filtering function is simultaneous-integrated with a solid state image pickup element main body 1, and simultaneously, hori zontal transfer registers 2a to 2n of n-stages are provided, and signal charge is parallel-transferred among these. Accordingly, the desired filtering output can be obtained directly from the solid state image pickup element and in addition at real time, without constructing any exclusive hardware type two-di mensional filtering circuit as a built-on circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device that is equipped with a two-dimensional filter function and can obtain a video signal that has been subjected to filtering processing in real time.

[Prior Art] Recently, various technologies have been developed for capturing and inputting images of subjects using solid-state image sensors such as COD image sensors and MOS image sensors, and various technologies have been realized as video cameras, electronic still cameras, etc. There is.

This type of solid-state image sensor (image sensor) basically has multiple photoelectric conversion sections arranged in a matrix, and each photoelectric conversion section generates and accumulates signal charges according to the amount of incident light. The data are configured to be read out sequentially in time series via a charge transfer unit (transfer register).

However, when handling video signals obtained through such an image sensor, image signal processing includes, for example, two-dimensional filtering processing to extract the edge component of the image by determining the differential value between adjacent pixels, and uneven illumination. Two-dimensional bypass filtering processing is often performed to correct this. This two-dimensional filtering process is basically performed by performing a convolution integral operation between the pixel of interest, a plurality of surrounding pixels, and a predetermined weighting coefficient. In other words, this two-dimensional filtering process conventionally involves storing pixel signals read out in time series from a solid-state image sensor in shift registers for n lines, and delaying the pixel signals obtained from each of these shift registers. This is realized by processing to obtain signals of (nXm) pixels, multiplying each of these signals by a predetermined filter coefficient, and then calculating the sum of the signals.

However, in order to construct such a two-dimensional filtering processing circuit as a dedicated hardware circuit and connect it to the output stage of the solid-state image sensor to obtain the desired filtering output, the configuration of the image processing device must be quite large. It is undeniable that it will happen. Moreover, there is a problem that filtering output cannot be obtained in real time.

[Problems to be Solved by the Invention] Conventionally, when performing two-dimensional filtering processing on a video signal obtained from a solid-state image sensor, a dedicated two-dimensional filtering circuit is used to connect the solid-state image sensor to a video signal obtained from the solid-state image sensor. It is necessary to construct an external circuit as a circuit, and there is a problem in that the configuration of the image processing device becomes quite large-scale, and the filtering output cannot be obtained in real time.

The present invention has been made in consideration of these circumstances, and its purpose is to provide an easy-to-handle device that allows desired filtering output to be obtained directly from a solid-state image sensor in real time. An object of the present invention is to provide a highly practical solid-state imaging device.

[Means for Solving the Problems] The present invention provides an output stage of a solid-state image sensor that transfers signal charges accumulated in the photoelectric conversion units line by line from a plurality of photoelectric conversion units arranged in a matrix in parallel. In addition, an n-stage transfer register is provided to store the signal charges transferred in parallel line by line from the photoelectric conversion unit over n consecutive lines, and to serially transfer and output the signal charges of each line. , a delay means for delay processing the signal charges serially transferred and outputted from these n stages of transfer registers and outputting in parallel signal charges of m consecutive pixels for each line, and n determined by this delay means. This device is characterized by simultaneously integrating a plurality of multipliers that multiply each signal charge of m-stage pixels by a predetermined coefficient, and an adder that calculates the sum of each multiplication value by each of these multipliers.

[Function] According to the present invention, signal charges transferred in parallel line by line from a plurality of charging converters arranged in a matrix are stored over n consecutive lines, and the signal charges of each line are stored. Using n-stage transfer registers that serially transfer and output each signal charge, each of the signal charges of the above n lines is read out in parallel and in time series, and the signal charges of consecutive m pixels in each line are extracted, and these ( It becomes possible to obtain a signal obtained by performing filtering processing in real time using the signal of the nXm) pixel as the output of the solid-state image sensor.

As a result, it becomes possible to obtain the desired filtering output directly from the solid-state image sensor in real time without constructing a dedicated hardware two-dimensional filtering circuit as an external circuit. It becomes possible to sufficiently improve the ease of handling.

[Example] Hereinafter, a solid-state image sensor according to an example of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of a solid-state image sensor according to an embodiment, and l is a main body of the solid-state image sensor. This solid-state image sensor main body has a plurality of photoelectric conversion units 1a each consisting of a photodiode that generates a signal charge according to the amount of incident light, arranged in a matrix as pixels, and a plurality of photoelectric conversion units 1a arranged along each row of these photoelectric conversion units 1a. It has a planar configuration in which vertical transfer registers 1b are arranged in each column, and an element isolation region 1c is formed for each unit in the column direction formed by the photoelectric conversion section 1a and vertical transfer register tb in each column.

The vertical transfer register lb in each column transfers and inputs the signal charge accumulated in each photoelectric converter 1a in parallel under the control of a transfer gate 1d formed between the photoelectric converter 1a and the photoelectric converter 1a. It is driven in response to a vertical transfer lock from a vertical transfer control section, and vertically transfers the parallel input signal charges from each photoelectric conversion section 1a in the vertical direction, here, toward the bottom of the drawing. As a result, from the solid-state image sensor main body l, data is transmitted line by line from the vertical transfer register 1b of each column, that is, from each photoelectric conversion unit 1a of the lowest piece of the plurality of photoelectric conversion units 1a arranged in a matrix. The signal charges are transferred and output in parallel one line at a time starting from the signal charges.

However, signal charges that are transferred and outputted in parallel for one line are input in parallel to the output terminals of each of the vertical transfer registers Ib of the solid-state image sensor body l, and the manually input signal charges are transferred horizontally in the horizontal direction. N-stage (here, three stages) horizontal transfer registers 2a, 2b, and 2c are provided for data transfer.

That is, here, in order to perform two-dimensional filtering processing based on pixel signals in a (3×3) pixel area spanning three pixels in three consecutive lines as illustrated in FIG. In order to store signal charges calculated in parallel for each line over three consecutive lines,
Three stages of horizontal transfer registers 2a, 2b, and 2c are provided. In other words, in this example, the pixel of the g line is set as the pixel of interest, and the surrounding (3X 3) pixels are referred to and 2
In order to perform the dimensional filtering process, the signal charges of the (N-1)th line, the 1gth line, and the (II+1)th line are respectively accumulated over one line.

These horizontal transfer registers 2a, 2b, and 2c are driven in response to a horizontal transfer lock from a horizontal transfer control section (not shown), and transfer signal charges for one line manually applied thereto in a horizontal direction, here in the drawing. Transfer horizontally towards the right side of each. At this time, the horizontal transfer register 2a,
The signal charges outputted from 2b and 2c respectively pass through buffers 3a, 3b and 3c to their tips (
left end side), the horizontal transfer register 2a,
2b, the transfer is controlled cyclically. When the signal charges for one line go around once through the cyclic serial transfer, each horizontal transfer register 2a is synchronized with the parallel output of the signal charges in units of one line from the solid-state image sensor body 1. , 2b, 2c for one line are output in parallel to the next stage.

Due to this output control, the signal charges for one line, for example, the (N+1) line start, accumulated in the horizontal transfer register 2a are transferred in parallel to the horizontal transfer register 2b, and at this time, the g line accumulated in the horizontal transfer register 2b is transferred in parallel. The signal charges for one line are transferred in parallel to the horizontal transfer register 2c. Then, it was accumulated in the horizontal transfer register 2c (
, Q-1), the signal charges for one line are discharged as they are, and the horizontal transfer register 2a is newly filled with (ρ+
2) The signal charges of the line are stored over one line.

As a result, the signal charges stored in each of the horizontal transfer registers 2a, 2b, and 2c over one line are shifted by one line. In this state, each horizontal transfer register 2a, 2b is transferred as described above.

The signal charge from 2C is transferred to the buffer 3 by serial transfer.
They will be read out serially via the terminals a, 3b, and 3c, respectively.

Regarding the horizontal transfer register 2c in the third stage (final stage), after the signal charges input in parallel thereto are serially transferred, there is no need to reuse those signal charges. It is also possible to omit the feedback input of the charge to the leading end side, so that the cyclic transfer operation is not performed there.

Therefore, each of the horizontal transfer registers 2a, 2b, 2c
A first sample-and-hold circuit 4a for sampling and holding the signal charges in synchronization with the serial transfer timing is provided at the signal end where the signal charges are output in series through the buffers 3a, 3b, and 3c.
4b, 4c, second sample-and-hold circuits that sample and hold each of the above-mentioned signal charges after one sample delay 5a, 5b, 5cs; third sample-and-hold circuit that samples and holds each of the above-mentioned signal charges after another two-sample delay; 6a.

6b and 6c are provided respectively. In addition, the above second
The sample-and-hold circuits 5a, 5b, and 5c are each configured of two-stage sample-and-hold circuits that are directly connected via a buffer, and the third sample-and-hold circuits 6a, 6b, and Be are each configured here as Each circuit is composed of three stages of sample and hold circuits that are directly connected via buffers.

In this way, each horizontal transfer register 2a, 2b.

2c, each of which is provided in parallel with the output end of the first to third
Sample and hold circuits 4a, ~4c, 5b, ~[l
a.

In steps 6c to 6c, the signal charges for the three consecutive pixels of each line described above, that is, the signal charges of (3 lines x 3 pixels) are determined in parallel.

These first to third sample and hold circuits 4a,
The multipliers 7a, 7b, and 71 connected to ~4c, 5b, ~Ba, and ~6c, respectively, calculate the values set in the coefficient register 8 for the signal charges of (3 lines x 3 pixels) obtained as described above. The multiplication outputs of these multipliers 7a, 7b, . Note that the filter coefficients set in the coefficient register 8 are preset in advance according to the contents of the two-dimensional filtering process.

Two-dimensional filtering processing for (3×3) pixels is executed here by multiplication processing using such filter coefficients and addition processing of the multiplication results. The output from the adder 9, which is the result of the filtering process, is outputted to the outside via an output buffer 10 as a filtering output of the solid-state image sensor.

In this case, the sampling output of the sample and hold circuit 5b of the front 4 and 2 is output as is through the output buffer 11 as a signal charge of the pixel of interest, that is, a normal signal output from the solid-state image sensor body 1. It has become.

With these two output systems, the raw signal charge (video signal) imaged by the solid-state image sensor body 1 and the above-mentioned two
The dimensional filtered video signals are obtained in synchronization with each other. In other words, a two-dimensional filtered output is determined in real time for the raw video signal.

Thus, according to a solid-state image sensor formed by simultaneously integrating such a circuit function section (two-dimensional filtering function), an image signal that has been subjected to two-dimensional filtering processing as an output of the element can be processed in real time together with the raw image signal. can be obtained.

Moreover, by simply setting filter coefficients according to the filtering specifications in advance in the coefficient register 8, the desired filtering output can be directly obtained as the element output. Therefore, there is no need to take the trouble to implement a two-dimensional filtering circuit in hardware as a part of the image processing device, unlike in the past. Furthermore, it is possible to sufficiently ensure real-time performance of the filtered signal, and it is possible to dramatically improve its usability.

Further, it is relatively easy to simultaneously integrate the above-mentioned two-dimensional filtering function with the solid-state image sensor main body l, considering the current semiconductor manufacturing technology, and the above-mentioned n-stage horizontal transfer registers 2a, to 2n are provided. Since it is relatively easy to transfer signal charges in parallel between these, there are advantages such as the structure of the solid-state imaging device itself does not become very complicated. Therefore, it is possible to greatly simplify the configuration of a video camera or an electronic still camera constructed using this type of solid-state imaging device.

By the way, in the embodiment described above, n stages (three stages) of horizontal transfer registers 2a, 2b, and 2e are provided in parallel, and the signal charges for one line are transferred in parallel between them. n connected in series as illustrated in Figure 3.
It is also possible to implement the horizontal transfer registers 2a, 2b, and 2c in stages (three stages). That is, the signal charges serially output from the first stage horizontal transfer register 2a are directly transferred to the second stage horizontal transfer register 2 via the buffer 3a.
b, and the signal charges serially output from the second-stage horizontal transfer register 2b are input as they are to the third-stage horizontal transfer register 2C via the buffer 3b.

With this configuration, these horizontal transfer registers 2
It is no longer necessary to transfer signal charges for one line in parallel between a, 2b, and 2c, and each horizontal transfer register 2a,
Since there is no need to cyclically transfer signal charges in series in 2b and 2c, the drive system and configuration thereof can be simplified.

Also, at this time, each horizontal transfer register 2a, 2b, 2c
The first to third sample-and-hold circuits for delay processing the signal charges serially transferred and output from the circuit are realized as three-stage sample-and-hold circuits connected in series via buffers, as shown in Figure 3. However, the signal charges held in the sample and hold circuits of each stage may be read out in parallel. In this way, the number of sample and hold circuits required for delay processing can be reduced compared to the configuration shown in the first embodiment described above, and the configuration can be simplified. Even if the configuration is simplified in this way, the same effects as in the previous embodiment can be achieved.

Note that the present invention is not limited to the embodiments described above. In the embodiment, it was explained that two-dimensional filtering processing is performed between signal charges of (3 lines x 3 pixels), but -
When performing two-dimensional filtering processing (n lines x m pixels) for boat fishing, it is sufficient to provide n stages of horizontal transfer registers and m stages of delay means (sampling circuits). Further, regarding filter coefficients for performing two-dimensional filtering processing, if the processing specifications are fixedly determined, it is also possible to set them in advance as ROM data or the like. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As explained above, according to the present invention, the two-dimensional filtering function for performing two-dimensional filtering processing on the signal charge (image signal) read out from the photoelectric conversion unit is simultaneously provided with the photoelectric conversion unit. It has become possible to integrate the filter and obtain its filtering output in real time. Moreover, it is configured to incorporate a two-dimensional filtering function very effectively and obtain a desired filtering output. As a result, it has become possible to significantly simplify the configuration of video cameras and electronic still cameras constructed using this type of solid-state image sensor, and has great practical effects such as simplifying their handling. can be played.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a photoelectric conversion element according to an embodiment of the present invention, FIG. 2 is a diagram showing the concept of a pixel for performing two-dimensional filtering processing, and FIG. 3 is another embodiment of the present invention. FIG. 2 is a schematic configuration diagram of a photoelectric conversion element. 1... Solid-state image sensor body, la... Photoelectric conversion section, 1
b... Vertical transfer register, le... Inter-element isolation region, 1d... Transfer gate, 2a, 2b, 2
c...Horizontal transfer register, 3a, 3b, 3cm・
- Buffers, 4a, ~4c, 5b. ~6a, ~6c... First to third sample hold circuits (delay means) 7a, 7b, ~7I... Multiplier, 8... Filter coefficient register, 9... Adder, 1
0, 11... Output buffer.

Claims (3)

[Claims] (1) The signal charges accumulated in the photoelectric conversion unit are transferred line by line from a plurality of photoelectric conversion units arranged in a matrix in parallel, and the parallel transferred signal charges in units of line are transferred in series. In the solid-state imaging device that reads signal charges from each of the photoelectric conversion elements in time series, the signal charges transferred from the photoelectric conversion unit in parallel in units of lines are stored over n consecutive lines, and the signal charges of each line are stored. There are n stages of transfer registers that serially transfer and output charges, and signal charges that are serially transferred and output from these n stages of transfer registers are delayed to form consecutive m pixel signal charges for each line. a delay means for outputting in parallel, a plurality of multipliers for multiplying each signal charge of n stages and m pixels obtained by the delay means by a predetermined coefficient, and an adder for calculating the sum of the multiplied values by these multipliers. What is claimed is: 1. A solid-state imaging device characterized by simultaneous integration of (2) The n-stage transfer register cyclically serially transfers signal charges for one line input in parallel and outputs the same.
Claim (1) comprising a parallel transfer register for n lines that transfers signal charges for one line to the next stage in parallel in synchronization with readout of signal charges for each line from the photoelectric conversion section. ). (3) Claim (3) characterized in that the n-stage transfer register consists of transfer registers for n lines connected in series.
1) The solid-state imaging device according to item 1).