JPH03187262A - Mask rom and manufacture thereof - Google Patents

Abstract

PURPOSE:To shorten the time taken from writing of information to completion of a mask ROM by providing an island region of a thin film of single crystal semiconductor island region with a MOS transistor on one side and by introducing impurity from the other side to write information. CONSTITUTION:A plurality of gate electrodes 5 are formed in parallel via an insulating film 8 on one main face of a single crystal semiconductor island region 3 consisting of a thin film, and source-drain regions 6a-6g are formed in the single crystal semiconductor island region 3. Impurity is introduced selectively into the channel-forming region of a MOS transistor according to information from the other side of the island region 3, thereby creating enhancement type transistors Q2, Q4, Q7, Q8, T2, and T3 and depletion type MOS transistors Q1, Q3, Q5, Q6, T1, and T4. This introduction of impurity requires no ion implantation for example at high energy because the single crystal semiconductor island region 3 is a thin film. This design can shorten the time taken from writing of information to completion of a mask ROM.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mask ROM employing So+ (silicon on insulator) technology and a method for manufacturing the same.

[Summary of the invention]

The present invention provides a mask ROM in which a memory cell is formed by MOS transistors connected in series, and a method for manufacturing the same, in which the MO3 By providing a transistor and writing information by introducing impurities from the other side of the single crystal semiconductor island region, the accuracy of writing information is improved, and the information is written to easily complete the mask ROM. Time until (TAT: Lu
This aims to shorten the rn around time.

[Conventional technology]

Information is written in the mask ROM during its manufacturing process, and its memory cells are usually configured with MO3FETs. As a type of mask ROM, a NAND type mask ROM is known, which is composed of a plurality of series-connected MOSFET arrays. This NAND type mask ROM
is attracting attention as a ROM that can accommodate larger capacities due to larger integration.

In this NAND type mask ROM, information is normally written by controlling the threshold IT pressure of the MO3FET by ion implantation. However, conventionally (7) NA
Since information is written to ND type mask ROM in the process before and after forming the MOSFET gate insulating film, the time required from writing information to completing the mask ROM (TAT)
The problem was that it was long.

As a countermeasure for this improvement, the technique described in, for example, Japanese Patent Laid-Open No. 60-37767 is known.

According to this technology, a MOSFET is placed on a thin film membrane.
After forming the MOSFET, impurities are introduced into the channel formation region of the MOSFET from the back surface of the membrane plan according to the information to write information, thereby shortening the TAT.

[Problem to be solved by the invention]

As semiconductor devices become more highly integrated, techniques for writing information with high precision are required also in mask ROMs. However, in the technique described above in which ions are implanted from the back side of the membrane plan where the MOSFET is formed, the energy required for ion implantation into the membrane plan is high because it is necessary to implant ions through the membrane plan. Become.

As a result, the precision of ion implantation deteriorates and the dark value voltage varies, so there is a problem that higher precision cannot be achieved.

SUMMARY OF THE INVENTION The present invention has been proposed in view of the conventional situation, and an object of the present invention is to provide a mask ROM that improves the accuracy of information writing and shortens TAT, and a method for manufacturing the same. .

[Means to solve the problem]

A mask ROM and a manufacturing method thereof according to the present invention have been proposed to achieve the above-mentioned objects.

That is, in the present invention, a single crystal semiconductor island region made of a plurality of thin films is formed on a support, and a gate electrode of a MOS transistor connected in series is formed on the surface of the single crystal semiconductor island region on the side of the support. The method is characterized in that information is written by selectively introducing impurities into the single crystal semiconductor island region from the other surface of the single crystal semiconductor island region.

The present invention also includes a step of forming a groove in one main surface of a single crystal semiconductor substrate and forming a polishing stopper in the groove;
forming a plurality of gate electrodes in parallel on the one main surface via an insulating film and forming source/drain regions on the single crystal semiconductor substrate to obtain MOS transistors connected in series; a step of bonding a support to the surface side; a step of polishing the single crystal semiconductor substrate from the other side of the single crystal semiconductor substrate to reduce the thickness of the single crystal semiconductor substrate until the polishing stopper appears; The method is characterized by comprising a step of selectively introducing impurities between the source and drain regions from the other surface side to write information.

[Effect]

In the present invention, a plurality of gate electrodes are formed in parallel on one main surface of a single crystal semiconductor island region made of a thin film with an insulating film interposed therebetween, and source/drain regions are formed in the single crystal semiconductor island region. . This series connected MO5! - The structure is such that the one main surface provided with the transistor is bonded to a support.

Then, from the other surface side of the single crystal semiconductor island region,
Impurities are selectively introduced into the channel forming region of the MO3 transistor according to the information, thereby obtaining enhancement type and daily silane type MOS transistors. In introducing this impurity, since the single crystal semiconductor island region is a thin film, it is not necessary to perform ion implantation with high energy, for example.

Therefore, it is possible to write information with high precision.

Furthermore, in the mask ROM manufacturing method of the present invention, a groove in which a polishing stopper is embedded is formed in one main surface of the single crystal semiconductor substrate. After bonding this one main surface side to a support, the single crystal semiconductor substrate is polished until the polishing stopper appears from the other surface. Since the polishing stopper is provided, it is easy to detect the end point of polishing, and the single crystal semiconductor substrate is formed into an I film to a required thickness. Also,
Since the surface to which the support is bonded is the side on which the gate electrode of the single-crystal semiconductor substrate is formed, the single-crystal semiconductor substrate is reliably made into a thin film by polishing. Next, in accordance with the information, impurities are introduced into the channel forming region of the MO3 transistor from the other side of the single crystal semiconductor substrate to write information. At this time, the impurities are inserted into the thinned single crystal semiconductor substrate. Since the ions are introduced into the substrate, the energy required for ion implantation is small; therefore,
The accuracy of ion implantation is improved. Further, since the information is written after the MOS transistors have been formed in advance as described above, the TAT can be shortened.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment This embodiment is an example of a NAND type mask ROM, in which a silicon base l as a support is bonded to the bottom of a single crystal semiconductor base, and the gate electrode of a MOS transistor of a memory cell is attached to the silicon base. This is an example of a mask ROM having a structure located between a base 1 and a single crystal semiconductor substrate, and in which information is written from the surface opposite to the support.

First, the structure of the mask ROM of this embodiment will be explained with reference to FIGS. 1 to 3.

On a silicon base l serving as a support, there is a single crystal semiconductor substrate on which MOS transistors connected in series via a flattening film 91 and an interlayer insulating film 8 are formed. This single-crystal semiconductor substrate is formed by polishing a silicon substrate as described later, and consists of a selectively oxidized Jll SI region 2 for an element and an island region 3 surrounded by a III 8N region 2 for the element. ing. A plurality of gate electrodes 5 are formed in parallel under this island region 3 with a gate oxide film 4 interposed therebetween. This gate electrode 5 connects word lines WL, ~WL, which extend substantially parallel to each other in the Y direction at predetermined intervals, and these word lines WL1.
~WLa Selection line SL provided approximately parallel to a, ~SL
, functions as. In the island region 3 between adjacent gate electrodes 5, n0 type impurity regions 68 to 6g functioning as source/drain regions are formed. This impurity region 6a
6g are arranged in the X direction perpendicular to the gate electrode 5. As a result, one series-connected MOSFET string is formed by nMOS transistors Ql~Q4 and T + ~Tt, and nMOS transistors Q, ~Q- and T, ~
Another series-connected MOSFET string is formed at T4.

A ground voltage is supplied to the impurity region 6a, and the impurity region 6g is connected to a wiring layer 7 to be described later through a contact portion IO. Further, an n'''' type impurity such as phosphorus is selectively introduced into the channel forming region of the island region 3. nMOS transistors Q, , Qco, Qs, Qh with channels introduced with this impurity
, T+, and Ta are of the daily silane type (normally-on type), and no impurities are introduced between the source and drain regions and the nMOSM remains a p-type single crystal silicon layer.
OS transistor Qg4. Q,,Qs,Ta,T,
is an enhancement type (normally-off type). In particular, in this embodiment, impurity ions are implanted into the island region 3 at the surface of the single crystal semiconductor substrate opposite to the side where the gate electrode 5 is formed. It is done from the side. Therefore, the energy of ion implantation can be reduced, and the accuracy of information writing can be improved. Further, the ion implantation is performed after the wiring layer 7 is formed. Therefore, TAT can be significantly shortened.

A glabellar insulating film 8 is formed in the lower layer of one surface of the island region 3 in which such a memory cell is provided.

The glabellar insulating film 8 covers the silicon base 1 side of the gate electrode 5. Then, a wiring layer 7 is formed under the interlayer insulating film 8. The wiring layer 7 has a pattern extending in the X direction that is substantially orthogonal to the direction of extension of the gate electrode 5, and is connected to one series-connected MOSFET column consisting of nMOS transistors Q, ~Q4 and T, ~T2, and the nMOS transistors.
It overlaps with the element isolation region 2 that isolates the other series-connected MOSFET string composed of the transistors Qs-Q and T, -T4. This wiring layer 7 is connected to the impurity region 6g through a contact portion 10 which is an opening in the glabella insulation film 8. A flattening film 9 that flattens the lower surface of the wiring layer 7 is used to form the wiring layer 7 and the eyebrow insulation W! It is formed in the lower layer of B. This flattening film 9 is
This is a film for bonding a single crystal semiconductor substrate on which a MOS transistor array is formed to a silicon base 1, and has a structure in which the lower surface of this flattening film 9 and one surface of the silicon base 1 are bonded. . On the other hand, a silicon oxide film 11 is formed on the other surface of the island-like region 3, and the silicon oxide film 11
A silicon nitride film 12 is laminated thereon. These silicon oxide film 11 and silicon nitride film 12 function as a protective film.

In the mask ROM of this embodiment having such a structure, information can be written after the gate electrodes and bit lines are formed, and the TAT can be shortened. Further, the writing is performed on the thin single crystal island region 3, and since the energy of the ion implantation is low, it is possible to write information with high precision. Further, since each MO3 transistor constituting the memory cell has a Sol structure, the junction capacitance is significantly reduced, and the operating speed can be increased.

Next, a method of reading information from the mask ROM of this embodiment will be explained.

FIG. 4 is an equivalent circuit diagram of a mask ROM having the above-described structure. ,~T,
Select columns.

At the same time, the word line WL is set to L'' level (low level), and the other words MWL, , WL,.

WL is set to "H" level. At that time, information of the MOS transistor Q is read from the current flowing from the bit line.

Furthermore, a method of manufacturing the mask ROM of this embodiment will be explained.

First, as shown in FIG. 5(a), one main surface 21a of the silicon substrate 21 is selectively etched to form a groove 22 in the element isolation region. After forming a silicon oxide film 23 having a thickness at least as deep as the trench on the entire surface including the inside of the trench 22, the entire surface is etched back.As a result, the silicon oxide film 23 is buried in the trench 22. It will be done. This silicon oxide M23 functions as a polishing stopper in a polishing process to be described later, and at the same time functions as an element bone # region. Note that the element bone a region can also be formed separately from the polishing stopper by selective oxidation or the like. Subsequently, a gate oxide film 25 is formed on the island region 24 surrounded by the trench 22.
A layer 26 of gate electrode material such as polysilicon is deposited through the gate electrode and patterned to obtain a word line of a predetermined shape. Since the trench 22 is already filled with the silicon oxide film 23, the gate electrode material layer 26 does not remain in the trench 22.The patterning is performed in the memory cell portion as shown in FIG. It consists of a plurality of parallel strip patterns. Using this gate electrode material layer 26 as a mask, ions of n-type impurities such as phosphorus are implanted,
An impurity region 27 is formed on the surface of the island region 24 using a self-alignment line.

This impurity region 27 functions as a source/drain region, and the nMOS transistor formed on the island region 24 is used as a memory cell. Further, memory cells adjacent in the longitudinal direction of the word line are separated from each other by a silicon oxide film 23 in the trench 22. And gate electrode material layer 2
An interlayer insulating film is formed on the entire surface including layer 6 by CVD or the like. As this interlayer insulating film 28, for example, a PSG film, a BPSG film, etc. can be used. This interlayer insulating film 28
After forming, a contact hole is opened in the glabellar insulating film 28, and a wiring layer that will become a bit line (not shown) is formed on the glabellar insulating film 28.

Subsequently, after flattening the surface by forming a flattening film 29 on the entire surface, as shown in FIG. Compare with 30.

Then, polishing is performed until the silicon oxide film 23 appears from the back surface 2 l bm of the silicon substrate 21 .

Since this silicon oxide film 23 functions as a polishing stopper, the silicon substrate 21 can be thinned to a predetermined thickness. As a result, as shown in FIG. 5(C),
The silicon substrate 21 is thinned to have a Sol structure in which the bottom of the impurity region 27 is exposed.

When the silicon substrate 21 is polished as shown in step 2 and the island-like region 24 where a channel will be formed is formed facing the surface on the gate electrode material layer 26, it enters a standby state waiting for information to be written. Note that a protective film such as a silicon oxide film or a silicon nitride film may be formed on the surface side of the island region 24 at this stage.

Subsequently, as shown in FIG. 5(d), the silicon substrate 21
After applying the resist 1!131 on the back surface 21b of the resist film 31, the resist film 31 is exposed and developed according to the program information. For example, an impurity such as phosphorus is introduced. As a result, an n-type impurity region 3 is selectively formed in the channel forming region of the MO3 transistor.
2 is formed. By such ion implantation, the above M
The threshold voltage of the OS transistor is controlled, a daily silane type MOS transistor and an enhancement type MOS transistor are formed, and information is written. At this time, impurities are only introduced into the thinned silicon substrate 2I, and the energy required for ion implantation is low, thus improving the accuracy of ion implantation.

After removing the above-mentioned resist) H31, as shown in FIG. 5(e), silicon oxide M33 is formed on the back surface 21b of the silicon substrate 21, and this silicon oxide 1! A silicon nitride film 34 is deposited on the silicon nitride film 34 by plasma CVD or the like on the mask ROM of this embodiment.

As described above, in the mask ROM of this embodiment, after completing the wiring formation in advance, the silicon substrate 21 is polished to become a thin film. Therefore, information can be written from the back surface 21b side of the polished silicon substrate 21, the energy of ion implantation can be lowered, and the TAT can be significantly shortened. Also, each MO3 transistor has S
o Since it is a II structure, it is possible to reduce the junction capacitance.

Second Embodiment This embodiment is a modification of the first embodiment, in which a silicon base and an nM transistor are connected in series to one main surface.

This example has a Sol structure in which an S transistor is provided and bonded to a single-crystal silicon substrate, and a wiring layer that becomes a bit line is provided on the other main surface side of the single-crystal silicon substrate.

First, the structure of the mask ROM of this embodiment will be explained with reference to FIGS. 6 and 7.

On the silicon base 51 as a support, there is a flattened layer H59.
, a single-crystal semiconductor substrate on which MOS transistors connected in series via a glabellar insulating film 5B are formed. This single-crystal semiconductor substrate is formed by polishing a silicon substrate as described later, and selectively oxidized element portion III 6N region 5.
2 and an island region 53 surrounded by an If tiJl region 52 corresponding to the element.

Gate oxidation I! on the lower part of one side of this island-like wI region 53
A plurality of gate electrodes 55 extend parallel to each other in the Y direction via I54. These gate electrodes 55 function as word lines and selection lines. In the island region 53 between adjacent gate electrodes 55, there is an n
2-type impurity regions 56a to 56g are formed. The impurity regions 56a to 56g are arranged in the X direction orthogonal to the direction in which the gate electrode 55 extends. As a result, *! is separated by the element MwI region 52. IIIt
A MOS transistor row is formed by connecting a plurality of nMO5 transistors in series in each case. A ground voltage is supplied to the impurity region 56a, and the impurity region 56g
Then, via the contact portion 60, it is connected to the aluminum wiring layer 57 formed in the other island-like region.

Also, based on the program information, the depletion type (
Impurities such as phosphorus are selectively ion-implanted into the channel type Fs and s1 regions of the MOS transistor (normally-on type). On the other hand, a MOS transistor in which no impurity is introduced into the channel forming region is considered to be an enhancement type (normally-off type). In particular, in this embodiment, the impurity introduced into the island-like @II region 53 is not introduced into the gate electrode or Since this is performed after forming the source/drain regions, the TAT can be shortened. In addition, since the ion implantation for introducing the impurity region is performed from the other surface of the island region 53, which is the surface opposite to the silicon base 51, the energy is low, and therefore the precision in forming the impurity region is improved. It gets expensive.

A glabellar insulating film 58 is formed in the lower layer of one surface of the island region 53 in which such a memory cell is provided, and the gate electrode 55 is embedded in the interlayer insulating film 58. Then, a flattening film 59 for flattening the lower surface of the glabellar insulating film 58 is formed under the glabellar insulating film 195B. The structure is such that the plane of this flattening film 59 and one side of the silicon base 51 are bonded together.

On the other hand, on the other surface of the island region 53, a silicon oxide Wj461 having an opening above the impurity region 56g is formed.
An aluminum wiring layer 57 functioning as a bit line is formed on the silicon oxide film 61. The pattern of the aluminum wiring layer 57 extends in the X direction, which is substantially perpendicular to the extending direction of the gate electrode 55, and forms a planar pattern with the element bone II 911 region 52 separating adjacent memory cells. This aluminum wiring layer 57 is connected to the impurity region 56g at a contact portion 60 facing the opening of the silicon oxide film 61. As a protective film, a silicon oxide film 62. silicon nitride film 63
are layered.

The mask ROM of this embodiment having such a structure is different from that of the first embodiment in that the mask ROM of this embodiment has an aluminum wiring layer 5 serving as a bit line.
A monocrystalline silicon layer 7 is formed by ion implantation for programming an island region. For this reason, an aluminum wiring material can be used as the bit line wiring layer, and since the surface on which the aluminum wiring layer 57 is formed is a polished surface, it is advantageous in terms of step coverage. Also, similar to the first embodiment, TA
It is possible to shorten T, and because it has a Sol structure, junction capacitance can be reduced and high-speed operation can be achieved.
Furthermore, highly accurate writing becomes possible in response to higher integration. Note that the aluminum wiring layer 57 may be formed before or after ion implantation for writing information.

〔Effect of the invention〕

As described above, the mask ROM of the present invention can significantly shorten the TAT by forming the memory cells and forming the wiring in advance and manufacturing the mask ROM to a near-complete state. Further, in the present invention, ion implantation is performed from the back surface of the thin film single crystal semiconductor substrate on the upper part of the support using the Sol bonding technique. Therefore, since the energy required for ion implantation is low, the precision of ion implantation is improved and a highly reliable mask ROM can be obtained. Furthermore, the Sol structure significantly reduces junction capacitance, allowing high-speed operation and significantly suppressing a drop in bit line potential.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the structure of an example of a mask ROM of the present invention, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line ■-■ in FIG. FIG. 4 is an equivalent circuit diagram of the memory cell portion of the above example, and FIGS.
Figure (e) is a process sectional view for explaining the manufacturing method of the above-mentioned example according to the manufacturing process order. FIG. 6 is a plan view showing the structure of another example of the mask ROM of the present invention, and FIG.
The figure is a sectional view taken along the line ■-■ in FIG. 6. 1.30.51...Silicon base 2.52...Element isolation region 3.24.53...Island region 5.55...Gate electrode 26...Gate electrode material layers 6a to 6g , 27.56a to 56g・Region 7...Wiring layer 57...Aluminum wiring layer 8.28.58...Interlayer insulating film 9.29.59...Planarization film/Impurity 21...Silicon Substrate 22... Groove 32... Impurity region

Claims (2)

[Claims] (1) A single crystal semiconductor island region made of a plurality of thin films is formed on a support, a gate electrode of a MOS transistor connected in series is formed on a surface of the single crystal semiconductor island region on the support side, and A mask ROM characterized in that information is written by selectively introducing impurities into the single crystal semiconductor island region from the other side of the single crystal semiconductor island region.
. (2) Forming a groove on one main surface of the single crystal semiconductor substrate,
A step of forming a polishing stopper in the groove, and forming a plurality of gate electrodes in parallel on the one main surface with an insulating film interposed therebetween, and forming source/drain regions on the single crystal semiconductor substrate and connecting them in series. a step of bonding a support to the one main surface side; and a step of polishing the single crystal semiconductor substrate from the other surface of the single crystal semiconductor substrate until the polishing stopper appears. Manufacture of a mask ROM characterized by comprising a step of thinning a single crystal semiconductor substrate, and a step of selectively introducing impurities between the source and drain regions from the other surface side to write information. Method.