JP2008034576A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with which a memory cell using a thyristor can be obtained without a need of a special process while an inexpensive bulk semiconductor substrate is used. <P>SOLUTION: The semiconductor device 1a is provided with a DRAM cell with a thyristor structure, which has an n-type cathode n(K) arranged on a surface side of a p-type semiconductor substrate 100, a p-type base p(B) disposed in a surface layer of the n-type cathode n(K), an n-type base n(B) and a p-anode p(A) which are sequentially arranged on the base and a gate electrode G arranged on the p-type base p(B). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a memory cell is configured using a thyristor.

  In recent years, memory cells such as DRAMs and SRAMs using a thyristor have been proposed. In these memory cells, the memory operation is performed with the thyristor in the off state of “0” and the on state of “1”.

  Among these, in the case of DRAM, one memory cell is constituted by one fine thyristor. FIG. 13 (1) shows a cross-sectional view of a DRAM cell using a thyristor, and FIG. 13 (2) shows an equivalent circuit of a semiconductor device using this DRAM cell. This DRAM cell is configured using an SOI substrate, and is realized by a PNPN junction formed in a semiconductor thin film 602 on an insulating substrate 601. The gate electrode G is. The MOS structure is arranged on the P-type base p (B) of the thyristor via the insulating film 603. On the side wall of the gate electrode G, a side wall 604 and a mask pattern 605 for separately forming each layer are provided. In the above configuration, the N-type cathode n (K) is connected to the first word line WL1, the p-type anode p (A) is connected to the bit line BL, and the gate electrode G is connected to the second word line (write enable line) WL2. ,It is connected.

  FIG. 14 (1) shows characteristics at the time of data holding and data reading in the DRAM cell having the above-described configuration. The bit line BL is set to a high potential (Vdd) with respect to the word line WL1, the high resistance state of the thyristor is set to “0” in the memory, and the current value Ioff or Iread (D0) holds the data “0” or Read. The low resistance state is set to “1” in the memory, and data “1” is held or read by the current value Ion or Iread (D1) at that time.

  FIG. 14 (2) shows the characteristics when data “1” is written. A write voltage is applied to the word line WL2, the potential of the bit line BL is set to a high potential (Vdd) and the thyristor is in a low resistance state, and data “1” is written to the word line WL1. FIG. 14 (3) shows the characteristics when data “0” is written. A write voltage is applied to the word line WL2, the potential of the bit line BL is set low with respect to the word line WL1, the thyristor is set in a low resistance state, and data “0” is written. (See Non-Patent Document 1 below).

  In the SRAM, one memory cell is composed of one fine thyristor and one access transistor. For this reason, the memory cell becomes smaller than a DRAM composed of one transistor and one capacitor and an SRAM composed of six transistors.

  FIG. 15A shows a cross-sectional structure of an SRAM cell using a thyristor. This SRAM cell is formed on the surface side of the bulk semiconductor substrate 701. In particular, the thyristor 702 has a configuration in which PNPN junctions are sequentially arranged in the height direction at a portion where the surface layer of the semiconductor substrate 701 is processed into a convex shape. The gate electrode G is disposed so as to face the convex side wall obtained by processing the semiconductor substrate so as to surround the P-type base p (B) of the thyristor 702. The N-type cathode n (K) of the thyristor 702 is connected to one of the source n (s) / drain n (d) of the access transistor (n-channel MOS transistor) Tr.

FIG. 15B shows an equivalent circuit of a semiconductor device using the SRAM cell. The gate electrode Gt of the access transistor Tr is connected to the first word line WL1, and the gate electrode G of the thyristor 702 is connected to the second word line WL2. One N-type diffusion layer (for example, source n (s)) of the access transistor Tr is connected to the bit line BL, and the other N-type diffusion layer (for example, drain n (d)) is the N-type cathode of the thyristor 702. n (K). The P-type anode p (A) layer of the thyristor 702 is connected to the reference potential (V _REF ).

FIG. 16A shows characteristics at the time of data retention in the DRAM cell having the above configuration. The bit line BL is set to a low potential with respect to the reference potential (V _REF ), the intersection between the high resistance characteristic of the thyristor and the access transistor characteristic is “0” of the memory, and the intersection of the low resistance characteristic of the thyristor and the access transistor characteristic is Data is held as “1” in the memory.

FIG. 16 (2) shows characteristics at the time of data reading. A read voltage is applied to the word line WL1 to bring the access transistor into a low resistance state. The bit line BL is applied to a low potential with respect to the reference potential (V _REF ), the current at the intersection of the high resistance characteristics of the thyristor and the access transistor characteristics is read out data “0”, the low resistance characteristics of the thyristor and the access Data is read using the current at the intersection of the transistor characteristics as the read current for data “1”.

FIG. 17A shows the characteristics when data “1” is written in the DRAM cell having the above configuration. A write voltage is applied to the word lines WL1 and WL2, the bit line BL is set at a low potential with respect to the reference potential (V _REF ), the thyristor is set in a low resistance state, and data “1” is written.

FIG. 17B shows the characteristics when data “0” is written. A write voltage is applied to the word lines WL1 and WL2, the potential of the bit line BL is set to a high potential with respect to the reference potential (V _REF ), the thyristor is set in a low resistance state, and data “0” is written (the following Patent Document 2).

  As another SRAM, a configuration using an SOI substrate as shown in FIG. 18 has been proposed. In this case, the SRAM cell is formed by the access transistor Tr formed using the semiconductor thin film 602 together with the thyristor 600 formed on the semiconductor thin film 602 on the insulating substrate 601 with the same configuration as the DRAM cell shown in FIG. Can be configured. The N-type cathode n (K) of the thyristor 600 and one of the source n (s) / drain n (d) of the access transistor (n-channel MOS transistor) Tr share the same region (the following non-patent document) Reference 3).

"Technical Digest IEDM 2005", (USA), 2005, p.321-324. "Technical Digest IEDM 1999" (USA), 1999, p.283-286 "Technical Digest IEDM 2004", (USA), 2004, p.273-276.

  However, the memory cell configuration using the thyristor configured as described above has the following problems. That is, in the configuration using the SOI substrate as shown in FIG. 13 or FIG. 18, the SOI substrate is expensive, and the bulk semiconductor substrate that is widely used cannot be used as a mixed memory. is there.

  On the other hand, in the configuration using the bulk semiconductor substrate as shown in FIG. 15, there is a problem that a special process different from the normal semiconductor process is required in forming the gate electrode surrounding the p-type base of the thyristor. .

  Therefore, an object of the present invention is to provide a semiconductor device that can obtain a memory cell using a thyristor without using a special process while using an inexpensive bulk semiconductor substrate.

  In order to achieve such an object, a semiconductor device according to the present invention includes a first conductivity type region, a second conductivity type base region, a first conductivity type base region, and a second conductivity type region in this order. Provided with a semiconductor region. In addition, a gate electrode provided in the base region of the second conductivity type is provided. In such a configuration, in particular, the second conductivity type base region is composed of a diffusion layer provided in the surface layer portion of the first conductivity type region. The first conductivity type base region and the second conductivity type region are provided on the surface side of the second conductivity type base region. Further, it is assumed that the gate electrode is provided above the base region of the second conductivity type.

  In the semiconductor device having such a configuration, a second conductivity type base region made of a diffusion layer is provided in the surface layer portion of the first conductivity type region, and a gate electrode is provided on the surface of the second conductivity type base region. It is a configuration. Therefore, the gate electrode can be processed and formed above the base region of the second conductivity type. At the same time, since the second conductivity type base region is provided in the surface layer portion of the first conductivity type region, and another region is sequentially provided on the surface side, and is electrically separated, the bulk semiconductor substrate It can be formed on the surface side.

  As described above, according to the semiconductor device of the present invention, the first conductive type region, the second conductive type base region, and the first conductive type are used without using a cheap bulk semiconductor substrate and requiring a special process. It is possible to obtain a semiconductor device having a configuration using a thyristor formed by sequentially joining a base region and a second conductivity type region.

  Hereinafter, embodiments of a semiconductor device of the present invention will be described in detail with reference to the drawings. In each of the following embodiments, the first conductivity type is p-type and the second conductivity type is n-type. However, the opposite may be used. In this case, the p-type and n-type in the following description are used. Replace the mold.

<< First Embodiment >>
<Configuration of semiconductor device>
FIG. 1 is a configuration diagram showing an outline of the semiconductor device of the first embodiment. A semiconductor device 1a shown in this figure has a thyristor-type DRAM cell provided on the surface side of a p-type semiconductor substrate 100. FIG.

  In the semiconductor substrate 100, an n-type well layer 101 is provided at a predetermined depth, and a p-well layer 102 is provided on a surface layer separated by the n-type well layer 101. The surface side of the p-well layer 102 is STI (shallow trench). Each element region is separated by element isolation 103 consisting of isolation.

  In the region of the surface layer isolated by the element isolation 103, an n-type cathode region (hereinafter referred to as an n-type cathode) n (K) is provided over the entire surface of the isolated region. A p-type base region (hereinafter referred to as a p-type base) p (B) is provided in the surface layer portion of the n-type cathode n (K). The p-type base p (B) includes a diffusion layer, is surrounded by an n-type cathode n (K) and an element isolation 103, and is separated into islands. It is in a floating state.

  An n-type base region (hereinafter referred to as an n-type base) n (B) is provided on the p-type base p (B). The n-type base n (B) is selectively epitaxially grown on a part of the p-type base p (B), and is electrically separated from the n-type cathode n (K). . Furthermore, a p-type anode region (hereinafter referred to as a p-type anode) p (A) is provided on the n-type base n (B). The p-type anode p (A) is selectively epitaxially grown on the n-type base n (B), and is electrically separated from the p-type base p (B) and the n-type cathode n (K). Yes.

  As described above, the n-type cathode n (K), the p-type base p (B), the n-type base n (B), and the p-type anode p (A) are provided in this order to form a thyristor. It has become.

  A gate electrode G having a MOS structure is wired on the p-type base p (B), and an insulating side wall 107 is provided on the side wall thereof. The side wall 107 separates and electrically insulates the gate electrode G-n type cathode n (K) from the gate electrode G-n type base n (B) and the p-type anode p (A). Are separated and electrically insulated. Although the case where the gate electrode G has a MOS structure is illustrated here, the gate electrode G may be formed by diffusion bonding of a metal material to the semiconductor substrate 100.

  Further, the n-type cathode n (K) and the p-type anode p (A) are connected to electrodes.

  The semiconductor device 1a is operated in the same manner as the DRAM cell described in the prior art.

<Method for Manufacturing Semiconductor Device>
A method for manufacturing the semiconductor device 1a according to the first embodiment will be described with reference to the manufacturing process diagrams of FIGS.

  First, as shown in FIG. 2A, a semiconductor substrate 100 made of p-type silicon is prepared, and an n-well layer 101 is formed at a predetermined depth of the semiconductor substrate 100 by applying an ion implantation method. Next, a p-well layer 102 is formed on the n-well layer 101 by ion implantation as necessary.

  Next, an element isolation 103 made of STI is formed on the surface side of the semiconductor substrate 100 to isolate each element region. Further, the surface of the semiconductor substrate 100 is covered with a protective insulating film 104.

  Next, as shown in FIG. 2B, for example, by introducing impurities using an ion implantation method, the depth is separated by the element isolation 103 at a position in the p-well layer 102 that is shallower than the n-well layer 101. N-type cathode n (K) is formed.

  Next, as shown in FIG. 2 (3), a p-type base that reaches from the surface of the semiconductor substrate 100 to a depth position where it is joined to the n-type cathode n (K), for example, by introducing impurities using an ion implantation method. p (B) is formed.

  Next, as shown in FIG. 2 (4), a polysilicon electrode film 106 is formed through the gate insulating film 105 so as to cross over the central portion of the p-type base p (B), and these are patterned. Thus, a gate electrode G having a MOS structure is formed. Thereafter, insulating side walls 107 are formed on these side walls. Note that the gate insulating film 105 is formed after the protective insulating film 104 is removed.

  Next, as shown in FIG. 3A, a mask pattern 201 having a shape covering the p-type base p (B) exposed on one side of the gate electrode G is formed. Next, an n-type layer reaching the n-type cathode n (K) from the surface of the semiconductor substrate 100 is formed by ion implantation from the mask pattern 201, the gate electrode G, and the sidewall 107, and this n-type layer is formed. The layer portion is taken as a portion for taking out the n-type cathode n (K). Note that the mask pattern 201 is removed after the ion implantation.

Next, as shown in FIG. 3B, a protective film 202 having a shape that covers the exposed surface of the n-type cathode n (K) and the gate electrode G and exposes the p-type base p (B) is formed. This protective film 202 serves as a mask for epitaxial growth performed in the next step, and is made of silicon oxide (SiO ₂ ) or silicon nitride (SiN).

  Next, as shown in FIG. 3 (3), an n-type silicon layer is grown on the exposed surface of the semiconductor substrate 100, that is, on the p-type base p (B) by a selective epitaxial growth method. Let base n (B).

  Subsequently, as shown in FIG. 3 (4), a p-type silicon layer is grown on the n-type base n (B) by selective epitaxial growth, and this grown layer is used as a p-type anode p (A).

  After the above, the protective film 202 used as a mask at the time of selective epitaxial growth is removed, and the upper portion of the semiconductor substrate 100 is covered with an interlayer insulating film not shown here. Then, connection holes reaching the n-type cathode n (K), the gate electrode G, and the p-type anode p (A) are formed in the interlayer insulating film, and the n-type cathode n (K), gate electrode are formed through these connection holes. The wiring connected to G and the p-type anode p (A) is formed to complete the semiconductor device 1a shown in FIG.

  In the semiconductor device 1a of FIG. 1 obtained as described above, the p-type base p (B) made of a diffusion layer is provided on the surface layer portion of the n-type cathode n (K), and the gate electrode G is provided thereon. This is a configuration provided. Therefore, the gate electrode G can be processed and formed above the p-type base p (B). Also, a vertical structure in which a p-type base p (B) is provided on the surface layer portion of the n-type cathode n (K), and an n-type base n (B) and a p-type anode p (A) are sequentially provided thereon. Therefore, each layer can be formed on the surface side of the bulk semiconductor substrate 100 in a state of being electrically separated.

  From the above, a semiconductor device (DRAM cell) 1a using a thyristor can be obtained using an inexpensive bulk semiconductor substrate 100 and without requiring a special process.

  In particular, in the configuration of the first embodiment, the p-type base p (B) and the p-type anode p (A) are formed above the semiconductor substrate 100 by a selective epi growth technique. For this reason, although it is a vertical type using the bulk semiconductor substrate 100, the diffusion layer by impurity introduction like ion implantation is only two layers of the n-type cathode n (K) and the p-type base p (B). . Therefore, compared with the case where all of the four layers are diffusion layers formed in the adjacent region, the process margin is increased, and thus the fabrication becomes easy.

  Furthermore, since the n-well layer 101 formed at a deep position is separated from the DRAM portion having the thyristor structure by the p-well layer 102, current flows through the n-well layer 101 in the turn-on state of the thyristor. Can be prevented.

<< Second Embodiment >>
<Configuration of semiconductor device>
FIG. 4 is a configuration diagram showing an outline of the semiconductor device 1b of the second embodiment. The semiconductor device 1b shown in this figure is different from the semiconductor device 1a of the first embodiment shown in FIG. 1 in that the n-type base n (B) is formed of a diffusion layer. Is the same as in the first embodiment.

  That is, the n-type base n (B) is provided as a diffusion layer on the surface layer portion of the p-type base p (B), and is arranged in a state of being electrically separated from the n-type cathode n (K) and the gate electrode G. Has been. The p-type anode p (A) is provided as a layer that is selectively epitaxially grown on the exposed surface of the n-type base n (B), as in the first embodiment.

  The semiconductor device 1b is also operated in the same manner as the DRAM cell described in the prior art.

<Method for Manufacturing Semiconductor Device>
The manufacturing method of the semiconductor device 1b according to the second embodiment is the same as the manufacturing method according to the first embodiment except that the n-type base n (B) is formed by epitaxial growth in the process described with reference to FIG. The n-type base n (B) may be formed by introducing p-type impurities into the surface layer of the p-type base p (B).

  At this time, it is important to introduce impurities so that the n-type base n (B) is shallower than the p-type base p (B).

  Even in the semiconductor device 1b of the second embodiment obtained as described above, the p-type base p (B) made of a diffusion layer is provided on the surface layer portion of the n-type cathode n (K), and the upper part thereof Is provided with a gate electrode G. Therefore, as in the first embodiment, a semiconductor device (DRAM cell) 1b using a thyristor can be obtained using an inexpensive bulk semiconductor substrate 100 and without requiring a special process.

  In particular, in the configuration of the second embodiment, the p-type anode p (A) is formed above the semiconductor substrate 100 by a selective epi growth technique. For this reason, although it is a vertical type using the bulk semiconductor substrate 100, the diffusion layer by introducing impurities such as ion implantation has n-type cathode n (K), p-type base p (B), and n-type base n (B ) And only three layers. Therefore, compared with the case where all of the four layers are diffusion layers formed in the adjacent region, the process margin is increased, and thus the fabrication is easy.

  Furthermore, since the n-well layer 101 formed at a deep position is separated from the DRAM portion having the thyristor structure by the p-well layer 102, current flows through the n-well layer 101 in the turn-on state of the thyristor. Can be prevented.

<< Third Embodiment >>
<Configuration of semiconductor device>
FIG. 5 is a configuration diagram illustrating an outline of a semiconductor device 1c according to the third embodiment. The semiconductor device 1c shown in this figure is different from the semiconductor device 1b of the second embodiment shown in FIG. 4 in that the p-type anode (A) is composed of a diffusion layer together with the n-type base n (B). However, other configurations are the same as those of the second embodiment.

  That is, the n-type base n (B) is provided as a diffusion layer on the surface layer portion of the p-type base p (B) and is electrically separated from the n-type cathode n (K) and the gate electrode G. Is provided. Further, the p-type anode p (A) is provided as a diffusion layer on the surface layer portion of the n-type base n (B) and is electrically separated from the p-type base p (B) and the gate electrode G. Is provided.

  The semiconductor device 1c is also operated in the same manner as the DRAM cell described in the prior art.

<Method for Manufacturing Semiconductor Device>
In the manufacturing method of the semiconductor device 1c of the third embodiment, in the manufacturing method of the first embodiment, in the step described with reference to FIG. 3 (3), instead of forming the n-type base n (B) by epitaxial growth, An n-type base n (B) is formed by introducing a p-type impurity into the surface layer of the p-type base p (B).

  Thereafter, a mask 109 that opens only a part of the n-type base n (B) is formed, and a p-type anode p (A) is formed by introducing p-type impurities from the mask 109.

  At this time, impurities are introduced so that the n-type base n (B) is shallower than the p-type base p (B) and the p-type anode p (A) is shallower than the n-type base n (B). It is important to do.

  Even in the semiconductor device 1c according to the third embodiment, the p-type base p (B) made of a diffusion layer is provided on the surface layer portion of the n-type cathode n (K), and the gate electrode G is provided on the upper portion. This is a configuration provided. Therefore, as in the first embodiment, the semiconductor device (DRAM cell) 1c using a thyristor can be obtained using an inexpensive bulk semiconductor substrate 100 and without requiring a special process.

  Furthermore, since the n-well layer 101 formed at a deep position is separated from the DRAM portion having the thyristor structure by the p-well layer 102, current flows through the n-well layer 101 in the turn-on state of the thyristor. Can be prevented.

<< Fourth Embodiment >>
<Configuration of semiconductor device>
In the fourth embodiment, a semiconductor device having an SRAM cell using the semiconductor device having the thyristor configuration described above will be described.

  FIG. 6 is a cross-sectional configuration diagram showing a schematic configuration of the semiconductor device of the fourth embodiment, and shows two SRAM cells. A semiconductor device 2a shown in this figure includes, on the surface side of a p-type semiconductor substrate 100, a semiconductor device (1a) having the structure shown in FIG. 1, that is, an SRAM cell 201 composed of a MOS transistor Tr together with a thyristor 1a. ing.

  In the semiconductor substrate 100, an n-type well layer 101 is provided at a predetermined depth, a p-well layer 102 is provided on a surface layer separated by the n-type well layer 101, and the surface side of the p-well layer 102 is made of STI. The element regions are separated by the separation 103.

  The thyristor la portion of each SRAM cell 201 is configured in the same manner as in the first embodiment. That is, the p-type base p (B) is provided on the surface layer portion of the n-type cathode (K). The p-type base p (B) is surrounded by the n-type cathode (K) and the element isolation 103 and is separated into islands, and is in an electrically floating state with respect to another part of the semiconductor substrate 100. Yes. The n-type base n (B) and the p-type anode p (A) are stacked in this order on the p-type base p (B). On the p-type base p (B), a gate electrode G having a MOS structure is provided.

  On the other hand, the MOS transistor Tr is formed by sandwiching a p-type region constituting a channel portion between two n-type regions, that is, a source n (s) and a drain n (d). Here, the configuration in which the p-type region between the source n (s) and the drain n (d) is the p-well layer 102 is illustrated. However, in order to control the threshold voltage of the MOS transistor Tr, the p-type region is illustrated. A configuration in which a channel region in which the impurity concentration is adjusted is specially provided may be used.

  In particular, the drain n (d) of the MOS transistor Tr shares the n-type cathode n (K) of the thyristor 1a as it is.

  Further, in FIG. 6, two SRAM cells 201 are illustrated, but these SRAM cells 201 and 301 have a configuration in which the source n (s) of the MOS transistor Tr is shared.

  The semiconductor device 2a is operated in the same manner as the SRAM cell described in the prior art.

<Method for Manufacturing Semiconductor Device>
A manufacturing method of the semiconductor device 2a of the fourth embodiment will be described based on the manufacturing process diagrams of FIGS.

  First, as shown in FIG. 7A, a semiconductor substrate 100 made of p-type silicon is prepared, and an n-well layer 101 is formed at a predetermined depth of the semiconductor substrate 100 by applying an ion implantation method. Next, a p-well layer 102 is formed on the n-well layer 101 by ion implantation as necessary.

  Next, STI is formed as an element isolation 103 on the surface side of the semiconductor substrate 100, and each element region is isolated. Further, the surface of the semiconductor substrate 100 is covered with a protective insulating film 104.

  Next, as shown in FIG. 7B, a region for forming the source and gate electrodes of the two MOS transistors is covered with a mask pattern 202. Then, for example, by introducing impurities using an ion implantation method, an n-type cathode n (K) is formed at a depth in the p-well layer 102 shallower than the n-well layer 101 and at a depth separated by the element isolation 103. . After the ion implantation, the mask pattern 202 is removed.

  Next, as shown in FIG. 7 (3), a region where two MOS transistors are to be formed is covered with a mask pattern 203, and an n-type cathode n (from the surface of the semiconductor substrate 100 is introduced by introducing impurities, for example, using an ion implantation method. A p-type base p (B) reaching the depth position where it is joined to K) is formed. After the ion implantation, the mask pattern 203 is removed.

  Next, as shown in FIG. 7 (4), a polysilicon electrode film 106 is formed on the semiconductor substrate 100 via the gate insulating film 105, and this is patterned to connect the gate electrodes G and Gt in parallel. Form. At this time, the two gate electrodes G are provided so as to cross the end portions on the respective p-type bases p (B). On the other hand, the two gate electrodes Gt are provided across the upper portion of the p-well layer. Note that the gate insulating film 105 is formed after the protective insulating film 104 is removed.

  Next, as shown in FIG. 8A, a mask pattern 204 having a shape covering the p-type base p (B) exposed on one side of the gate electrode G is formed. Then, shallow n-type LDD regions 205 are formed on both sides of the gate electrode Gt by introducing impurities (for example, ion implantation) from the mask pattern 204 and the gate electrodes G and Gt. After the ion implantation is completed, the mask pattern 204 is removed.

  Thereafter, as shown in FIG. 8B, insulating sidewalls 107 are formed on both sides of the gate electrodes G and Gt.

  Next, as shown in FIG. 8C, a mask pattern 206 having a shape covering the p-type base p (B) exposed on one side of the gate electrode G is formed. An n-type layer reaching the n-type cathode n (K) from the surface of the semiconductor substrate 100 by introducing impurities (for example, ion implantation) from the mask pattern 206, the gate electrodes G and Gt, and the sidewalls 107 is formed. The n-type layer portion is formed as an extraction portion of the n-type cathode n (K) and a drain n (d) of the MOS transistor. Further, a source n (s) composed of an n-type layer deeper than the LDD region 205 is formed between the gate electrodes Gt and Gt. Note that the mask pattern 206 is removed after the ion implantation.

Next, as shown in FIG. 9A, the n-type cathode n (K), the drain n (d), the source n (s), and the gate electrodes G and Gt are covered, and the p-type base p (B) A protective film 207 having a shape exposing the surface is formed. This protective film 207 serves as a mask for epitaxial growth performed in the next step, and is made of silicon oxide (SiO ₂ ) or silicon nitride (SiN).

  Next, as shown in FIG. 9B, an n-type silicon layer is grown on the exposed surface of the semiconductor substrate 100, that is, on the p-type base p (B) by a selective epitaxial growth method. Let base n (B).

  Subsequently, as shown in FIG. 9 (3), a p-type silicon layer is grown on the n-type base n (B) by selective epitaxial growth, and this grown layer is used as a p-type anode p (A).

  After the above, the protective film 207 used as a mask at the time of selective epitaxial growth is removed as necessary, and the upper part of the semiconductor substrate 100 is covered with an interlayer insulating film not shown here. Then, connection holes reaching the gate electrodes G and Gt, the p-type anode p (A), and the source n (s) are formed in the interlayer insulating film, and the gate electrodes G and Gt and the p-type anode p are formed through these connection holes. (A) and a wiring connected to the source n (s) are formed to complete the semiconductor device 2a shown in FIG.

  In the semiconductor device 2a of FIG. 6 obtained as described above, the SRAM cell 201 is configured using the thyristor 1a having the same configuration as that of the first embodiment. That is, the thyristor 1a has a configuration in which a p-type base p (B) made of a diffusion layer is provided on the surface layer portion of the n-type cathode n (K), and a gate electrode G is provided thereon. Therefore, the SRAM cell 201 composed of the thyristor 1a and the access MOS transistor Tr can be obtained by using an inexpensive bulk semiconductor substrate 100 and without requiring a special process.

  In particular, also in the configuration of the fourth embodiment, the n-type base n (B) and the p-type anode p (A) are formed above the semiconductor substrate 100 by a selective epi growth technique. For this reason, as in the first embodiment, the process margin is increased as compared with the case where all of the four layers are diffusion layers formed in the adjacent region, so that the fabrication is easy.

  Further, in the thyristor 1a, the p-type base p (B) and the p-well layer 102 are separated by the n-type cathode n (K). Therefore, element isolation is provided for isolating the p-type base p (B) of the thyristor 201 and the p-well layer 102 constituting the channel portion between the source n (s) and the drain n (d) in the MOS transistor Tr. There is no need. Further, since it is not necessary to provide element isolation, the drain n (d) of the MOS transistor Tr and the n-type cathode n (K) of the thyristor 201 can be used as a common region. Thereby, the cell size can be reduced.

  Further, since the p-type base p (B) and the p-well layer 102 are separated by the n-type cathode n (K), the p-well layer 102 can be set to a common potential in all the SRAM cells 201. It is. Therefore, when the p-well layer 102 is fixed to the ground potential or the like, it is not necessary to form the contact of the p-well layer 102 for each MOS transistor, and if one well contact is formed for a set number of MOS transistors. Since it is good, the cell size can be miniaturized. However, the element isolation 103 for isolating the surface portion of the p-well is necessary.

  Further, since the n-well layer 101 formed at a deep position is separated from the thyristor 1a portion by the p-well layer 102, current is prevented from flowing through the n-well layer 101 when the thyristor 1a is turned on. it can.

«Fifth embodiment»
<Configuration of semiconductor device>
FIG. 10 is a configuration diagram showing an outline of the semiconductor device 2b of the fifth embodiment. The semiconductor device 2b shown in this figure is different from the semiconductor device 2a of the fourth embodiment in that the n-type base n (B) in the thyristor 1a is configured by a diffusion layer, and the other configuration is the first configuration. It is the same as the fourth embodiment.

  That is, the n-type base n (B) is provided as a diffusion layer on the surface layer portion of the p-type base p (B), and is arranged in a state of being electrically separated from the n-type cathode n (K) and the gate electrode G. Has been. The p-type anode p (A) is provided as a layer that is selectively epitaxially grown on the exposed surface of the n-type base n (B), as in the first embodiment.

  The semiconductor device 2b is also operated in the same manner as the SRAM cell described in the prior art.

<Method for Manufacturing Semiconductor Device>
In the manufacturing method of the semiconductor device 2b of the fifth embodiment, in the manufacturing method of the fourth embodiment, instead of forming the n-type base n (B) by epitaxial growth in the step described with reference to FIG. The n-type base n (B) may be formed by introducing p-type impurities into the surface layer of the p-type base p (B).

  At this time, it is important to introduce impurities so that the n-type base n (B) is shallower than the p-type base p (B).

  Even in the semiconductor device 2b of the fifth embodiment obtained as described above, the SRAM cell 201 is configured using the thyristor 1b having the same configuration as that of the second embodiment. That is, the thyristor 1b has a configuration in which a p-type base p (B) made of a diffusion layer is provided on the surface layer portion of the n-type cathode n (K), and a gate electrode G is provided thereon. For this reason, the SRAM cell 201 including the thyristor 1b and the access MOS transistor Tr can be obtained using an inexpensive bulk semiconductor substrate 100 and without requiring a special process.

  In particular, also in the configuration of the fifth embodiment, the p-type anode p (A) is formed above the semiconductor substrate 100 by the selective epi growth technique. Therefore, as in the second embodiment, the process margin is increased compared to the case where all of the four layers are diffusion layers formed in the adjacent region, and the fabrication is easy.

  Further, also in the thyristor 1b, the p-type base p (B) and the p-well layer 102 are separated by the n-type cathode n (K). Therefore, as in the fourth embodiment, it is possible to reduce the cell size. Further, since the n-well layer 101 formed at a deep position is separated from the thyristor 1b portion by the p-well layer 102, current is prevented from flowing through the n-well layer 101 when the thyristor 1b is turned on. it can.

<< Sixth Embodiment >>
<Configuration of semiconductor device>
FIG. 11 is a configuration diagram illustrating an outline of a semiconductor device 2c according to the sixth embodiment. The semiconductor device 2c shown in this figure is different from the semiconductor device 2b of the fifth embodiment in that the n-type base n (B) and the p-type anode (A) are also composed of diffusion layers. The configuration is the same as in the fifth embodiment.

  That is, the n-type base n (B) is provided as a diffusion layer on the surface layer portion of the p-type base p (B), and is provided in a state of being electrically separated from the n-type cathode n (K) and the gate electrode G. It has been. Further, the p-type anode p (A) is provided as a diffusion layer on the surface layer portion of the n-type base n (B), and is provided in a state of being electrically separated from the p-type base p (B) and the gate electrode G. It has been.

  The semiconductor device 2c is also operated in the same manner as the SRAM cell described in the prior art.

<Method for Manufacturing Semiconductor Device>
The manufacturing method of the semiconductor device 2c according to the sixth embodiment is the same as the manufacturing method according to the fourth embodiment except that the n-type base n (B) is formed by epitaxial growth in the step described with reference to FIG. An n-type base n (B) is formed by introducing a p-type impurity into the surface layer of the p-type base p (B).

  Thereafter, a mask 209 that opens only a part of the n-type base n (B) is formed, and a p-type anode p (A) is formed by introducing p-type impurities from the mask 209.

  At this time, impurities are introduced so that the n-type base n (B) is shallower than the p-type base p (B) and the p-type anode p (A) is shallower than the n-type base n (B). It is important to do.

  Even in the semiconductor device 2c of the sixth embodiment obtained as described above, the SRAM cell 201 is configured using the thyristor 1c having the same configuration as that of the third embodiment. That is, the thyristor 1c has a configuration in which the p-type base p (B) made of a diffusion layer is provided on the surface layer portion of the n-type cathode n (K), and the gate electrode G is provided on the p-type base p (B). For this reason, the SRAM cell 201 including the thyristor 1c and the access MOS transistor Tr can be obtained by using an inexpensive bulk semiconductor substrate 100 and without requiring a special process.

  Further, also in the thyristor 1c, the p-type base p (B) is separated from the p-well layer 102 by the n-type cathode n (K). Therefore, as in the fourth embodiment, it is possible to reduce the cell size. Further, since the n-well layer 101 formed at a deep position is separated from the thyristor 1c portion by the p-well layer 102, current is prevented from flowing through the n-well layer 101 when the thyristor 1c is turned on. it can.

<< Seventh Embodiment >>
<Configuration of semiconductor device>
FIG. 12 is a configuration diagram showing an outline of the semiconductor device 3a of the seventh embodiment. A semiconductor device 3a shown in this figure includes an SRAM cell composed of a MOS transistor Tr together with the semiconductor device (1a) of the first embodiment shown in FIG. 1, that is, a thyristor 1a. The semiconductor device 3a is different from the semiconductor device (2a) described with reference to FIG. 6 in that the thyristor 1a and the MOS transistor Tr are provided in a region separated by the element isolation 103. Other configurations are the same as those in the fourth embodiment.

  The semiconductor device 3a is also operated in the same manner as the SRAM cell described in the prior art.

  Even in the semiconductor device 3a having such a configuration, the thyristor 1a is provided with the p-type base p (B) made of a diffusion layer on the surface layer portion of the n-type cathode n (K), and the gate electrode G on the upper portion thereof. Is provided. Therefore, the SRAM cell 201 composed of the thyristor 1a and the access MOS transistor Tr can be obtained by using an inexpensive bulk semiconductor substrate 100 and without requiring a special process.

  Further, also in the thyristor 1a, the n-well layer 101 formed at a deep position is separated from the thyristor 1a portion by the p-well layer 102. Can be prevented from flowing.

  In the seventh embodiment, the semiconductor device (thyristor) having the configuration described in the first embodiment is used as the thyristor 1a. However, the semiconductor devices (thyristors) of the second and third embodiments are exemplified. The same applies to the configuration using the above.

  In the first to seventh embodiments described above, the element is separated from the p-type semiconductor substrate 100, and a deep n-well layer 101 is provided to reduce noise entering from the p-type semiconductor substrate 100. Explained the configuration. However, when there is no need to consider noise reduction or a reduction in operation margin, the n-well layer 101 does not need to be provided, and a configuration in which the n-well layer 101 is not provided in each embodiment may be employed.

It is a section lineblock diagram showing the composition of the semiconductor device of a 1st embodiment. FIG. 6 is a cross-sectional process diagram (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional process diagram (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment; It is a section lineblock diagram showing the composition of the semiconductor device of a 2nd embodiment. It is a section lineblock diagram showing the composition of the semiconductor device of a 3rd embodiment. It is a section lineblock diagram showing the composition of the semiconductor device of a 4th embodiment. It is sectional process drawing (the 1) which shows the manufacturing method of the semiconductor device of 4th Embodiment. It is sectional process drawing (the 2) which shows the manufacturing method of the semiconductor device of 4th Embodiment. It is sectional process drawing (the 3) which shows the manufacturing method of the semiconductor device of 4th Embodiment. It is a section lineblock diagram showing the composition of the semiconductor device of a 5th embodiment. It is a section lineblock diagram showing the composition of the semiconductor device of a 6th embodiment. It is a section lineblock diagram showing the composition of the semiconductor device of a 7th embodiment. It is a figure explaining the structure of the DRAM cell described in the nonpatent literature 1 of the prior art. FIG. 5 is a current-voltage diagram illustrating the operation of a prior art DRAM cell. It is a figure explaining the structure of the SRAM cell described in the nonpatent literature 2 of the prior art. FIG. 6 is a current-voltage diagram (part 1) for explaining the operation of the conventional SRAM cell; It is a current-voltage diagram illustrating the operation of the prior art SRAM cell. It is a figure explaining the structure of the SRAM cell described in the nonpatent literature 3 of the prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1a, 1b, 1c, 2a, 2b, 2c, 3a ... Semiconductor device, 100 ... Semiconductor substrate (semiconductor layer), 103 ... Element isolation, G ... Gate electrode, n (K) ... n-type cathode (1st conductivity type area | region) ), P (B)... P-type base (second conductivity type base region), n (B)... N-type base (first conductivity type base region), p (A). Type region), n (d) ... drain region, Tr ... transistor (for access)

Claims (9)

A semiconductor region in which a first conductivity type region, a second conductivity type base region, a first conductivity type base region, and a second conductivity type region are provided in contact with each other in this order;
In a semiconductor device comprising a gate electrode provided in the base region of the second conductivity type,
The base region of the second conductivity type is composed of a diffusion layer provided in a surface layer portion of the first conductivity type region,
The first conductivity type base region and the second conductivity type region are provided on the surface side of the second conductivity type base region,
The semiconductor device according to claim 1, wherein the gate electrode is provided on an upper part of the base region of the second conductivity type. The semiconductor device according to claim 1,
The semiconductor device, wherein the first conductivity type region and the second conductivity type base region are provided in a surface layer of a semiconductor substrate. The semiconductor device according to claim 2,
The base region of the second conductivity type is in a state of being isolated in an island shape by the first conductivity type region and element isolation. The semiconductor device according to claim 1,
The first conductivity type base region comprises a layer selectively epitaxially grown on the second conductivity type base region;
The semiconductor device according to claim 1, wherein the second conductivity type region disposed at the end portion is a layer selectively grown epitaxially on the base region of the first conductivity type. The semiconductor device according to claim 1,
The first conductivity type base region comprises a diffusion layer provided in a surface layer portion of the second conductivity type base region;
The second conductivity type region comprises a layer selectively epitaxially grown on the base region of the first conductivity type. The semiconductor device according to claim 1,
The first conductivity type base region comprises a diffusion layer provided in a surface layer portion of the second conductivity type base region;
The second conductivity type region includes a diffusion layer provided in a surface layer portion of the base region of the first conductivity type. The semiconductor device according to claim 1,
The gate electrode is provided on the base region of the second conductivity type via an insulating film. A semiconductor device, wherein: The semiconductor device according to claim 1,
An access transistor having a drain region having the same potential as that of the first conductivity type region is provided. The semiconductor device according to claim 8.
The semiconductor device, wherein the first conductivity type region and the drain region share the same region.

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