JPH03185931A - A/d converter circuit - Google Patents

A/d converter circuit

Info

Publication number
JPH03185931A
JPH03185931A JP1323859A JP32385989A JPH03185931A JP H03185931 A JPH03185931 A JP H03185931A JP 1323859 A JP1323859 A JP 1323859A JP 32385989 A JP32385989 A JP 32385989A JP H03185931 A JPH03185931 A JP H03185931A
Authority
JP
Japan
Prior art keywords
circuit
comparator
input
current
input section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1323859A
Other languages
Japanese (ja)
Inventor
Takao Morishita
森下 隆雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP1323859A priority Critical patent/JPH03185931A/en
Publication of JPH03185931A publication Critical patent/JPH03185931A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To improve the accuracy of A/D conversion by providing a compensation circuit and supplying a base current to a transistor(TR) of an input section of each comparator to prevent the production of an error component in the division of a reference voltage, thereby applying accurate division. CONSTITUTION:A comparator 6 supplies a base current to a base of TRs of an input section of each comparator and the current flowing to the entire reference resistor group 3 from a reference voltage terminal 1 is made identical. Thus, no error component due to a base current is generated in the divided voltage and an accurate comparate level is obtained. That is, the circuit 6 is constituted of TRs and current mirror circuits equal to those of the input section of the comparator and a base current is supplied to the TRs of the input section of each comparator. Thus, an input analog signal is compared with each accurate division voltage at each comparator to obtain a digital value with high accuracy and power consumption is saved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、並列比較型のA−Dコンバータ回路に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel comparison type A-D converter circuit.

〔従来の技術〕[Conventional technology]

第2図(alij:従来の並列比較型A−Dコンバータ
回路の一例の回路構成を示す。
FIG. 2 (alij) shows a circuit configuration of an example of a conventional parallel comparison type AD converter circuit.

図にかいて1は基準電圧端、2はアナログ信号入力端、
3はリファレンス抵抗群、4はコンパレータ回路群、5
はエンコード回路である。
In the figure, 1 is the reference voltage terminal, 2 is the analog signal input terminal,
3 is a reference resistance group, 4 is a comparator circuit group, 5
is an encoding circuit.

基準電圧Vrefをリファレンス抵抗群3で分割し。The reference voltage Vref is divided by the reference resistor group 3.

コンパレータ回路群4の各コンパレータ回路ニヨシ入カ
アナログ信号■□と分割した各電圧を比較する。
Each comparator circuit of the comparator circuit group 4 is compared with the input analog signal □ and each divided voltage.

各瞬時の入力アナログ信号のレベルに応じた数のコンパ
レータ回路が出力を反転する。クロック信号ごとの出力
を反転したコンパレータ回路の数を捕え、これをエンコ
ード回路5で2進数に変換してディジタル値を得る。
A number of comparator circuits invert the output depending on the level of the input analog signal at each instant. The number of comparator circuits that invert the output of each clock signal is captured, and the encoder circuit 5 converts this into a binary number to obtain a digital value.

第2図(b)は第2図(a)のA−Dコンバータ回路に
訟けるコン・(レータ回路の入力部の回路構成を示す。
FIG. 2(b) shows the circuit configuration of the input section of the converter circuit which is connected to the A-D converter circuit of FIG. 2(a).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の上記のような並列比較型A−Dコンバータ回路で
は、第2図(b)に示すように、リファレンス抵抗群3
から各コンパレータ回路に電流が流れ流増幅率)により
、分割電圧にエラー成分が生じ。
In the conventional parallel comparison type A-D converter circuit as described above, as shown in FIG. 2(b), the reference resistor group 3
Current flows through each comparator circuit, and an error component occurs in the divided voltage due to the current amplification factor.

正確ナコンノ4レートレベルが得られないという問題が
あった。
There was a problem that accurate Nakonno 4 rate level could not be obtained.

基準電圧端1から流れ込む電流をiHとすると。Let the current flowing from the reference voltage terminal 1 be iH.

各分割電圧のレベルは最上位から順次 となり、最上位からn@目の分割電圧のレベルは。The level of each divided voltage is set sequentially from the highest level. So, the level of the n@th divided voltage from the highest level is.

上記のように、 ■nにはエラー成分(n−1)!・1b−Rが生ずる。As described above, ■N is the error component (n-1)!・1b-R occurs.

本、発明は上記の問題を解消するためになされたもので
1分割電圧にエラー成分の生じない回路を提供すること
を目的とする。
The present invention has been made to solve the above problem, and an object of the present invention is to provide a circuit in which no error component occurs in one divided voltage.

〔課題を解決するための手段〕 本発明の並列比較型A−Dコンバータ回路は、リファレ
ンス抵抗回路からコンミ4レータ回路群の各コンパレー
タ回路に流れ込むコンパレータ入力電流により分割電圧
に生ずるエラー成分を補償すルタメ、コンノJ?レータ
回路の入力部のトランジスタと特性が等しいトランジス
タにょう入力部のトランジスタのベース電流を検出し、
カレントミラ回路K 、1: J コンパレータ回路群
の各コンパレータ回路の入力に上記ベース電流に相当す
る電流を供給する補償回路を設けたものである。
[Means for Solving the Problems] The parallel comparison type A-D converter circuit of the present invention compensates for error components occurring in the divided voltage due to the comparator input current flowing from the reference resistor circuit to each comparator circuit of the comma-four regulator circuit group. Lutame, Konno J? Detects the base current of the transistor in the input part of the transistor whose characteristics are the same as that of the transistor in the input part of the regulator circuit,
Current mirror circuit K, 1: J A compensation circuit is provided for supplying a current corresponding to the base current to the input of each comparator circuit of the comparator circuit group.

〔実施例〕〔Example〕

第1図(a)は本発明の一実施例の回路構成を示す。 FIG. 1(a) shows a circuit configuration of an embodiment of the present invention.

図にかいて1.2,3.4,5は第2図(a)の同一符
号と同一または相当する部分を示し、6はリファレンス
抵抗群3による基準電圧の分割電圧のエラー成分を除く
ための補償回路である。
In the figure, 1.2, 3.4, and 5 indicate the same or corresponding parts as the same reference numerals in FIG. This is a compensation circuit.

第1図(b)は第1図(a)の実施例におけるコン−ぐ
レータ回路の入力部の回路構成を、第1図(c)は第1
図(a)の実施例における補償回路6の回路構成を示す
FIG. 1(b) shows the circuit configuration of the input section of the conglomerator circuit in the embodiment of FIG. 1(a), and FIG.
The circuit configuration of the compensation circuit 6 in the embodiment of FIG. 3(a) is shown.

補償回路6かも、各コンパレータ回路の入力部のトラン
ジスタのベースに流れ込むベース電流ス抵抗群3全体に
流れる電流が等しくibとなシ。
In the compensation circuit 6, the base current flowing into the base of the transistor in the input section of each comparator circuit and the current flowing through the entire resistor group 3 are equal to ib.

分割電圧にベース電流ibによるエラー成分が生ずるこ
とがなくなる。したがって、正確なコンノfレートレベ
ルが得られる。
An error component due to the base current ib is no longer generated in the divided voltage. Therefore, an accurate conno f rate level can be obtained.

補償回路6は、コンパレータ回路の入力部と等しいトラ
ンジスタと定電流回路による該トランジスタで構成され
ていて、各コンノやレータ回路の入力部のトランジスタ
にベース電流を供給する。
The compensation circuit 6 is composed of a transistor that is the same as the input section of the comparator circuit and the same transistor as a constant current circuit, and supplies a base current to the transistors at the input section of each converter circuit and the regulator circuit.

入力アナログ信号が各コンパレータ回路で正確な各分割
電圧と比較され、精度の高いディジタル値が得られる。
The input analog signal is compared with each accurate divided voltage in each comparator circuit to obtain a highly accurate digital value.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によると、基準電圧を正確
に分割することができ、高い精度のA−D変換を実現で
きるという利点がある。
As described above, according to the present invention, there is an advantage that the reference voltage can be accurately divided and highly accurate A-D conversion can be realized.

また、従来、精度劣化を防ぐため、リファレンス抵抗群
に過大な電流を流して−たが、本発明により、その必要
がなくなり、省電力になる。
Furthermore, in the past, an excessive current was passed through the reference resistor group in order to prevent accuracy deterioration, but the present invention eliminates the need for this, resulting in power savings.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は本発明の一実施例の回路構成を示す回路
図、第1図(b)は第1図(a)の実施例におけるコン
パレータ回路の入力部の回路構成を示す回路図。 第1図(clは第1図(a)の実施例にかける補償回路
の回路構成を示す回路図、第2図(&)は従来の並列比
較型A−Dコンバータ回路の一例の回路構造を示す回路
図、第2図(blは第2図(aJのA−Dコンバータ回
路にかけるコンパレータ回路の入力部の回路構成を示す
回路図である。 l・・・基準電圧端、2・・・アナログ信号入力端、3
・・・リファレンス抵抗群、4・・・コンパレータ回路
群、5・・・エンコード回路、6・・・補償回路、なお
図中同一符号は同一または相当する部分を示す。
FIG. 1(a) is a circuit diagram showing the circuit configuration of an embodiment of the present invention, and FIG. 1(b) is a circuit diagram showing the circuit configuration of the input section of the comparator circuit in the embodiment of FIG. 1(a). . Figure 1 (cl) is a circuit diagram showing the circuit configuration of a compensation circuit applied to the embodiment of Figure 1 (a), Figure 2 (&) is a circuit diagram of an example of a conventional parallel comparison type A-D converter circuit. The circuit diagram shown in FIG. 2 (bl is a circuit diagram showing the circuit configuration of the input section of the comparator circuit applied to the A-D converter circuit of FIG. 2 (aJ). l...Reference voltage terminal, 2... Analog signal input terminal, 3
. . . reference resistance group, 4 . . . comparator circuit group, 5 . . . encode circuit, 6 .

Claims (1)

【特許請求の範囲】 コンパレータ回路群により入力アナログ信号と基準電圧
をリファレンス抵抗群で分割した各電圧を比較し、入力
アナログ信号の瞬時ごとのレベルに対し出力の反転する
コンパレータ回路の数をエンコード回路で2進数に変換
する構成の並列比較型A−Dコンバータ回路において、 リファレンス抵抗回路からコンパレータ回路群の各コン
パレータ回路に流れ込むコンパレータ入力電流により分
割電圧に生ずるエラー成分を補償するため、コンパレー
タ回路の入力部のトランジスタと特性が等しいトランジ
スタにより上記入力部のトランジスタのベース電流を検
出し、カレントミラー回路により上記コンパレータ回路
群の各コンパレータの入力に上記ベース電流に相当する
電流を供給する補償回路を設けたことを特徴とするA−
Dコンバータ回路。
[Claims] A circuit that encodes the number of comparator circuits whose outputs are inverted for each instantaneous level of the input analog signal by comparing the input analog signal and each voltage obtained by dividing the reference voltage by the reference resistor group using a group of comparator circuits. In a parallel comparison type A-D converter circuit configured to convert into a binary number at , the input of the comparator circuit is A compensation circuit is provided in which the base current of the transistor in the input part is detected by a transistor having the same characteristics as the transistor in the part, and a current corresponding to the base current is supplied to the input of each comparator in the comparator circuit group by a current mirror circuit. A- characterized by
D converter circuit.
JP1323859A 1989-12-15 1989-12-15 A/d converter circuit Pending JPH03185931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1323859A JPH03185931A (en) 1989-12-15 1989-12-15 A/d converter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1323859A JPH03185931A (en) 1989-12-15 1989-12-15 A/d converter circuit

Publications (1)

Publication Number Publication Date
JPH03185931A true JPH03185931A (en) 1991-08-13

Family

ID=18159385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1323859A Pending JPH03185931A (en) 1989-12-15 1989-12-15 A/d converter circuit

Country Status (1)

Country Link
JP (1) JPH03185931A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013021438A (en) * 2011-07-08 2013-01-31 New Japan Radio Co Ltd Frequency conversion circuit
WO2013183688A1 (en) * 2012-06-05 2013-12-12 国立大学法人 鹿児島大学 Analog-digital converter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013021438A (en) * 2011-07-08 2013-01-31 New Japan Radio Co Ltd Frequency conversion circuit
WO2013183688A1 (en) * 2012-06-05 2013-12-12 国立大学法人 鹿児島大学 Analog-digital converter
US9118337B2 (en) 2012-06-05 2015-08-25 Kagoshima University Analog-digital converter
JPWO2013183688A1 (en) * 2012-06-05 2016-02-01 国立大学法人 鹿児島大学 Analog to digital converter

Similar Documents

Publication Publication Date Title
US4875048A (en) Two-step parallel analog to digital converter
US4573005A (en) Current source arrangement having a precision current-mirror circuit
US5721548A (en) Analog-to-digital converter for compensating for input bias current of comparator
US4752731A (en) Electronic type electric energy meter
JPH03185931A (en) A/d converter circuit
JPS63198419A (en) Linearity compensating circuit for parallel a/d converter
US4542332A (en) Precision current-source arrangement
US6600434B2 (en) A/D conversion device and A/D converter error correction device
JPS59207732A (en) Two step type ad converter
KR100282443B1 (en) Digital / Analog Converter
JP2956119B2 (en) Parallel A / D converter
JPH0547006B2 (en)
JPS61242119A (en) Digital-to-analog converter
JPH01296822A (en) Analog-digital converter
US4647904A (en) Folding-type analog-to-digital converter
JP3172090B2 (en) AD converter
JPH0296431A (en) Parallel type a/d converter
JPS63266927A (en) Parallel analog/digital converter
JPS6022675Y2 (en) AD converter
JPS63209225A (en) Integrated circuit for analog/digital converter
JPS6029035A (en) A/d converter
JPS58105382A (en) Integration circuit
JP2808771B2 (en) Analog / digital converter
JPS63181530A (en) A/d converter
JPH0237824A (en) Comparator