JPH03185929A - Quantizer - Google Patents

Abstract

PURPOSE:To obtain excellent picture quality in >=7-bit through the use of a 6-bit A/D converter by providing an analog adder adding wobbling clocks, an A/D converter and a digital adder, etc. CONSTITUTION:An analog video signal SV fed to an input terminal 1 is applied to an analog adder 4 via a buffer 2 and a resistor 3. Moreover, a system clock CLK is fed to a terminal 5, the phase of the clock is inverted by an inverter 6 and the result is divided into 1/2 by a frequency divider 7, and the result is fed to the adder 4 via a resistor 8 as a wobbling clock WOB. Then the sum of the signal SV from the adder 4 and the clock WOB is fed to the 6-bit A/D converter 9, where the signal is converted into a 6-bit digital data Xn and fed to an adder 10. Then the adder 10 adds data Xn and Xn-1, a 7-bit digital data Yn is outputted and fed to an output terminal 12, and the 6-bit A/D converter is used to obtain excellent picture quality in >=7-bit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a quantization device suitable for use, for example, in digitally processing a video signal.

[Prior Art] FIG. 9 shows the basic configuration of a digital video processing device.

In the figure, an analog video signal supplied to an input terminal 51 is converted into a digital signal by an A/D converter 52 and then supplied to a digital video processing circuit 53. The output signal of this processing circuit 53 is converted into an analog signal by a D/A converter 54 and then supplied to an output terminal 55.

In such a video processing device, the A/D converter 52
The image quality improves as the number of quantization bits increases.

Generally, a screen with normal brightness requires 7 or more pits, and in practice it is standard to use an 8-bit A/D converter.

[Problems to be Solved by the Invention] However, since an 8-bit A/D converter is relatively expensive, an inexpensive 6-bit A/D converter is often used. 6 bits) The A/D converter expresses the brightness level from dark to bright with 64 gradations, so the brightness level from dark to bright is 25
Compared to an 8-bit A/D converter that expresses 6 gradations, this causes deterioration in gradation expression due to generation of false contouring and deterioration in S/N due to quantization noise.

For example, a dither method has been proposed as a method for making false contours less noticeable. That is, as shown in FIG. 10, an adder 57 adds a pseudorandom number generated by a dither signal generator 56 to an analog video signal, and the output signal of this adder 57 is supplied to an A/D converter δ2. It is something to do. According to this, the false contour is dispersed and becomes less noticeable.

However, this dither method has the disadvantage that the dither signal generator 56 that generates pseudo-random numbers is a relatively large-scale circuit. Furthermore, the digital signal itself obtained from the A/D converter 52 using the dither method is still 6 bits, and the improvement in gradation expression is largely due to the spatial integration effect, which is sufficient for still images. There were cases where it was not possible.

Therefore, in the present invention, it is possible to obtain a good image quality equivalent to or higher than that of 7 bits by using, for example, an inexpensive 6-bit A/D converter.

[Means for Solving the Problems] The present invention provides a human-powered analog signal with a frequency 172I'l-N times the conversion clock (M and N are positive integers, and M>
N) and whose amplitude is an odd multiple of 1/2 step width of the number of quantization bits N, and an analog adder that adds a wobbling clock whose amplitude is an odd multiple of 1/2 step width of the number of quantization bits N, and converting the output signal of this analog adder into a digital signal with the number of quantization bits N. 2M-N-1 clocks to 1 clock of the conversion clock, which supplies the output signal of this A/D converter to obtain an output digital signal with the number of quantization bits M. The circuit includes a series circuit of 2M-N-1 stages of digital low-pass filters each consisting of delay elements having a delay time of .

[Function] In the above configuration, the A/D converter has a quantization bit number N
, for example, 6 bits, a digital signal of M bits, 7 bits or more is obtained from the digital adder. In other words, using an N-bit A/D converter, it is possible to obtain an image quality equivalent to or higher than that of M pits.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. In this example, a 6-bit A/D converter is used to obtain a 7-bit digital signal.

In the figure, an analog video signal SV supplied to an input terminal 1 is passed through a buffer 2 and a resistor 3 to an adder 4.
is supplied to

Further, the system clock CLK is supplied to the terminal 5. In this example, the system clock CLK is synchronized with the horizontal synchronization signal HD of the video signal Sv described above, and its frequency is, for example, 1100f)I (fH is the horizontal frequency).

The system clock CLK supplied to the terminal 5 has its phase inverted by an inverter 6, and then is divided by 25 by a frequency divider 7. The output signal of the frequency divider 7 is supplied to the adder 4 via a resistor 8 as a wobbling clock WOB. In this case, the addition ratio of the video signal Sv and the wobbling clock WOB in the adder 4 is determined by the resistance values of the resistors 3 and 8. The peak-to-peak value) is set to be an odd multiple of the 1/2 step width of the 6-bit quantization step, in this example 1 time.

Video signal SV from adder 4 and wobbling clock W
The addition signal with OB is supplied to a 6-bit A/D converter 9 and converted into 6-bit digital data X11. In this case, the A/D converter 9 is supplied with the system clock CLK, which is supplied to the terminal 5, as a conversion clock (sampling clock).

As mentioned above, when forming the wobbling clock WOB, the phase of the system clock CLK is inverted by the inverter 6, so that the changing points (rising and falling edges) of the wobbling clock WOB are the sampling points. They are made to not match.

6-bit digital data Xn output from the A/D converter 9 is supplied to a digital adder 10.

Further, digital data Xn outputted from the A/D converter 9 is supplied to a data terminal of a D flip-flop 11, and a system clock CLK is supplied from a terminal 5 to a clock terminal of this D flip-flop 11. This D
The output terminal Q of the flip-flop 11 receives digital data X delayed by one clock from the digital data Xn.
n-1 is obtained, and this digital data X n-1 is supplied to the adder 10.

The adder 10 adds digital data Xn and Xn-1, and the adder 10 outputs 7-bit digital data Yn, which is supplied to the output terminal 12 as output digital data. In this case, the adder 10 and the D flip-flop 11 substantially reduce the frequency by 1/1 of the frequency of the system clock CLK.
A low-pass filter having a cutoff frequency of frequency No. 2 is constructed. Therefore, the wobbling clock WOB added by the adder 4 is automatically removed by this low-pass filter, so that it no longer appears in the digital data Yn.

This example is configured as described above, and then the digital data Y
How n is formed will be explained.

FIG. 2 shows the state of quantization in a typical A/D converter. As is clear from this figure, the normal A/D
In the converter, as the number of bits increases from 6 bits (dashed line) to 7 bits (-dotted chain line), the manually input video signal S
It approaches V (solid line) and good results can be obtained.

This is compared to a 6-bit quantization step (Ln).
This is because the 7-bit quantization step (Ln and Qn) is finer.

In this example, the adder 4 adds the wobbling clock WOB to the video signal SV (shown by the broken line in FIG. 3), and
The signal (SV+WOB) supplied to the /D converter 9 is 6
It is repeatedly shifted with a step width of 1/2 of the bit quantization step (as shown by the solid line in the figure). Therefore, the digital data Xn output from the A/D converter 9 is arranged as shown by the dots in the figure.

In the D flip-flop 11, this digital data
Since n is delayed by one clock of the system clock CLK, the digital data Xn-1 is arranged as shown by the dot "O" in FIG. Therefore, the 7-bit digital data Yn output from the adder 10 is arranged as shown by the "X" points in the figure.

In the end, 7-bit digital data Yn is 7-bit) A
The result is similar to that of quantization using a /D converter (see Figure 2 @).

In FIG. 1, the amplitude of the wobbling clock WOB supplied to the adder 4 is set to an even number multiple of 1/2 step width of a 6-bit quantization step, for example, twice (one step width of a 6-bit quantization step). ), such results cannot be obtained.

As described above, according to this example, it is possible to obtain the same digital data Yn using the inexpensive 6-bit A/D converter 9 as when using a 7-bit A/D converter.

Also, the wobbling clock W added to the video signal SV
OB is a simple repetitive signal and can be formed with simple circuits such as an inverter 6 and a frequency divider 7, and does not require large-scale circuits such as conventional dither signal generators.
It is easy to integrate and can be constructed at low cost.

Furthermore, since the entire process is performed in synchronization with the system clock CLK, there is no risk of beats or flickers occurring.

Furthermore, since the output 7-bit digital data Yn itself has a 7-bit information content, unlike the dither method, this method has the advantage of being effective even for still images and the like.

10- Note that in the above embodiment, 7-bit digital data Yn is obtained using a 6-bit A/D converter 9, but N-bit A/D conversion is generally performed using a similar configuration. M-bit digital data can be obtained using the device.

Here, N and M are positive integers, and N<M.

In this case, the frequency of the wobbling clock WOB added to the video signal SV is 1/2M-N of the frequency of the system clock CLK, and the amplitude is an odd multiple of the 172 step width of the number of quantization bits N. It will be done like this.

Further, the digital data Xn from the A/D converter is transmitted through 2 ff1-N-1 stages each composed of delay elements each having a delay time of 2 M-N-1 clocks to 1 clock of the system clock CLK. is supplied to a series circuit of low-pass filters.

In FIG. 5, for example, a 6-bit A/D converter 9 is used to obtain 8-bit digital data Zn.

In the figure, the frequency is divided into four by the frequency divider 7A.

11- And the wobbling clock W supplied to the adder 4
The amplitude of OB is, for example, 1/2 of the 6-pit quantization step.
It is considered to be the step width.

The 6-bit digital data Xn output from the A/D converter 9 is supplied to a digital adder 13.

Further, the digital data Xn output from the A/D converter 9 is supplied to the data terminal of the D flip-flop 14, and the signal obtained at the output terminal Q of this D flip-flop 14 is supplied to the data terminal of the D flip-flop 15. is supplied to The system clock CLK is supplied from the terminal 5 to the clock terminals of these D flip-flops 14 and 15. At the output terminal Q of the D flip-flop 15,
Digital data Xn-2 delayed by two clocks from the digital data Xn is obtained, and this digital data Xn-2 is supplied to the adder 13.

The adder 13 adds digital data Xn and Xn-2, and the adder 13 outputs 7-bit digital data Yn. In this case, the 2-adder 13 and the D flip-flops 14 and 15 substantially increase the frequency of the system clock CLK by 1
A low-pass filter having a cutoff frequency of /4 is constructed. Therefore, the wobbling clock WOB added by the adder 4 is automatically removed by this low-pass filter, so that it no longer appears in the digital data Yn.

The 7-bit digital data Yn output from the adder 13 is supplied to the digital adder 16.

Also, the digital data Yn output from the adder 13
is supplied to the data terminal of the D flip-flop 17,
The clock terminal of this D flip-flop 17 has a terminal 5.
The system clock CLK is supplied from the system clock CLK. The output terminal Q of this D flip-flop 17 receives digital data Yn- which is delayed by one clock from the digital data Yn.
1 is obtained, and this digital data Yn-1 is sent to adder 1.
6.

The adder 16 adds digital data Yn and Yn-113-, and the adder 16 outputs 8-bit digital data Zn.
is supplied to the output terminal 12 as output digital data. In this case, adder 16 and D flip-flop 1
7 constitutes a low-pass filter whose cutoff frequency is substantially 172 of the frequency of the system clock CLK.

The example shown in FIG. 5 is constructed as described above, and the other parts are constructed similarly to the example shown in FIG.

In this example, the adder 4 adds the wobbling clock WOB to the video signal SV (shown by the broken line in FIG. 6), and
The signal (sv+woB) supplied to the /D converter 9 is 6
It is repeatedly shifted with a step width of 1/2 of the bit quantization step (as shown by the solid line in the figure). Therefore, the digital data Xn output from the A/D converter 9 is arranged as shown by the dots in the figure.

In the D flip-flops 14 and 15, this digital data Xn is delayed by two clocks of the system clock CLK14-.
n-2 is arranged as shown by the "○" point in FIG.

Therefore, the 7-bit digital data Yn output from the adder 13 is arranged as shown by the "X" points in the figure.

In addition, in the D flip-flop [7], this digital data Yn is delayed by l clocks of the system clock CLK, so the digital data Yn-1 is
The arrangement will be as shown by the point Δ. Therefore, adder 1
The 8-bit digital data Zn output from 6 is
The arrangement is as shown by the "mouth" point in the figure.

In this way, the 8-bit digital data Zn has the same result as quantization by an 8-bit A/D converter.

In the above-described embodiment, the output signal of the A/D converter 9 is immediately converted into multi-bit data, but in the case of a memory application system, the output signal of the A/D converter 9 may be stored in the memory. By increasing the number of bits on the output side of the memory, the memory capacity can be reduced and the configuration can be made at low cost.

[Effects of the Invention] As explained above, according to this invention, N-bit A
Using a /D converter, N bits of digital data having an information content of M bits (N<M) can be obtained. Further, since the wobbling clock added to the human analog signal is a simple repetitive signal, it can be formed with a simple circuit. Therefore, a quantization device that obtains M-bit digital data can be constructed easily and inexpensively, and since it is only necessary to add a small number of circuits to an N-bit A/D converter, it can be easily integrated into an integrated circuit. I'll come.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Figs. 2 to 4 are diagrams explaining its operation, Fig. 5 is a block diagram showing another embodiment of the invention, and Figs. 6 to 8 The figure is an explanatory diagram of its operation, No. 9
The figure is a basic configuration diagram of the DigiMole video processing device 16, and FIG. 10 is an explanatory diagram of the dither method. 1 ・ 2 ・ 3, 8 ◆ 4 ・ 6 ◆ 7 ◆ 9 ◆ 10, 1 11, 1 12 ◆ ・Input terminal, buffer, resistor, analog adder, inverter, frequency divider, A/D converter 6 ◆ Digital adder 15.17 ・D flip-flop ・Output terminal

Claims (1)

[Claims] (1) The frequency of the input analog signal is 1 of the conversion clock.
/2^M^-^N times (M and N are positive integers, and M>N)
and an analog adder that adds a wobbling clock whose amplitude is an odd multiple of 1/2 step width of the number of quantization bits N, and converting the output signal of the analog adder into a digital signal with the number of quantization bits N. an A/D converter and 2^M of each of the conversion clocks that supply the output signal of the A/D converter to obtain an output digital signal with a quantization bit number M;
^-^N^-^Constructed of delay elements with a delay time of 1 clock to 1 clock 2^M^-^N^-^1
1. A quantization device comprising: a series circuit of digital low-pass filters.