JPH0318276B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a non-volatile MIS floating gate memory device E ² PROM. This E ² PROM is constructed in combination with a volatile memory device such as static random access memory (SRAM).

Background of the Technology Recently, a memory device (NOVRAM) has been developed that combines an SRAM cell with the above-mentioned E ² PROM cell configured with a floating gate. Although this NOVRAM has the disadvantages of a complicated circuit configuration and large size, it can be expected to have applications similar to nonvolatile read/write RAM.

FIG. 1 is a circuit diagram of a typical NOVRAM cell. In FIG. 1, the NOVRAM cell includes an SRAM cell consisting of transistors Q ₁ to Q ₄ and CL ₁ ;
E ² PROM consisting of capacitor modules CM ₁ and CM ₂ , transistors Q ₅ to _{Q 8} , and capacitors C ₁ and C ₂
It consists of cell CL ₂ .

The SRAM cell CL ₁ has a flip-flop configuration similar to a normal cell, and data is written and read through transfer gates connected to nodes N ₁ and N ₂ . Also, E ² PROM
In the cell CL ₂ , it depends on whether or not electrons are injected into the floating gate formed by the electrode E ₃ of the memory module CM ₁ , the electrode E ₆ of the memory module CM ₂ , and the gate of the transistor Q ₇ . The data is stored. Here, SRAM
Transferring data from cell CL ₁ to E ² PROM cell CL ₂ is called "store," and conversely, transferring data from E ² PROM cell CL ₂ to SRAM cell CL ₁ is called "recall."

For example, assume that data in which the potentials of nodes N ₁ and N ₂ of SRAM cell CL ₁ are at low level and high level, respectively, is stored in E ² PROM cell CL ₂ . In this case, the power supply voltage V _HH from 0V to 20~30V
for example, and hold it for 10 msec. At this time, node _N1 is at low level, so transistor _Q5 is turned off, and the capacitor module
Since the electrode E ₁ of CM ₁ is in a floating state, the floating gates (gates of E ₃ , E ₆ , and Q ₇ ) are pulled up to a high voltage due to capacitive coupling due to the rise in voltage V _HH . On the other hand, since node N ₂ is at high level, transistor Q ₆ is turned on,
Therefore, the electrode _E4 of the capacitor _CM2 is at ground potential. As a result, the high voltage V _HH is the capacitance between the electrodes E ₂ and E ₁ , the capacitance between the electrodes E ₁ and E ₃ , and the capacitance between the electrodes E ₆ and E ₄
In this case, it will be applied to the capacitance between
The capacitance between electrodes E ₆ and E ₄ is set to be very small compared to the other two capacitances. Therefore, the electrode E ₆ ,
A voltage approximately close to the voltage _VHH is applied between _E4 , and electrons are injected from the electrode _E4 to the electrode _E6 , that is, the floating gate, due to the tunneling phenomenon, and the transistor _Q7 is turned off. This negative charge on the floating gate is retained even after both power supply voltages V _CCC and V _HH are turned off, and nonvolatile storage is performed.

Further, assume that data in which the potentials of nodes N ₁ and N ₂ of SRAM cell CL ₁ are at high level and low level, respectively, is stored in E ² PROM cell CL ₂ . At this time, since the node N ₂ is at a low level, the transistor Q ₆ is turned off, and the electrode _{E 4} of the capacitor module CM ₂ is in a floating state, so the electrode E ₄ becomes Pulled up to high voltage. On the other hand,
Since node _N1 is at high level, the transistor
Q ₅ is turned on and therefore the electrode E ₁ of the capacitor CM ₁ is at ground potential. As a result, the high voltage V _HH
is the capacitance between electrodes E ₅ and E ₄ , the capacitance between electrodes E ₄ and E ₆ ,
This will be applied to the capacitance between electrodes E ₃ and E ₁ , but in this case as well, since the capacitance between electrodes E ₄ and E ₆ is set to be very small compared to the other two capacitances, A voltage approximately close to the voltage V _HH is applied between E ₄ and E ₆ , and electrons are extracted from the electrode E ₆ , that is, the floating gate, to the electrode E ₄ due to the tunneling phenomenon, and the transistor Q ₇ is turned on.

Next, the data of the E ² PROM cell CL ₂ , where electrons are stored in the floating gate, is transferred to the SRAM cell.
Assume a case where a recall is made to CL ₁ . in this case,
While the power supply voltage V _HH is held at 0V, the power supply voltage V _CCC is temporarily lowered to 0V, and then raised to, for example, 5V. At the same time, the array recall signal AR is set to high level to turn on the transistor _Q8 . At this time, transistor Q ₇ is in the off state, so for SRAM cell CL ₁ , the load capacitance on node N ₁ side is reduced by the amount of capacitor C ₁ to node N ₂
larger than the side load capacity. Therefore, the node _N1 with a large load capacity becomes a low level, and the node _N2 with a small load capacity becomes a high level. Conversely, electrons are extracted from the floating gate.
When recalling the data of the E ² PROM cell CL ₂ to the SRAM cell CL ₁ , the transistor Q ₇ is in the on state. Therefore, in this case, if the capacitance of capacitor C ₂ is set larger than that of capacitor C ₁ , the load capacity on the node N ₂ side will be larger than the load capacity on the node N 1 side, and as a result, the load capacity on the node N ₁ side will be larger than the load capacity on the node N ₁ side. becomes high level, and node _N2 becomes low level.

The memory modules CM ₁ and CM 2 of the E ² PROM cell CL ₂ shown in FIG. ₁ are composed of a semiconductor substrate and a metal layer, such as a polysilicon layer. For example, electrodes E ₁ and E ₄ are formed by separate N-type impurity diffusion regions in a P ^-type semiconductor substrate, and the floating gate is connected capacitively, that is, via an insulating film, above these N-type impurity diffusion regions. has been done. Also,
Electrodes E ₂ and E ₅ are electrically connected to each other and also capacitively connected above the N-type impurity diffusion region. Furthermore, part or all of the insulating film between the electrodes E ₄ and E ₆ is made extremely thin to enable the tunneling phenomenon. Therefore, the data of SRAM cell CL ₁
E ² When storing in PROM cell CL ₂ , electrode E ₁ ,
A voltage close to V _HH is applied to one of E ₄ , but in this case, electrons from within the substrate are transferred to N as an electrode.
The potential of the electrode E ₁ or E ₄ decreases over time due to junction leakage. As a result, the voltage between the electrodes E ₄ and E ₆ during storage also decreases, reducing the tunneling efficiency, resulting in a problem in that the storage efficiency of the E ² PROM decreases. Also, electrons move between _{E 4} and E ₆ due to the tunnel effect _.
Reduce the voltage between

OBJECT OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to improve the storage efficiency of an E ² PROM that utilizes the tunneling phenomenon.

Structure of the Invention In order to achieve the above- ^mentioned object, the write voltage V _HH
By means of this, when the voltage V _HH reaches 0 V after the first increase, the potential of the electrode E ₁ or E ₄ changes from 1 to 1 to the negative voltage side due to junction leakage. In this case, even if the gate voltage of transistor Q ₅ or the gate voltage of transistor Q ₆ is 0 V, the voltage of electrode E ₁ or E ₄ as the drain of transistor Q ₅ or Q ₆ is the threshold. It will be lower than the voltage. As a result, transistor Q ₅ or Q ₆ turns on and current flows, and eventually the potential of electrode E ₁ or E ₄ recovers to about -0.4 to -0.7V. Therefore, when the voltage increases from the second time onwards, The tunnel efficiency is improved by the amount of recovery.

Embodiments of the Invention Embodiments of the present invention will be described with reference to the drawings from FIG. 2 onwards.

FIG. 2 is an overall configuration diagram of NOVRAM including a nonvolatile semiconductor device as an embodiment of the present invention.
In FIG. 2, 1 is the memory cell CL ₁ of FIG.
_CL2 is a memory cell array provided at the intersection of each word line _Wi and each bit line pair Bj _{, j} . 2
is an address buffer that receives an X address signal A _i (i=0 to n), 3 is an X decoder, 4 is an address buffer that receives a Y address signal A _i ′ (i=0 to n), and 5 is a Y Decoder, 6 is a Y gate that selectively connects the sense amplifier 7 from SRAM and write enable circuit 8 to SRAM to memory cell 1, 9 is an output buffer for output data D0, 10
is the input buffer of input data DI. 11 is a chip select signal, a write enable signal for SRAM, a store signal for E ² PROM, and an array recall signal for E ² PROM.
This is a mode select circuit that receives AR and selects an operating mode.

In other words, during storage (ST="1"), the mode select circuit 11 selects the boost circuit 12, timer 1,
3. Put the counters 14 into operation at the same time. Then, the booster circuit 12 uses the internal clock to
A voltage of 25V V _HH is sent to E ² PROM cell CL ₂ , but
At this time, the timer 13 is activated for a predetermined period of time, for example.
After counting 5 msec, the supply of the internal clock to the booster circuit 12 is stopped and _VHH is temporarily set to 0V. after that,
The booster circuit 12 again outputs a voltage V _HH of 20 to 25V.
E ² Send to PROM cell CL ₂ . The above repeated operations are counted by the counter 14.
When the count is counted twice, for example, a store reset signal is sent to the mode select circuit 11 as a count-up signal. As a result, from the SRAM cell
The data store operation to the E ² PROM cell is completed.

On the other hand, when the array recall signal AR becomes "1"(="0"), the mode select recall circuit 15 is brought into operation. As a result, array recall signal AR turns on transistor Q ₈ (FIG. 1) of E ² PROM cell CL ₂ and also operates V _CC switch 16 . This V _CC switch 16 changes the data of the E ² PROM cell CL ₂ by once setting the voltage V _CCC to 0V and then returning it to 5V.
This causes SRAM cell CL ₁ to be recalled.

In addition, in the above embodiment, the power supply voltage at the time of storing, that is, writing to the E ² PROM cell.
Although V _HH is repeated twice with a duration of 5 msec, the duration can be changed and the number of repetitions can be increased to three or more.

Effects of the Invention FIGS. 3A and 3B are graphs for explaining the effects of the present invention. In Figure 3 A and B, V _N3 ,
V _N3 ′ is the node in Figure 1 when transistor _Q6 is off.
The potential of N ₃ is V _N3 when there is no tunneling phenomenon between the electrodes E ₄ and E ₆ , and V _N3 ′ when there is a tunneling phenomenon. V _F and V _F ′ are the potentials of the floating gate, and again, if V _F does not have a tunneling phenomenon between electrodes E ₄ and E ₆ , V _F ′ indicates that there is no tunneling phenomenon between electrodes E ₄ and E ₆ . Indicates a certain case. As mentioned above, when there is a tunneling phenomenon, the potential at node _N3 becomes V _N3 →
The potential of the floating gate decreases to V _N3 ′, and the potential of the floating gate increases from V _F to V _F ′ by that amount. In this way, for example, if the initial floating gate potential is −
3V, the potential of the floating gate after applying V _HH (22V) for 10msec is +1.2V,
This means that data has been rewritten.

FIG. 3B is according to the present invention. In other words,
V _HH (22V) of 5 msec was applied twice. When there is a tunneling phenomenon, the potential of the floating gate is about +1V after the first application of V _HH , but
After the second application of V _HH , the potential of the floating gate becomes +2.6V, which is a significant improvement compared to +1.2V in the conventional case of FIG. 3A.

The above-mentioned effect is exactly the same when it comes to compensating for the drop ⁱⁿ V _N3 due to juncture leak that occurs when writing to the E ² PROM, and it is possible to prevent a drop in the tunneling efficiency of the E ² PROM. Efficiency can be improved.

[Brief explanation of the drawing]

Figure 1 is a typical NOVRAM cell circuit diagram.
FIG. 2 is a block circuit diagram showing the overall configuration of a NOVRAM including a nonvolatile semiconductor memory device as an embodiment of the present invention, and FIG. 3 is a timing diagram illustrating the effects of the present invention. _CL1 : SRAM cell, _CL2 : ^E2 PROM cell, _E1 :
Electrode (first electrode area), E ₂ : electrode (high voltage application electrode), E ₃ : electrode (floating gate),
E ₄ : Electrode (second electrode area), E ₅ : Electrode (high voltage application electrode), E ₆ : Electrode (floating gate),
_Q5 , _Q6 : switching transistor, 12: booster circuit, 13: timer, 14: counter.

Claims (1)

[Claims] 1. An impurity diffusion region provided in a semiconductor substrate and having a conductivity type opposite to that of the substrate is used as one electrode E ₄ , and an electrode provided opposite to the impurity diffusion region E ₄ is used as the other electrode. _E6 , a tunnel capacitor that causes a tunnel phenomenon between the electrodes, an auxiliary capacitor having one electrode connected to the other electrode of the tunnel capacitor, and a common connection between the tunnel capacitor and the auxiliary capacitor. A write voltage V _HH is capacitively coupled between the MIS transistor Q ₇ for data reading with a floating gate connected to a point, and the one electrode E ₄ of the tunnel capacitor and the other electrode of the auxiliary capacitor. Write circuits 12, 13, which inject or discharge charges into or out of the floating gate by utilizing the tunneling phenomenon in the tunnel capacitor caused by the applied voltage.
14, _Q6 , wherein the capacitance value of the tunnel capacitor is smaller than the capacitance value of the auxiliary capacitor, and the write circuit is configured to: Means 12, 13, 1 for applying write voltage V _HH multiple times
4, and one electrode E ₄ of the tunnel capacitor.
and a means _Q6 connected to the write voltage V _HH to temporarily conduct when the write voltage V HH is lowered to suppress potential fluctuations in the impurity diffusion region due to juncture leakage in the impurity diffusion region. Non-volatile semiconductor memory device.