JPH0318228B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an image processing method, and particularly relates to a first and a second image processing method.
An image processing method that generates an image by shifting one image stored in a frame memory by a predetermined amount relative to the other and performing a predetermined calculation between the first and second images in the overlapping portion. Regarding.

<Prior art> A first image stored in a first frame memory is shifted horizontally and/or vertically relative to a second image stored in a second frame memory, and the first image is overlapped with the second image stored in a second frame memory. There is image processing in which an image is generated by performing predetermined arithmetic processing between first and second images of a rectangular portion, and a desired result is obtained using the image portion obtained by the arithmetic operation.

By the way, in order to perform such processing, it is necessary to determine which parts of the generated image are useless parts and which parts are useful parts, in other words, which parts need to be subjected to image processing. The processing device that performs the processing must be easily recognizable.

<Problems to be Solved by the Invention> However, conventionally it has not been possible to distinguish which parts are useless parts and which parts are useful parts by simple processing.

From the above, the purpose of the present invention is to
Moreover, by high-speed processing, it is possible to distinguish which parts are useless parts and which parts are useful parts, and furthermore, it provides an image processing method which can give the image itself features that can be distinguished. That's true.

<Means to solve the problem> FIG. 1 is a block diagram of an image processing apparatus.

11, 21, and 31 are first, second, and third frame memories; 12, 22, and 32 are serial access memories (SAM); 13, 23 are address counters; 41 is an arithmetic unit; 42 is a horizontal width register; 43 is a vertical width register, 45 is a horizontal scan counter, and 46 is a vertical scan counter.

<Operation> Shifts the first image stored in the first frame memory 11 in the horizontal and/or vertical direction relative to the second image stored in the second frame memory 21, and When performing predetermined arithmetic processing between the first and second images of a rectangular part that is connected, and making the image part composed of the calculation result useful and the other part useless, the useless image part is stored. It is possible to write all null data (NULL data, usually logic "0") into the storage area of the third frame memory 31.

In this way, a processing device that processes the image later can easily identify which parts are useful and which are useless.

<Embodiment> FIG. 1 is a block diagram of an image processing apparatus implementing the present invention.

11, 21, and 31 are first, second, and third frame memories; 12, 22, and 32 are serial access memories (SAM); 13, 23 are address counters; 41 is an arithmetic unit; 42 is a horizontal width register; 43 is a vertical width register, 45 is a horizontal scan counter, and 46 is a vertical scan counter.

The first and second frame memories 11 and 21 respectively store first and second images, and the third frame memory 31 stores images generated using the first and second images. It has a size of ×256.

Address counters 13 and 23 have capacities that indicate memory scan positions in the horizontal and vertical directions, respectively.
256 horizontal counters 13a, 13b; 23a, 2
3b.

The serial access memories 12 and 22 transfer one horizontal line of image data from the first and second frame memories 11 and 21 indicated by the vertical counters 13b and 23b, and output image data from the address indicated by the horizontal counters 13a and 23a. do.

The serial access memory 32 writes data to the address indicated by the horizontal counter 13a of the address counter 13, and every time one horizontal scan is completed, the contents are written to the line of the third frame memory 31 indicated by the vertical counter 13b of the address counter 13. Transferred in parallel.

Arithmetic unit 41 is serial access memory 1
The image data of one pixel input from 2 and 22 is sequentially subjected to predetermined arithmetic processing and output.
Note that the arithmetic processing includes logical OR, logical product, exclusive OR, and other operations, and the type of operation to be performed is separately instructed.

The operation shown in FIG. 1 will be explained below.

Note that the first image IM ₁ (see FIG. 2A) stored in the first frame memory 11 is replaced by the second image IM 2 stored in the second frame memory ₂₁ .
The overlapping rectangular portions are shifted in the horizontal and/or vertical directions relative to the
A predetermined calculation process is performed between the first and second images of OP, and the image part IM _E (see the shaded area in Figure 2 B) composed of the calculation results is designated as useful, and the rest is designated as useless image part IM _N. do. Then, all null data (NULL data, usually logic "0") is written in the storage area of the frame memory 31 that stores the useless image part IM _N , and the above-mentioned operation is written in the storage area that stores the useful image part IM _E. The results shall be memorized.

In advance, among the four corner points of the rectangular part OP, the point P _S that is scanned earliest by raster scan
horizontal and vertical positions in the first and second frame memories of address counters 13 and 23;
Each is stored in b. In addition, in the example of Figure 2, H ₁
=H _S , V ₁ =V _S ; H ₂ =0, V ₂ , =0. or,
The horizontal width H _A and vertical width V _A of the rectangular portion OP are stored in the horizontal width register 42 and the vertical width register 43, respectively. Furthermore, H _A >0, V _A
>0, a low level (logic "0") is output. Therefore, the AND gate 44a is initially open.

When a request for image generation occurs in this state, the first image for one horizontal line at the vertical positions V ₁ and V ₂ indicated by the vertical counters 13b and 23b,
The second image data is read into serial access memories 12 and 22, respectively.

Next, one pixel worth of image data is input to the arithmetic unit 41 from the addresses in the serial access memories 12 and 22 indicated by the horizontal counters 13a and 23a, respectively.

Arithmetic unit 41 is designated separately. Arithmetic processing is performed using the input image data, and the result of the calculation is output.

Serial access memory 32 is AND gate 4
The calculation result input via 4a is stored at the address indicated by the horizontal counter 13a of the address counter 13.

When the above processing is completed, each horizontal counter 13
a and 13b count up the contents by one (H ₁ +1→H ₁ , H ₂ +1→H ₂ ), and the horizontal width register 42 counts down the contents by one (H _A -1→H _A ). Further, the horizontal scan counter 45 having a capacity of 256 counts up its contents _CH (however, the initial value of _CH is zero).

Thereafter, similar processing is repeated and the calculation results are stored in the serial access memory 32 in sequence.

Then, when the above process is repeated H _A times, the content of the horizontal width register 42 becomes zero, and its output becomes high level "1". As a result, the output of the AND gate 44a becomes "0" via the OR gate 44b and the NOT gate 44c. At this time, the content of the horizontal counter 13a is 0, and the content of the horizontal counter 23 is 0.
The content of a is H _A , and the content _CH of the horizontal scan counter 45 is H _A . As a result of the above, the calculation results are stored in addresses 255 to _HS of the serial access memory 32.

Thereafter, the above process is repeated until C _H =0, in other words, until one horizontal scan is completed, but regardless of the calculation result, the output of the AND gate 44a is at a low level (logic "0"), so "0'' are sequentially written from address 0 to address (H _S -1) in serial access memory 32.

Then, when C _H =0, in other words, when one raster scan is completed, the vertical width register 4
Contents of 3 V _A is counted down by 1, and
H _A is set in the horizontal width register 42 again. As a result, AND gate 44a opens.

Also, if _CH = 0, the vertical counters 13b, 2
The content of 3b increases by 1 count (V ₁ +1→V ₁ ,
V ₂ +1→V ₂ ), and the content CV of the vertical scan counter ₄₆ is also incremented by 1 (however, _CV
The initial value of is zero). At this time, the horizontal counter 13a
The content of is H _S and the content of the horizontal counter 23a is 0.

Thereafter, the above process is repeated until V _A =0.

When V _A =0, the image of the portion 31a enclosed by the dotted line in FIG. 2B has been generated and stored in the third frame memory 31. and,
Thereafter, until the content C _V of the vertical scan counter 46 becomes zero, in other words, until the scanning of one frame is completed, the output of the vertical direction width register 43 becomes high level, and the output of the AND gate 44a becomes "0".
It becomes permanent.

In addition, when V _A = 0, the horizontal counter 1
The content of 3a is H _S , the content of horizontal counter 23 a is 0, the content of vertical counter 13 b is 0, the content of vertical counter 23 b is V _A , the content of horizontal width register 42 is H _A , the content of horizontal scan counter 45 is 0 ,
The content V _V of the vertical scan counter 46 has become V _A.

Thereafter, the above process is repeated until C _V =0, in other words, until the scanning of one frame is completed, but regardless of the calculation result, the AND gate 44a
Since the output of is low level (logic “0”),
“0” is sequentially written into the serial access memory 32 and then stored in the storage area of the third frame memory 31.

Image data that has been subjected to arithmetic processing as described above
NULL data "0" will be stored in storage areas other than the storage area for storing IM _E (see diagonal lines in FIG. 2B).

Therefore, when the processing device subsequently performs a predetermined process on the image stored in the frame memory 31, it can easily distinguish between useless portions and useful image portions.

Figures 3 to 5 are the first image IM ₁ and the second image
These are various examples in which the relative shift direction of IM ₂ is changed, and the same parts as in FIG. 2 are given the same reference numerals.

<Effects of the Invention> According to the present invention, the first image stored in the first frame memory is horizontally and/or When shifting in the vertical direction and applying a predetermined calculation process between the first and second images of the overlapping rectangular parts, the image part composed of the calculation result is useful and the other image part is useless. , all null data (usually logic "0") is written in the memory area that stores useless image parts, so the processing device that processes the image later can easily identify which parts are useful and which are useless. This has made it possible to perform image processing more efficiently.

Further, according to the present invention, the first and second image data for one horizontal line are read out to the serial access memory respectively, and the image data is sequentially read from each serial access memory and input to the logic operation section, and the logic operation is performed. Since the results are stored in the third serial access memory and the contents of the third serial access memory are stored in the third frame memory, images can be generated by high-speed processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image processing apparatus implementing the present invention, and FIGS. 2 to 5 are explanatory diagrams of the image processing of the present invention. 11, 21, 31...Frame memory, 12,
22, 32... Serial access memory, 13,
23...address counter, 13a, 23a...
Horizontal counter, 13b, 23b... Vertical counter, 41... Arithmetic unit, 42... Horizontal width register, 43... Vertical width register, 45...
...Horizontal scan counter, 46...Vertical scan counter.

Claims (1)

[Claims] 1. The first frame memory stored in the first frame memory.
is shifted in the horizontal and/or vertical direction relative to the second image stored in the second frame memory, and the first,
In an image processing method that generates an image by performing predetermined arithmetic processing between second images, a first point of the four corner points of the rectangular portion that is scanned earliest by raster scan;
The first and second addresses in the second frame memory, the horizontal width and the vertical width of the rectangular portion are set, and one horizontal line corresponding to the vertical address included in the first and second addresses is set. The first and second image data of the image data are read into the first and second serial access memories, respectively, and the image data are sequentially read from the positions in each serial access memory indicated by the horizontal addresses included in the first and second addresses. Performs a predetermined calculation, stores the calculation result in the third serial access memory, and determines whether the horizontal reading width of the image data read from the first and second serial access memories exceeds the set horizontal width. If the horizontal scanning width exceeds the set horizontal width, null data is stored in the third serial access memory until one horizontal scan line is completed, and one horizontal scan cycle is completed. Upon completion, the contents of the third serial access memory are stored in the third frame memory, the vertical positions of the first and second addresses are advanced by one, and the above process is thereafter carried out from the first and second frame memories. Repeat until the vertical scanning width of the scanned image data exceeds the set vertical width. If it exceeds the set vertical width, null data is stored in the third frame memory until the raster scan cycle for one screen is completed. An image processing method characterized by memorization.