JPH0318120A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To prevent a propagation delay time and power consumption from increasing by providing a 1st FET between the base of a bipolar transistor(TR) and an output terminal and a 2nd FET which is controlled with the potential of a low-level means between the base and a potential determination part. CONSTITUTION:When inputs VI1 and VI2 are both 'H', an NMOS input part 120 is ON and an output 161 is 'L'. A PMOS input part 110 is OFF and an NMOS potential determination part 130 is ON. The low level means 140 turns on an NMOS 133 weakly to discharge the base potential, so that the bipolar TR 162 turns OFF. When only the VI1 varies to HL, the input part 120 turns OFF and a bipolar element 103 turns OFF. The potential determination part 130 is OFF and the input part 110 is ON. The TR 162 turns ON and the output 161 goes up to 'H'. Then the low level means 140 turns on a PMOS 150 to raise the output 161 to VDD, thereby preventing the propagation delay time and power consumption of a following-stage logic circuit from increasing. The PMOS 150 discharges the base charges of the bipolar element 182 to limit a current flowing through the potential determination part 130 and the rise time of the output 161 is shortened. This circuit operates similarly even at the time of other state transition of the VI1 and VI2, which is effective.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention provides a B i -C device in which a MOS transistor and a bipolar transistor are mixed on the same semiconductor substrate.
The present invention relates to a MOS (Pi-Si-MOS) type semiconductor logic circuit.

(Prior art) Conventionally, as a technology in this field, Japanese Patent Application Laid-Open No. 59-1
In addition to those described in Publication No. 103, there were, for example, the following. The structure will be explained below using diagrams.

FIG. 2 is a circuit diagram showing an example of the structure of a conventional semiconductor logic circuit.

This semiconductor logic circuit is used as a NAND circuit, and has an input terminal l for a first input potential Vil,
Its input terminal 1 is connected to a first input section 10 .

Furthermore, the input terminal 2 for the second input potential Vi2 is connected to the second input potential Vi2.
is connected to the input section 2o. The first input unit 10 is
It is composed of a P-channel MOS transistor (hereinafter referred to as PMOS) 1l and PMOS 12, and the second input section 20 is composed of an N-channel MOS transistor (hereinafter referred to as NM).
It is composed of an OS 〉2↓ and an NMOS 22. The output SIO,S of the first and second input parts 10.20
20 are respectively connected to the output section 3o.

The output section 30 connects an NP between the power supply potential VDD and the ground potential GND via an output terminal 3l for the output potential Out.
N transistors 32 and 33 are connected in series, and NMOSs 41 and 42 for discharging and a resistor 43 are connected between the bases of the transistors 32 and 33 and the ground potential GND, respectively.

The operation of this circuit is as follows.

For example, an input potential V of the ``H'' level is applied to the input terminals 1.2.
When il and Vi2 are respectively input, the output SIO of the input section 10 becomes the "L" level, and the output S20 of the input section 20 becomes the "H" level.

As a result, transistor 32 is turned off and transistor 32 is turned off.
3 is turned on, the output potential OUT of the output terminal 3l becomes a level.

This Bi-MOS semiconductor logic circuit has the advantages of low power consumption of a CMOS logic circuit and high speed of a bipolar logic circuit.

(Problems to be Solved by the Invention) However, the semiconductor logic circuit having the above configuration has the following problems.

(1) The output potential out changes from “LIT level” to “H” level.
” level, the charging current that charges the load capacitance is high at the beginning of the transition, so the base resistance of the transistor 32 is small. However, at the later stage of the transition, the charging current that charges the load capacitance becomes small. , transistor 32
On the contrary, the base resistance of will increase. Therefore, the transistor 32 is in a cut-off state, and the output voltage out does not rise to the power supply potential VDD. This causes a problem in that the propagation delay time increases in the next stage CMOS logic circuit (not shown), and a through current flows through the CMOS logic circuit, resulting in an increase in power consumption.

(2) Furthermore, the output potential out changes from the "L" level to '
When transitioning to the "H" level, a through current flows through the NMOS 4142 and the rise of the base potential of the transistor 32 is delayed, resulting in an increase in propagation delay time, and it has been difficult to solve these problems. .

The present invention provides a semiconductor logic circuit that solves the problems of the prior art in that propagation delay time and power consumption increase.

(Means for Solving the Problem) In order to solve the problem, the present invention provides a first and a second step that input at least one input potential and mutually cooperate to take the logic of the input potential. an input section, and first and second bipolar transistors connected in series via an output terminal, the base of the first bipolar transistor being connected to the output of the first input section, and the base of the first bipolar transistor connected to the output terminal of the second bipolar transistor. an output section in which the bases of the transistors are respectively connected to the outputs of the second input section, and the conduction states of the L second bipolar transistors are controlled in a complementary manner by each base potential; and the first bipolar transistor. The semiconductor logic circuit is equipped with a potential determining section that determines the potential of the base of the semiconductor logic circuit, and the following measures are taken.

the base of the first bipolar transistor and the first bipolar transistor
a first MOS transistor connected between the output terminal side electrode of the bipolar transistor and whose conduction state is controlled based on the potential of the electrode; and a first MOS transistor that outputs a predetermined potential based on the potential of the output terminal. a second MOS type transistor connected between the potential determining section and the base of the first bipolar transistor, the conduction state of which is controlled based on a predetermined potential of the low level means; It was established.

(Function) According to the present invention, since the semiconductor logic circuit is configured as described above, the first MOS type transistor works to raise the potential of the output terminal to the power supply potential.

The low level means controls the conduction state of the second MOS type transistor, the second MOS type transistor
works to discharge the charge at the base of the bipolar transistor.

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram of a semiconductor logic circuit showing an embodiment of the present invention.

This semiconductor logic circuit has an input terminal 100 for a first input potential VII, and the input terminal 100 has a
are commonly connected to the input sections 110 and 120 of the two. The first input section 110 includes PMOS1 1 1 and PMOS1 12 whose gates are connected to the input terminal 100, and includes PMOS111 and PMOS112 whose gates are connected to the input terminal 100.
Each source of MOS111 and 112 is connected to the power supply potential VDD,
Each drain is connected to the output node N1. Further, the gate of the PMOS 112 is connected to the input terminal lot for the second input potential VI2, and is also connected to the second input section 120.

The second input section 120 includes NMO8 1 21.122 whose gates are respectively connected to the input terminals 100 and 101.
and the source of NMOS 121 is NMOS 1 2
The drain of NMOS 121 is connected to the output node N2. The output side node N2 is connected to the ground potential G via the discharge resistor l23.
Connected to ND. In addition, input terminal 100.101
are connected to the potential determining section 130, respectively.

The potential determining unit 130 is a circuit that determines the potential of the node Nl, and includes NMOSs 131 and 132 to which input terminals 100 and 101 are connected, respectively. NMOS1 3
1, the drain is connected to the source of NMOSI32, the source is connected to the ground potential GND, and NMOS13
The drain of N2 is the second MOS transistor.
Connected to the source of MOS133. moreover,
The drain of the NMOS 133 is connected to the node N1, and the gate is connected to the low level means 140, respectively.

The low level means 140 is an NMOS
This is means for generating a voltage higher than the threshold level voltage of the low level generating circuit 141. MOS1
42, and an inverter 43.

FIG. 3 is a circuit diagram showing an example of the configuration of the low level generating circuit 141 in FIG. 1.

This low level generation circuit 141 has terminals Tl, T2, T3.
It is composed of a PMOS 141a having the following characteristics. Its terminal Tl, the drain of PMOS142, and NMO813
3 gates are connected at node N3, respectively,
Furthermore, the terminal T2 of the low level generation circuit 141 is connected to the ground potential GND, and the source of the PMOS 142 is connected to the power supply potential VD.
Each is connected to D. The gate of PMOS 142 is connected to PMOS 1, which is a first MOS type transistor.
50 and the input side of the inverter 140, and the output side of the inverter 140 and the terminal T3 of the low level generation circuit 141 are respectively connected to the output terminal 161 of the output section 160.

The output section 160 has a power supply potential VDD and a ground potential GND.
NPN transistors 162 and 163, which are first and second bipolar transistors, are connected in series between them, respectively, via an output terminal 161 for output potential OUT. The base of the transistor 162 is connected to the node N1, the collector is connected to the power supply potential VDD, and the emitter is connected to the output terminal 161.
and the drain of the PMOS 150, respectively. Furthermore, a transistor 163 is connected to the output terminal 161.
Its collector is connected to the ground potential GND, and its emitter is connected to the ground potential GND.

FIG. 4 shows the voltage characteristics of the node N3 with respect to the output potential OUT, and FIG. 5 shows the characteristics of the NMOS 133. The operation of FIG. 1 will be explained with reference to FIGS. 4 and 5.

(A) When the input potentials VII and VI2 are both at the ``H'' level, the NMOSs 121 and 122 are turned on, and if the potential of the output terminal 161 is higher than the forward voltage VBE between the base and emitter of the transistor 163, the transistor 1
63 is turned on, and the output potential OUT of the output terminal 16l decreases. After that, the output potential OUT becomes the forward voltage VBE
When the voltage is below, the transistor 163 enters the cut-off state, but since it continues to be discharged through the resistor 121, the output potential OUT decreases to the ground potential GND and becomes the "L" level.

At this time, both PMOS III and 112 are off, but both NMOS 131 and 132 are on. Furthermore, since the input of the inverter 43 is at the 11 L I+ level, its output is at the II H II level,
PMOS 142, 150 are in the off state. However,
Since the output potential OUT is at the "L" level, the low level generation circuit 141 generates a low level voltage at the node N3, as shown in FIG. 4, which is lower than the power supply potential VDD and higher than the threshold level voltage of the NMOS. Therefore, NMOS13
3 is in a weak on state as shown in FIG.
It is discharged through a path of 131. Therefore, transistor 162 is in an off state.

(B) When only the input potential VII transitions from the II H II level to the "L'" level, the NMOS 121 is turned off, and the transistor 163 is turned off because the base charge is discharged through the resistor 123.

Furthermore, NMOS131 is turned off, but PMOSIII
turns on. On the other hand, the PMOS 150 has an output potential OUT
is in an off state while it is at the "L" level. At that time, the base potential of the transistor 162 increases, so the transistor 162 is turned on. As a result, the output potential OUT becomes 11}{I+ level. After that, inverter 1
Since the output of 43 becomes "L" level, PMOS 1
50 is turned on, and the output potential OUT is pulled up to the power supply potential VDD. Also, the potential of node N3 is 17 H I
At the T level, the NMO 813B is turned on and ready to immediately respond to the next transition of the input potentials VI1 and VI2.

By the way, input potential VI2 only or input potential VII
, VI2 simultaneously goes from 11 8 I+ level to 11 1
Even when transitioning to the I1 level, the same operation as above is performed.

(C) When the input potential VI2 is at the II Hu level and the input potential VII transitions from the IIL'' level to the ``H'' level, both PMOS III and 112 are turned off, and NMOS 13
1 and 132 are both turned on. - At this time, since the node N3 is at the "H" level, the NMOS 133 is turned on and the transistor 162 is turned off. However, NMOS121
, 122 are both on, so the transistor 163
turns on.

Therefore, the output potential OUT becomes the "earth" level.

At the initial stage when the input potential VI2 transitions from the "L'" level to the II H I+ level, the output voltage OUT is at the "Hll" level, so the node N3 remains at the "H" level. As a result, the NMO8133 is in the on state. Therefore, the base charge of the transistor 162 is discharged in a short time.

In the latter period when the input potential VI2 transitions from the "L++ level" to the "''HT+ level, the output potential OUT is at the "L" level, so the output of the inverter 143 is at the "H'' level.Therefore, the PMOSs 133 and 150 are turned off. However, the potential of node N3 becomes ``''Ln level. As a result, N
MO8133 is in a weak on state and transistor 16
The base potential of No. 2 drops to the ground potential GND. N
When the gate potential of MO8133 is set to ground potential GND, NM08133 is cut off, but PMOS15
If the timing at which the transistor 0 is turned off is later than the timing at which the NMOS 133 is turned off, charge remains at the base of the transistor 162. By turning NMOSI 33 into a weak on state, the base charge of transistor 162 can be discharged.

By the way, when the input potential VII is at the "H" level and the input potential VI2 transitions from the "゜L゜゛ level to the "H" level, the input potentials VII and VI2 simultaneously become "t, II
It operates in the same way even when the level transitions from the "Hll level".

This embodiment has the following advantages.

<1> Figure 6 is a waveform diagram of the output potential OUT, and PM
Output potential O depending on the presence or absence of OS150 and NMOS133
This shows the startup state of the UT. Here, waveform A is when both PMOS 150 and NMOS 133 are provided, waveform B is when only PMOS 150 is provided, and waveform C is when neither PMOSI 50 nor NMOS 133 is provided. As shown in Figure 6, PMOS150
By using
can be raised up to. This can prevent increases in propagation delay time and power consumption of the CMOS logic circuit, which is the next stage circuit.

(2> Figure 7 is a waveform diagram of the drain current of NMO8131, and shows the magnitude of the through current depending on the presence or absence of PMOS150 and NMOSI33. Here, waveform A is the waveform when both PMOS150 and NMOS133 are provided. Waveform B is when only PMOS 150 is provided, and waveform C is when neither PMOS 150 nor NMOS 133 is provided.As shown in FIG.
By using this, it is possible to limit the through current flowing between the NMOSs 131 and 132. Therefore, that amount can be supplied as the base current of the NPN transistor 162, and the rise delay time of the output potential OUT can be improved.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following variations.

(I> In the above embodiment, the PMOS 141a is used for the low level generating circuit l4■, but it is also possible to configure the PMOS in multiple stages, for example.

(n) In the above embodiment, a two-manpower NAND gate is used, but it is also possible to use an inverter, a multi-input NAND gate, or a NOR gate. In this case, P constituting the first input section 1lO
MOS, second input section 120 and potential determining section 130
It is necessary to provide NMOS constituting the NMOS corresponding to the number of input potentials.

However, when constructing a NOR gate, the first input section 1
10 PMOSs are connected in series, and the second input section 1
20 and the NMOS forming the potential determining section 130 need to be connected in parallel.

(Effects of the Invention) As explained in detail above, according to the present invention, when the potential of the output terminal reaches the level of "Hl+", the first MOS
Since the type transistor is turned on and the potential of the output terminal is raised to the power supply potential, an increase in propagation delay time and power consumption of the next stage logic circuit can be prevented.

Furthermore, since the first MOS transistor is provided and the base charge of the first bipolar transistor is discharged, the through current flowing to the potential determining section can be restricted, and the rise time of the output terminal potential can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor logic circuit showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional semiconductor logic circuit, and FIG. 3 is a circuit diagram of the low level generation circuit 141 in FIG. Figure 4 is a waveform diagram of the potential characteristics of node N3 in Figure 1, and Figure 5 is a waveform diagram of the potential characteristics of node N3 in Figure 1.
The characteristic waveform diagram of NMOS 133 in the figure, Figure 6 is
The waveform diagram of the output potential OUT in the figure, Figure 7 is the waveform diagram of the output potential OUT in Figure 1.
It is a drain current waveform diagram of MO813l. 110.120...First and second input sections, 13
0...Potential determination unit, 140...Low level means, 150, 133...First. second MO
S-type transistor, 160...Output section, 161
...Output terminal, 162...First bipolar transistor, l63...Second bipolar transistor, Nl, N2. N3... Node, VII, VI2... 1st. Second input potential, OUT...output potential, VDD...potential power supply, GND...ground potential. -330 VDDl 32 Hal l1 pull - -130- Younger brother 1 Figure 3 Figure 4 Figure 5 Waveform diagram of toru-inance voltage NMQSI33

Claims (1)

[Claims] First and second input sections which input at least one or more input potentials and cooperate with each other to take the logic of the input potentials, and a second input section connected in series via an output terminal. 1, a second bipolar transistor, the base of the first bipolar transistor being connected to the output of the first input section;
an output section in which the bases of the bipolar transistors are respectively connected to the outputs of the second input section, and the conduction states of the first and second bipolar transistors are controlled in a complementary manner by each base potential; a semiconductor logic circuit comprising: a potential determining section that determines a potential of a base of a bipolar transistor;
a first MOS transistor connected between the output terminal side electrode of the bipolar transistor and whose conduction state is controlled based on the potential of the electrode; and a first MOS transistor that outputs a predetermined potential based on the potential of the output terminal. a second MOS type transistor connected between the potential determining section and the base of the first bipolar transistor, the conduction state of which is controlled based on a predetermined potential of the low level means; A semiconductor logic circuit characterized by being provided with.