JPH03181094A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To suppress the parasitic capacity of a column select signal line and the current consumption of a read circuit to be increased by enlarging the capacity of a memory by controlling the read circuit and a write circuit by the output of a control signal generating circuit which defines the output of a decoder circuit for column selection as one part of the input. CONSTITUTION:Near a read circuit 5 and a write circuit 6 in a memory cell sub array 2, control circuits 7 and 8 for these circuits 5 and 6 are provided and a column select signal YS is connected to the source of an MOS transistor M3 of these control circuits 7 and 8. Therefore, since the parasitic capacity of the column select signal line YS is decreased rather than the input to the gate of the MOS transistor M3, the starting time and ending time of the column select signal line YS can be shortened. Further, since the plural read circuit 5 and write circuit 6 are selectively operated, a current to flow to a lot of circuits in an unselected state is suppressed to 0. Thus, it is suppressed to increase the parasitic capacity of the column select signal line and the current consumption of the read circuit 8 by enlarging the capacity of the memory.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a circuit suitable for increasing the speed and increasing the degree of integration of semiconductor memory devices, and particularly relates to a control circuit for reading and writing to memory cells. It is something.

[Conventional technology]

Among semiconductor memories, in order to shorten access time in semiconductor memories such as static RAM and dynamic RAM, a method has been proposed in which a read circuit and a write circuit are provided separately for each data line pair to which multiple memory cells are connected. ing. Regarding static RAM, IE, Journal of Solid
State circuit volume Nisshi 19 (1
October 1984) pages 572 to 577 (IEEE
, Journal of 5olid-5tate C
1rcuits.

Volume SC-19 (October 1984
．． pp572577).

Also, in the case of dynamic RAM,
There is r163-64690. Figure 2 shows the JP-A-6
FIG. 8 of No. 3-64690 shows a separate type read/write circuit of a dynamic RAM and its related circuits. read circuit, write circuit and column selection signal YS,
1 shows a circuit around a memory cell of a dynamic RAM, which is composed of read and write circuit control signals wc and wc.

1 is a transistor that stores charge in a capacitance, ↓ a capacitor dynamic RAM memory cell, 2 is a memory cell array consisting of multiple memory cells, 1 circuit 3 is a precharge circuit, and selects a memory cell. in front,
The potential of the data lines DL and DL is set in advance to the reference voltage supply line HVC.
This is a circuit that keeps the potential equal to the potential of . Circuit 4 is a memory cell rewriting circuit. This is the cross-linked CMO8
It changes the potential of the common drive lines SAP and SAN of the circuit, amplifies the minute potential difference read from the memory cell to the data line, and rewrites the memory cell. The precharge circuit 3 and the rewrite circuit 4 are circuits unique to DR^A. Reference numeral 5 denotes a reading detection circuit, which detects the potential difference of the data line before the circuit 4 operates and amplifies the data line potential, and connects the sense output line (read common data line) SO
, SO to obtain a differential voltage signal or differential current signal. 6 is a write circuit. Common drive line SA
Since P and SAN drive a large number of circuits 4 and a large number of data line pairs via them, the response is slow, and therefore the amplification of the data line potential by the circuit 4 is also delayed. However, if a readout detection circuit (hereinafter simply referred to as "readout circuit j") 5 is provided, readout can be performed sufficiently quickly without waiting for amplification, as described below.However, for this purpose, It is necessary to advance the selection of the YS line to almost the same time as the selection of the word line, and to place a highly sensitive main amplifier in the subsequent stage.

The operation of this circuit will be explained. Memory cell selection is performed by setting the word line WL to a high potential, and column selection is performed by setting the column selection signal YS to a high potential. first,
In a read operation, data MD is read from a selected memory cell.
A minute differential signal read out to L and DL is detected by a differential amplifier 5 made up of MOS transistors. The MO8 current source of this differential amplifier is turned on by the potential of the column selection signal YS.

Turn off. Even if the phase of the column selection signal YS is faster than the word line, malfunction of the memory will not occur. The drain outputs of the differential amplifiers 5 provided for each column are connected in common to a plurality of columns and sent as sense outputs so, so to subsequent stage circuits. Since the current source of the circuit 5 in the non-selected column is off, the data line signal in the non-selected column does not affect this sense output.

Next, in a write operation, the column selection signal line YS is set to a high potential, and the write control line WC is set to a high potential and WC is set to a low potential, thereby turning on the MOS transistors M1 and M2. In this way, the write data on the common data lines CD, CD is transferred to the data line of the selected column and written into the selected memory cell.

If an attempt is made to realize a large capacity memory with the above configuration, the number of memory cells connected to the data line will increase, and the parasitic capacitance of the data line will increase. As a result, the signal voltage generated on the data line pair decreases, causing information destruction due to a decrease in speed and a decrease in S/N. To prevent this, a so-called multi-division data line method (Japanese Patent Laid-Open No. 198592) has been proposed in which the memory cell array is divided into many subarrays in the data line direction and reading and writing are performed within each subarray. .

However, when a multi-divided data line system is used in a large capacity memory, the number of subarrays increases, so the number of read circuits 5 or write circuits 6, which are load circuits for the column selection signal YS, increases.
The delay time due to the wiring resistance and wiring capacitance of the YS line increases. This causes the problem of reduced read and write operation speeds.6Also, in the multi-division data line system, there is a read circuit and a write circuit for each sub-array, but only the column selection signal YS from the - set of Y decoders is used for each sub-array. When the readout circuits are driven, a problem arises in that current flows through all of the plurality of readout circuits, increasing power consumption.

[Problem to be solved by the invention]

An object of the present invention is to provide a circuit for suppressing an increase in the parasitic capacitance of a column selection signal line YS even when the capacity of a memory increases, and a circuit for suppressing an increase in current consumption flowing through a readout circuit. be.

[Means to solve the problem]

In order to simultaneously achieve the two objectives, the present invention provides the following objectives.

These control circuits are provided near the read circuit and write circuit in each subarray, and the column selection signal YS is connected to the source of the MOS transistor of this control circuit. In this way, only the read circuits and write circuits of a small number of selected subarrays are selectively operated.

[Effect]

By connecting the column selection signal to the source of the MO8I- transistor, the parasitic capacitance of the column selection signal line YS can be reduced more than by inputting it to the gate of the MOS transistor.

This makes it possible to shorten the rise and fall times of YS. If the YS signal line and the word line can be selected at approximately the same time, the data line signal can be detected and the subsequent circuit can be operated without waiting for data line amplification during rewriting, reducing the DRAM access time by about 20 minutes. % (about Ions)
The speed can be increased.

Furthermore, since a plurality of read circuits and write circuits are selectively operated, the current flowing through a large number of unselected circuits can be suppressed to zero, and the power consumption of the entire chip can be reduced.

〔Example〕

Hereinafter, the present invention will be explained in detail using examples.

Note that in the following examples, DRAM will be explained, but
The present invention can also be applied to large-capacity SRAMs to achieve similar effects.

A basic embodiment of the present invention is shown in FIG. 1 is a memory cell of a dynamic RAM, and 2 is a memory cell array in one column connected to a plurality of word lines. 3 is a precharge circuit, and 4 is a rewrite circuit. 5 is a read circuit, and 6 is a write circuit.

The above l'Gil path and its operation are the same as the conventional example shown in FIG. A feature of the present invention is that control circuits 7 and 8 are provided. Reference numeral 7 designates a generating circuit for a control signal YSR for the read circuit, and 8 represents a generating circuit for a control signal YSW for the write circuit. This figure shows one column of data line pairs, but of course a plurality of data line pairs are arranged laterally along the word line. In the multi-division data line system, the above circuit group 2,
3, 4, 5°6.7.8 to form one subarray, and a plurality of subarrays are arranged along the YS line.

In this embodiment, the read circuit and write circuit in each subarray are configured to perform a logical operation using not the YS signal but the ys multiplied signal and other signals to generate a read control signal YSR and a write control signal Y.
It operates in response to SW. YSR and YSW are column selection signal YS, read circuit selection signal RC, and write circuit selection signal W.
Created using C logic operations. RC and WC reflect read/write commands and selection/non-selection information of the subarray, and are arranged perpendicular to the YS line and parallel to the word line.

During a read operation, YSR of the selected subarray is set to a high potential by YS, WC, and RC. Y of unselected subarray
SR and YSW of all subarrays remain at low potential. In this way, the current source M of the readout circuit of the selected subarray
Since the OS transistor M3 is turned on, the differential readout circuit composed of the lMo5 transistors M1 to M3 detects the potential difference between the data lines DL and DL and outputs a sense output so
, so output a differential voltage signal or differential current signal.

During a write operation, YSW of the selected subarray is set to a high potential and YSR is set to a low potential (or may remain at a high potential) by YS, WC, and RC.

At this time, the write data on the common data lines CD, CD is transferred to the transfer MOS transistors M4. It is transferred to data lines DL and DL through M5.

The features of this embodiment are as follows. Since only the readout circuit in the selected subarray and the selected column is operated by YS and RC, the current source MoS transistors of the readout circuits in many unselected subarrays are in the off state, and power consumption can be reduced.

In addition, the read circuit 5 detects a minute potential difference between the data lines and obtains a differential voltage or current signal at the sense outputs so and so before the rewrite circuit 4 operates and the potential of the data lines is amplified. If combined with a high-sensitivity main amplifier using, for example, bipolar in the subsequent stage, high-speed readout is possible. In addition, in the case of writing, the write data is on the common data line CD.

Since the data is transferred from the CD to the data lines DL and DL via one transfer MOS transistor, writing can be performed reliably at high speed.

FIG. 3 shows the control signal YSR generation circuit 7 in the embodiment shown in FIG.
, is an example specifically showing the control signal YSW generation circuit 8. 4 is a timing diagram for explaining the operation of FIG. 3. Six circuits 7 and 8 are CMOS inverter circuits consisting of both P-channel and N-channel type MOS transistors. The source of this circuit is connected to the column selection signal line YS.

In this way, the parasitic capacitance of the YS line is small, and the speed of the YS signal and the circuit driven by it can be increased. The reason for this is that the load capacitance of the YS line is such that many unselected control circuits 7
, 8, M3. M4. This is because the gate capacitance of M5 cannot be seen. M3. in one or a small number of selected subarrays. M4
．． Only the gate capacitance of M5 is added. Generally, the source/drain junction capacitance is about half or less than the gate capacitance, so the parasitic capacitance of ysg is about 172 compared to the case where it is applied to the gates of circuits 7 and 8.

Next, the operation of this circuit will be explained using FIG. 4. For reading, as shown in FIG. 4(a), the selection signal RC of the subarray is set to a low potential and the selection signal WC is set to a high potential. When the 0 column selection signal YS becomes a high potential, the output YSR of the circuit 7 becomes a high potential. Therefore, the current source MOS transistor M3 of the readout circuit is turned on and detects the potential difference between the data, l1tDL, and DL. On the other hand, since the output YSW of one circuit 8 is at a low potential, it is connected to the data lines DL, DL and the common data line CD.

It is separated from the CD. Therefore, read data is not affected.

For writing, as shown in FIG. 4(b), RC is set at a low potential (or it may remain at a high potential as shown by the broken line), and WC
is set to a low potential, and the column selection signal YS is set to a high potential.

At this time, YSW becomes high potential and transfer MOS transistor M4. Since M5 is turned on, the write data on the common data line is transferred to the data lines DL and DL, and writing is performed.

At this time, whether the read circuit operates or not does not affect the write operation.In addition, in the timing diagram (b), it is assumed that the switching of YSW is determined by YS, but W
Of course, it is also possible to control by switching C. This person reads the timing of YS,
There is no need to change by writing, and the single column decoder circuit can be simplified.

Further, the signal RC, which serves both as a read command and as a sub-array selection, as described above, can also be used as the drive signal PC of the precharge circuit 3. This is because PC is also lowered to a low potential in the selected subarray before word line selection. In that case, there is no need to newly provide an RC generation circuit.

FIG. 5 shows another embodiment of the invention. In FIG. 5, only the readout circuit differs from the circuit configuration in FIG. 3, and the rest is the same. In the readout circuit of FIG. 5, a MOS transistor to which a data line signal is input.

The arrangement of the MOS transistors to which the YSR signal is input has been reversed. i.e. MOS)-transistors Ml, M
2 are transistors M3.2 that detect the potentials of the sense output lines so, so and the data line. The transistors M1 and M2, which act as transfer gates with the drain of M4, are controlled by the readout circuit control signal YSR.6 The operation of this embodiment is as follows.
The operation is the same as that shown in the figure, but compared to Figure 3, the transistors M1 and M2 are turned on and off by YSR, so 5O9S
The capacitance of a large number of unselected data lines is not visible from O, the parasitic capacitance thereof can be reduced, and the response of the so and so lines can be made faster.

Fig. 6 shows an example in which the embodiment shown in Fig. 1 is specifically applied to a multi-division data line system.1 This example shows a case where the data line is divided into four, but as the number of divisions increases The effect of the present invention becomes remarkable. 1 is a memory cell, 2 is one of the memory cell sub-arrays, 3 is a precharge circuit, 4 is a rewrite circuit, 5 is a read circuit, 6 is a write circuit, 7 is a control signal generation circuit for the read circuit 5, 8 is a write circuit This is a control signal generation circuit for circuit 6. The above 2 to 8 constitute the niblock 9. Further, blocks 9 to 12 have the same circuit configuration. 13 is a column decoder that generates a column selection signal YS. Blocks 9 to 12 are controlled by this set of Y decoder outputs. 14 to 17 are readout circuit outputs SOi, SO
This is the main amplifier that amplifies the signal of i (i=o~3). This output M o =M a enters the output circuit 18 and finally becomes the data output Dout. The specific configuration of these main amplifiers and output circuits is disclosed in Japanese Patent Application Laid-Open No. 61-170992.
, JP-A No. 62-117190.

In the case of the multi-division data line system shown in this embodiment, there is only one column selection signal YS, but the selection of the read circuit and write circuit is RCi (i=o~3), WCi (i=0~3). and Y
This is done by the logical operation of S.

As shown in FIGS. 3 and 4, the YS line enters the sources of the MOS transistors of the control signal generating circuits 7 and 8. Therefore, even if the number of data line divisions is large, the YS
The parasitic capacitance of the YS line can be reduced compared to the case where the line is input to the gate of a MOS transistor. Therefore, the speed of the YS signal and the circuit driven by the YS signal can be increased.

Next, the operations of the plurality of subarrays will be explained. For reading, one word line is selected in the selected subarray. The readout circuit of the subarray is YS, RCi
(i=o~3), the read data from the memory cell to the data line is sent to a set of sense outputs SOi
, cursed by SOi. On the other hand, in a large number of unselected subarrays in which word lines are not selected, no operating current flows to the readout circuits connected to the subarrays.
The power consumption of the entire chip during reading can be reduced.

For writing, the write circuit of one selected subarray is
Selected by S and WCi, write data is written from the common data line.

Figure 7 shows the memory cell array divided into four sub-arrays as in Figure 6, but the main amplifier is divided into fourteen sub-arrays.
It is a collection of individual items. Similar to FIG. 6, the read operation of this embodiment is RCi, WCi (i=o~3, or
Since one subarray is selected from among the four subarrays by the subarray selection signal (subarray selection signal), it is possible to reduce the power consumption of the readout circuit. Since the current output is obtained only from the readout circuit of the selected subarray, it is possible to combine them into a common so and so in this way. Furthermore, since there is only one main amplifier compared to FIG. 6, the area occupied by this circuit on the chip can be reduced. Furthermore, Figure 6,
Regarding the main amplifier 4 and output circuit 18 in FIG.
BiCMO8, a high-speed, high-sensitivity bipolar disclosed in
By using the circuit, the memory access time can be further speeded up due to the synergistic effect with the effects of the present invention.

8, 9, and 10 show a fifth embodiment of the present invention,
Yes, precharge circuit, rewrite circuit, and read circuit for two columns of memory cell pitches.

One row of control circuits including a write circuit, a read circuit, and a write circuit are provided.

FIG. 8 is its circuit diagram, and FIGS. 9 and 10 are operation timing diagrams of the read cycle and write cycle, respectively.1 In this embodiment, the selection of the read circuit in FIGS. 1, 2 to 7 Signal RCI is shared by precharge circuit drive signal PC1. Here, A1 is a sub-array consisting only of memory cells, 1 is a memory cell, 3 is a precharge circuit, and 4 is a rewrite circuit.

5 is a read circuit, 6 is a write circuit, 7 is a control signal YSR generation circuit for the read circuit, and 8 is a control signal YS for the write circuit.
This is a W generation circuit. Reference numerals 19 and 20 indicate a sense amplification section that puts these together. Mllll.

M112, M2O1, M2O2 are data lines Di, Di, D2 . D2 and the data lines Di', Di' or D2' in the upper and lower sense amplifier sections 9.20
, D2'. Similar switch MO8Mlol.

M1O2 also exists above the sense amplification section 19.

Controls connection to the upper memory subarray (not shown).

In this embodiment, sense amplifying sections of 19.degree. and 20.degree. are alternately arranged on both sides of the upper and lower sides of the subarray.

This alternating arrangement has a small data line pitch of memory cells,
This is because the sense amplifier section does not fit within the pitch of one data line pair. Therefore, word line WL of sub-array A1
In order to read and write to the memory cells on 12, both sense amplifiers 19 and 20 must be operated. For this purpose, Mlll, M112 and M2O1,
Turn on M2O2 and turn off MIOI and M1O2.

The read operation will be explained using FIG. 9.

For simplicity, the operation of the memory cell 1 on the data line D1 will be described below, but the same applies to the memory cells connected to the data line D2.D2. First, when subarray Al is selected, MOS switches Mill, M
112. M2O1, M2O2 on, MIOI, M1O
2 must be turned off, the MOS switch selection signals 5HII and 5H20 are kept at a high potential, and 5HIO is kept at a low potential.0Next, the precharge circuit drive signal P
By changing CI from a high potential to a low potential, the data line is precharged to the HVC voltage and becomes high impedance. Then, the word line WL12 is changed from a low potential to a high potential (a voltage high enough to turn on the transfer MOS transistor of the memory cell) and the charge in the memory cell is read out to the data line. After that, the drive signal 5API of the rewrite circuit 4
, 5ANI are driven to amplify the potential difference signal on the data line]2 to an amplitude equal to or close to the power supply voltage. Note that the figure shows a case where information of high potential "1" is read from the memory cell.

The control signal YSR of the readout circuit is the column selection signal YSi(i
= O-n) and the logical operation of PCI. In the case of this embodiment, when PCl is at a low potential, YSR rises (falls) almost simultaneously with the rise (fall) of YSi.
, YSR timing can be considered in two ways. One is as shown by the broken line in FIG. 9, after amplifying the potential of the data line, the YSR is changed from a low potential to a high potential to change the sense output line 5o.
-1, This is a method to obtain a current difference signal in SQL. The other is, as shown by the solid line of YSR, by raising the word line WL12 at almost the same timing as the word line WL12, the read information from the memory cell is detected without waiting for amplification by the rewrite circuit, and the read common data line SQL is read.

This is a method of obtaining differential signals on SOI. The latter is more suitable for high-speed operation, but since the signal amount in the subsequent stage circuit of SOI and SQL is small, it must be a highly sensitive main amplifier.In addition, in the above read operation, the selection signal WCI of the write circuit is P
It is not shared with CI and has a high potential, and YSW is kept at a low potential.

Next, the write operation will be explained using the timing chart shown in FIG. Precharge circuit, word line WL12.
Sense amplifier drive signal 5API.

5ANI is the same as the read operation.

The YSW signal that controls the write circuit is generated in the circuit 7 by the logical operation of the write circuit selection signals WCI and YSi. The column decoder can be simplified if the switching timing of YSi remains the same during reading and writing. As in the case of this embodiment, the rising (falling) of YSW is
It is determined from the falling (rising) of I. Note that in this case as well, there are two methods for the timing of YSW.

First, as shown by the broken line in the figure, after the rewrite circuit operates and the potentials of the data lines Di and Di are amplified, the YS
The other case is to select common data lines C: D1 . This is the case when writing CDI data. The timing of this YSW is YSi
This can be done with WCl, but it can also be done with WCl. In the latter case, YSi does not need to change the timing between reading and writing, and the speed of YSi, that is, the speed of reading can be increased. At this time, even if the word line is selected, the data line D2. At D2, the write circuit (Save Ift in FIG. 8) does not operate, and only rewriting is performed.

As described above, by substituting PCI for the selection signal RCI of the readout circuit, there is an advantage that the number of wiring lines and circuits can be reduced because an RCI line and an RCI generation circuit are not particularly required.

FIG. 11 shows the entire memory array constructed by combining the memory cell sub-array of FIG. 8 and the sense amplifier section.

FIGS. 12 and 13 are operation timing diagrams of the above circuit in read and write cycles, respectively. In this embodiment, the present invention is applied to a multi-division data line system in which a memory cell array is divided into four parts, and the precharge circuit drive signal PCi is used instead of the readout circuit selection signal RCi as in FIG. This is an example using

In FIG. 11, numeral 4 indicates a rewrite circuit, 3 a precharge circuit, 5 and 7 a read circuit and a control signal YSR generation circuit, and 6 and 8 a write circuit and a control signal YSW generation circuit, respectively. and.

Reference numerals 19 to 22 designate sense amplification sections each comprising the circuit groups 3 to 8 above and MOS switches.

13 is a column decoder, 14, 15, 16, 17° 171 is the main amplifier section that amplifies and selects the sense output SOi, SOi (i = o ~ 4), 18 is ECL or TTL
This is an output circuit for connecting external interfaces such as Furthermore, AO to A3 are subarrays containing only memory cells.

As shown in FIG. 11, the data lines of the subarray and the sense amplifier section are connected via MOS switches.

The sense amplification sections are arranged above and below the subarrays, alternating with the subarrays. This is because, as explained in FIG. 8, the wiring pitch of the data lines becomes smaller, making it difficult to arrange the circuit of the sense amplifier section within the pitch of the two data lines.

The operation of the embodiment shown in FIG. 11 will be explained below.

First, the read operation will be explained using FIG. 12.

Now, among the four subarrays AO-A3 in FIG.
Select, other AO, A2. A3 is in a non-selected state.

At this time, memory cells 100, 101 of subarray AI
In order to read the information of
i, D2. In order to connect D2 and data lines D1'Di' and 02' and D2' in the sense amplifier section 20.21,
MOS switch drive signals 5HII, 5H20 are left at high potential, while unselected subarrays AO.

In order to separate A2 from the activated sense amplification section 20.21, 5HIO and 5H21 are brought to a low potential and the MOS switch is turned off. , 5HC) 1,5H40 may be at either a high potential or a low potential, but charging and discharging current can be saved by leaving it at a high potential.

Next, sense amplification section 20 .related to selected subarray A1.
The precharge signals Pct and PC2 of 21 are changed from high potential to low potential to disconnect the data line and precharge voltage AIAHVC. At this time, the subarray Al and the sense amplifier 2
The data line within 0.21 is in a high impedance state while being precharged to the HVC voltage. After this, the word line WL12 is raised from a low potential to a high potential (this potential is high enough to turn on the transfer MOS transistor of the memory cell), and the charge in the memory cell is transferred to the data line D.
l, Di, D2. Note that the figure shows a case where information of high potential 1 (I11) is read out from memory cells 100.101.After this, drive signal 5AP1.D2 is read out.
5AN1.5AP2.5AN2 drives the rewrite circuit 4.0 circuit 4 connects data lines Di, Di, D2. The potential difference of D2 is detected and these data lines are amplified to a logic amplitude of high potential and low potential.

The column selection signal YSO (i=one of o to n) rises from a low potential to a high potential almost simultaneously with the word line WL12. Since the read circuit control signal YSR is the result of a logical operation between YSO and PCi (functioning as the read circuit selection signal RCi) in the YSR generation circuit, the YSR signal rises in accordance with YSO. When YSR becomes a high potential, the readout circuit 5 in the sense amplifier section 20.21 connects the data line D.
1°Di, D2. The potential difference of D2 is detected and a current difference signal is output to the sense output lines SQL, SQL, SO2, and SO2. SQL, SQL, SO2, SO2 are amplified by the high-speed, high-sensitivity main amplifier 15.16 in the subsequent stage, and at the same time
One of two pairs of signals: QL, SQL, and SO2゜SO2
The pair is selected and the output signal D ou
get t. 14.degree.15.16, 17.171 are main amplifiers corresponding to five sense amplifier sections. If this circuit is configured with a bipolar current switch and its current source is controlled by a subarray selection signal, current will flow through only one of the five switches, making it possible to achieve the desired selection function and low power consumption at the same time.

Next, the write operation will be explained using FIG. 13. The same subarray A1 as in the read operation is selected.

AO1A2. It is assumed that A3 is in a non-selected state.

Switch MO8 control signals 5HIO, 5H21.

5HIN and 5H20 are the same as in the reading operation.

Also, precharge circuit drive signal PCI, PC2° word line WL12, and rewrite circuit drive signal 5API.

5ANI, 5AP2, and 5AN2 are also the same as the read operation.

Now consider the case where data is written to memory cells 100° and 101 in two consecutive cycles. In this case, the write circuit selection signals WCI and WC2 are used as the precharge circuit drive signal Pct in the same way as in the read operation.

It cannot be shared with PO2, because the sense amplifiers located above and below the memory sub-array are selected and rewritten, but only the top or bottom of the sub-array is desired to be written in one cycle.

If WCI, WO2 and PCI, PO2 are shared, the following inconvenience will occur. At the same time as YSO rises, the write circuits in the sense amplifiers 20 and 21 operate simultaneously and attempt to write to the memory cells 100 and 101 at the same time. However, in the write circuit of the sense amplifying section 20, the desired definite data is present in CDI, CDI, but in the write circuit of the sense amplifying section 21, the desired definite data is on CD2. Since there is only undefined data on CD2, undefined data is written into the memory cell 101.

Therefore, the write circuit selection signal WCi (i=1°2) is P
It cannot be shared with Ci (i = 1.2), however, when writing 2 bits or more (cells 100°101) or more in one cycle simultaneously, write circuit selection signal WCi (i
=1.2) can be shared with PCi (i=l, 2). In this case, CDI, CDI, CD2. CD2
It is necessary to control the peripheral circuits so that both have valid data.

Note that by selectively operating the readout circuits, it is possible to suppress the current flowing to unselected readout circuits, and by connecting the YS line to the sources of the MOS transistors of the control signal YSR generation circuit and YSW generation circuit. By reducing the parasitic capacitance of the YS line, there is an effect of increasing speed and reducing power consumption as in the previous embodiments.

The present invention can be used for both TTL and ECL interfaces. FIG. 14 shows an example in which the present invention is applied to an ECL interface.

High sensitivity main amplifier 14, 15.16°17 in Figure 11
．． 171 and a specific example of the output circuit 18 in JP-A-1-6
This will be explained using an example disclosed in No. 6128. Figure 14 shows
FIG. 15 is a diagram illustrating a configuration example of an ECL interface output circuit and its operation at the time of reading.

As shown by the broken line in FIG. 14, the output circuit system consists of three circuit blocks MAL, MA2 . Divided into OB. It should be noted that MAL is the high sensitivity main amplifier 14, 15 .
16, 17, and 171, MA2. Since a bipolar-based circuit, in which OB indicates the output circuit 18, requires a power supply voltage of 3V or more, a power supply voltage of VEH is applied.

In MAL, output lines so and s from the memory cell readout circuit
o is input, outputs MO and MO are taken out through a current-voltage conversion circuit and a bipolar differential amplifier circuit, and a current signal corresponding to the signal voltage of the data line appears at so and so. Qt
~Q4+ Rim Rz+ DllDa, Is~Ia circuit converts this current signal into voltage* Qz, Qt
A constant voltage Va (for example, -O, 8V) is applied to the base of , and voltage fluctuations of so and so are suppressed by utilizing the fact that the value of VBH does not depend much on the amount of current. This reduces the delay due to the parasitic capacitance of so and so @QIIp QssMl is a differential amplifier circuit, and whether or not to activate it is determined by GE, WE (write activation signal) and address input. The information from which subarray is to be transmitted to the subsequent stage is selected by the φa^j. φMAJ with the word line and column selection signal of the memory cell selected
It is also possible to perform a so-called static operation in which data from multiple memory cells is switched at high speed by switching only one memory cell. A current signal also appears in MO and MO.

In MA2, this is converted into a voltage signal like MAL and Do
, take out Do, Qet surrounded by a dashed line in MAZ
Qxo, M2 is a latch circuit, which holds data read from the memory cell by setting the signal φL to a high potential. Read data can continue to be output to D out even during the rewrite operation or precharge operation of the DRAM cell. This latch circuit is block MA
It may be provided within L. In this case, MO and MO are the base inputs.

SO and SO become collector outputs. Even during the rewrite operation or precharge operation of the DRAM cell, φ
Static operation is also possible by switching only MAJ.

Block OB takes out DouT from the emitter of Q7, φoF! Q during standby or write cycle
II! This is to turn on 1 and fix DOUT to a low potential.

FIG. 15 is an explanatory diagram of the read operation including the above-mentioned static column operation. GE, OE, I”-x
k.

Ayh and A2 are external input signals. GE is a chip enable signal, and OE is an output enable signal, which outputs valid data to D OUT when the potential is low.a A
xh is a word-related address signal group, Ayb is a column selection-related address signal group, and Azm is an address signal group for switching φA^. Azh during the period when GE and OE are at low potential.
In this static column operation, as shown in FIG. 14, by switching the outputs from the readout circuits in the sense amplifiers on both the upper and lower sides of one selected subarray, a 2-bit readout can be achieved. Static column operation. Furthermore, by increasing the number of subarrays selected in one cycle, 4-bit static column operation is also possible. In this case address Azh
Two or more pieces are required. Also, even if GE enters the precharge period with a high potential, if OE is a low potential, DO
Output valid data to UT.

Although omitted in FIG. 14, so, so.

MO, MO, Do, and Do have large parasitic capacitances, so in high-speed continuous cycle operation, the access time may be affected by the H history of the previous cycle. In this case, it is preferable to provide equalizer MOS transistors on these differential signal lines and keep them at the same potential during the standby period.

〔Effect of the invention〕

According to the present invention, it is possible to selectively operate the read and write circuits belonging to a plurality of subarrays, so that current flows only to the selected circuit and does not flow to many circuits in an unselected state, thereby reducing power consumption. It has the effect of electrification.

Furthermore, since the parasitic capacitance of the column selection signal line YS can be reduced, the rise and fall speeds of the column selection signal can be increased. Therefore, this column selection signal has the effect of increasing the speed of the driven circuit.

By raising the column selection signal YSi during writing at the same timing as the word line, writing can be performed at high speed.

The present invention can be used for both TTL and ECL interfaces. In addition, although the present invention is applied only to DRAM in the embodiment, the present invention can also be applied to SRAM to achieve the same effect.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a first embodiment showing the concept of the present invention, FIG. 2 is a diagram showing a conventional example, and FIGS. 3, 4, and 5 are diagrams showing a second embodiment of the present invention. FIG. 6 is a diagram showing the third embodiment of the present invention, FIG. 7 is a diagram showing the fourth embodiment, and FIGS. 8 to 10 are diagrams showing the fifth embodiment. FIGS. 11 to 13 are diagrams showing a sixth embodiment, and FIGS. 14 and 15 are diagrams showing specific examples of the main amplifier and output circuit in FIG. 11. 1.100,101...memory cell, 2...memory cell sub-array, 3...precharge circuit, 4...
Rewriting circuit, 5... Reading circuit, 6... Writing circuit, 7... Control signal generation circuit for reading circuit, 8...
Write circuit control signal generation circuit, 114, 15.16° 17, 171... Main amplifier (main amplifier), 18.
...Output circuit, VE pin...Power supply voltage, WL, WL12
゜PC, PCi...Precharge circuit drive signal line, H
VC...Precharge voltage supply line, SAP, SAN...
・Rewriting circuit drive line, RC, RCi...Reading circuit selection signal line, WC, WCi...Writing circuit selection signal line,
YS... Column selection signal line, YSR, YSRi... Read circuit control signal line, YSW... Write circuit control and common data line, CE... Chip enable signal, OE...
・Output enable signal, Axl... word-related address signal group, A, 1... is column selection-related address signal group,
Azl... address signal group for switching φMAJ, φMAJ... main amplifier activation signal, MO, M
O...Main amplifier output line, φ...Latch circuit drive signal. Dairoman YS Tomimefu 4 Diagram (0-) ShiL master buifful C 75w it (
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Claims (1)

[Claims] 1. A memory cell array is divided into a plurality of subarrays in the data line direction, and each subarray has a data line pair to which a plurality of memory cells are connected, and a readout provided for each of the plurality of data line pairs. a common data line pair for writing and a common data line pair for writing,
a differential read circuit that receives each data line pair as an input and a read common data line pair as an output; a write circuit that transfers write data from the write common data line pair to the data line pair;
In a semiconductor memory device comprising a control signal generation circuit for the read circuit and the write circuit, and further comprising a column selection decoder circuit shared by a plurality of subarrays, the read circuit and the write circuit output a column selection decoder circuit. A semiconductor memory device characterized in that it is controlled by the output of a control signal generation circuit which is part of the input. 2. The control signal generation circuit is provided near the read circuit and the write circuit, performs logic between the signal from the column selection decoder and the subarray selection signal, and controls the read circuit and the write circuit with this output. A semiconductor memory device according to claim 1, characterized in that: