JPH0373493A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain rapid and stably reading by amplifying a reading signal of a comparatively small signal level read out from a memory cell with a single end constitution by a differential sense amplifier based upon a reference voltage formed by a dummy cell. CONSTITUTION:A Y-group decoder DCR decodes a Y-group address signal to form a data line selecting signal and a Y selection circuit YSW connects the data line of a memory array M-ARY consisting of memory cells with single end constitution to a common data line CD. The dummy data line of a dummy array DCA is connected to a common dummy line CDD through a dummy switch circuit DSW and the reading signal of the common data line CD is supplied to the differential sense amplifier SA using the potential of the CDD as a reference voltage and highly stably and rapidly amplified. Consequently, high sensitive and rapid reading can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor memory device, and relates to a static RAM with a single-end configuration coupled to one data line.
It is related to effective technology that can be used for.

(Prior art) A static type RAM that has essentially one data line and performs write and read operations using this data line.
However, the v1 version has been proposed in Japanese Patent Laid-Open No. 56-105387. The memory cell in this RAM consists of a CMOS inverter circuit, a clocked inverter circuit that selectively feeds back its output signal to the input side, a transmission gate MOSFET that transmits a write signal, and a read clock gate that outputs a read signal. This memory cell has an input-only terminal and an output-only terminal, and is connected to pass lines (data lines) for human power and output, respectively.

At this time, the number of pass lines can be halved compared to a RAM using normal complementary data lines by using, for example, the output pass line as an input pass line for adjacent memory cells. It is.

[Problem to be solved by the invention]

The above RAM has the advantage that the number of pass lines (data lines) can be reduced by about half, but on the other hand, the number of elements is reduced because the memory cell uses a locked inverter circuit as described above. For example, if the memory cells listed in "2" are configured with a 0M05 circuit, one clocked inverter circuit will have 4 MOS F E
Since T is required, there are problems such as a total of 12 MOSFETs are required. By the way, in a fully static memory cell, there are a total of 6 MOSFEs.
It is composed of T.

An object of the present invention is to provide a new static RAM with a single-end configuration that achieves high integration and low power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[! Means for Solving a Problem] A brief overview of typical inventions disclosed in this application is as follows.

In other words, a read signal from a static memory cell with a single-end configuration is processed by a differential sense amplifier that receives a reference voltage and voltage formed by a dummy cell provided at the intersection of a word line and a dummy data line. Amplify.

[For production]

According to the above-mentioned means, a read signal with a relatively small signal level from a memory cell with a single-end configuration is amplified using a differential sense amplifier using a reference voltage formed by a dummy cell. Reading becomes possible.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a static RAM according to the present invention. Each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon using a known semiconductor integrated circuit manufacturing technique.

Address terminal A1 consisting of multiple bits is transmitted to address buffer ADH. This address buffer ADB
The address signal taken in is decoded by the decoder DCH. The X-system decoder DCR decodes the X-system address message to form a word line selection signal. The word line selection signal is not particularly limited, but word driver D
This will be communicated to the RV. By providing such a word driver DRV, a word line having a relatively large load capacitance due to the coupling of a large number of memory cells can be switched between selection and non-selection at high speed. Note that when a memory cell is coupled to a pair of word lines for reading and writing as described later, the word driver DRV performs a word line selection operation according to each operation mode.

The memory array M-ARY is configured by arranging memory cells in a single-end configuration as described later in a matrix. That is, each memory cell is arranged at the intersection of a data line and a word line.

A dummy cell array OCA consisting of dummy cells forming a read reference voltage is provided for such a memory array M-ARY. A dummy cell array is provided at each intersection of each word line and dummy data line. That is, the dummy cell OCA is composed of one column of dummy cells.

The Y-system decoder DCR decodes the Y-system address No. 48 to form a data line selection signal. The data line selection signal is transmitted to the Y selection circuit (column switch) YSW. The Y selection circuit YSW selects the data and evening lines of the memory array M-ARY from the common data &I in accordance with the selection signal of the data line.
Connect to CD.

In this embodiment, the dummy data line of the dummy seray DCA is connected to the common dummy data line CDD via a dummy switch circuit DSW. The read signal from the common data line CD is supplied to a differential sense amplifier SA that uses the potential of the common dummy data line CDD as a reference voltage, and is amplified there with high stability and high speed. The amplified output No. 8 of the sense amplifier SA is sent out from the output terminal Dout through the data output circuit DOB.

The timing control circuit TG receives the clock signal CLK and the control signal R/W and forms a precharge signal PC, a sense amplifier operation timing signal 3C, etc. necessary for internal operation.

The data input circuit DIB receives write data supplied from the input terminal Din and transmits it to the common data line CD.

FIG. 2 shows a circuit diagram of an embodiment of a main part of a static type RAM according to the present invention. The circuit in the same figure is 0M
It is composed of an O3 (complementary type MO3) circuit, and the P-channel MO3FET becomes an N-channel MO3FET by adding an arrow to its channel (bank gate) section.
Distinguished from SFET.

Memory cell MC in this embodiment has a single-ended configuration for high integration. That is, the memory cell MC is connected to a pair of CMOS inverter circuits Nl, as one memory cell MC is exemplarily shown.
The inputs and outputs of and N2 are cross-connected into a latch configuration. In this case, in order to make it possible to rewrite the held information only from the input terminal of the inverter circuit N1, in other words, in order to have a single-ended configuration, the size (conductance) of the MOSFET that constitutes the inverter circuit N1 is increased, M constituting inverter circuit N2
The size (conductance) of the OSFET is reduced. Thereby, the connection point between the human power of the inverter circuit N1 and the output of the inverter circuit N2 is used as an input/output terminal of the latch circuit, and when this input/output terminal is set to a high level/low level, held information is determined accordingly.

The input/output terminals of the latch circuit are connected to the data line DO through a write address selection switch MO3FETQ3. Address selection switch M for this write
The gate of O5FETQ3 is connected to the corresponding write word line WOW.

The input/output terminal of the latch circuit is an amplification MO for reading.
Connected to the gate of 3FETQI. This amplification MO3F
The source of ETQI is grounded, and an address selection switch MO3FETQ2 for reading is provided between the drain and the corresponding data IDO. The gate of this read address selection switch MO3FETQ2 is connected to the corresponding read word line WOR.

The other memory cells provided in the same row constituting the memory array M-ARY have the same configuration as above, and the gates of the address selection switches MO3FET corresponding to the word lines WOW, VOR and WIW, WIR are respectively connected. . The figure exemplarily shows a specific circuit of two memory cells in the row direction.

Other memory cells provided in the same column constituting memory array M-ARY have the same configuration as described above, and are connected to the data line DO2Di. The figure also exemplarily shows a specific circuit of two memory cells in the vertical direction.

The data lines DO, DI, . . . and the dummy data line DD, which will be described later, are provided with a P-channel type precharge MO3.
FETs Q5, Q6 and Q7 are provided. These M.O.
3FETQ5. A precharge signal PC is commonly supplied to the gates of Q6 and Q7.

In this embodiment, a dummy cell is provided that forms a reference voltage used in a read operation from the memory cell. The dummy cell DC is MO3F arranged in series.
Consists of ETQ3 and Q4. The gate of one MO3FETQ3 constituting the dummy cell DC is connected to the corresponding read word line WOR. the other MO3F
The gate of ETQ4 is not particularly limited, but the precharge signal PC is transmitted thereto. As a result, MO3FETQ4 is turned off during the precharge period, and MOSFETQ4 etc. are turned on during the readout period.2. A dummy cell column is activated.

Each of the above data &lDO, Di, etc. is a CMOS switch circuit Q consisting of a parallel P-channel MO3FET and an N-channel MO3FET that constitute a column selection circuit.
IO, Qll, Ql2. Common data Ic via Ql3
Connected to D. On the other hand, the dummy data DD is a similar CMOS switch circuit Q14. It is coupled to the dummy common data line CDD via Ql5.

The gate of the above N-channel type switch MO3FETQ11 is Yi! The gate of the P-channel type switch MO3FETQIO is connected to the selection b' selection Yo, and the selection of the Y selection MIYO is connected to the inverter circuit NIO. An R signal is transmitted. MO3FETQ1 compatible with data IDI
2. Similarly to the above, the selection signal of the corresponding Y selection line Y1 is also transmitted to Ql3.

In addition, a dummy inch MO3FETQI provided on the dummy data line DD4. The selection signal of the dummy selection lR line DY is similarly supplied to the gate of Ql5.

The dummy selection line DY may be fixed at the selection level constantly, or may be set to the selection level each time in synchronization with memory access.

The signals on the common data line CD and the common data line CDD are amplified by a differential sense amplifier as described below.

The sense amplifier in this embodiment is a zero-power stage circuit in which two amplifier circuits are connected in series, and the zero-power stage circuit is comprised of the following circuits.

The signals of the common data line CD and the dummy common data 1cDD are connected to a source follower type N which performs a level shift operation.
It is transmitted to the gates of channel MOSFETs Q16 and Ql7. On the source side of these MO3FETs Q16 and Ql7, there is an N-channel MO3F in a current mirror configuration.
ETQ18°Ql9 is provided, and these MO3FETs
Q1B.

A switch MO3FET Q20 is provided between the common source of Ql9 and the ground potential point ε of the circuit. This switch M
The OSFET Q20 is supplied with the sense amplifier operation timing signal 3C and turns on when the timing signal sc is set to high level, activating the sense amplifier.

The second stage amplifier circuit is composed of a double differential circuit. In other words, the inputs of two pairs of differential amplifier circuits consisting of a differential MOS FET consisting of an N-channel MO3FET and a P-channel current mirror type load MOS FET provided on the drain side of the differential MOS FET are cross-connected. death,
This is to obtain a double-ended differential output. Between the common source of these two pairs of differential MOSFETs and the ground potential point of the circuit, an N-channel MO3FET Q21 is provided which receives the timing signal SC, and is activated in the same manner as above when the timing signal SC is set to high level. be converted into

The pair of output terminals of the pair of differential circuits and the ta voltage Vee
A P-channel type precharge MOSFET'r that receives the timing signal sc is provided between the two. Then, the output signal of the differential circuit is transferred to the inverter circuit N4.
Complementary output signals A and B formed through N5 and N5 are transmitted to the output circuit.

The output circuit includes a push-pull type N-channel MO3FETQ23. which receives complementary output signals A and B passed through the inverter circuits N4 and N5. Q24 and Q25. Q26, and a pair of inverter circuits connected in a launch configuration, each receiving an output signal from the push-pull circuit. The above Bunschbul circuit Q23. Q24 and Q25.
The above δ numbers A and B are cross-supplied to the gate of Q26. For example, if output signal A is high level, MO3
FETQ23 and Q26 are turned on, their signal level is taken into the launch circuit, and the output terminal Do
A low level signal is output from ut. Output signal B
If is at a high level, MOSFETs Q24 and Q25 are turned on, the signal level is taken into the latch circuit, and a high level signal is output from the output terminal Dout.

Note that the output terminal of the input circuit DIB, which transmits a write signal during a write operation, is also coupled to the common data &iCD.

The word lines WOR, WIR and WOW, WIWe are as follows:
An X address buffer XADB, which is an X-based selection circuit,
Selection is made by a decoder circuit DCH that decodes the address signal taken in by returning the address bus sofa XADB and forms a selection signal for one word line for writing or reading L7 in response to a read/write signal (not shown). be done. In the figure, the address buffer and decoder are collectively represented as XADB and DCH. It should be understood that the output section of the decoder circuit DCH is provided with a word driver as described above, although not shown.

The above Y selection lines YO, Y1, etc. are the Y selection circuits of the Y system.
Address buffer YADB and address buffer YAD
A decoder circuit decodes an address signal taken in through B and forms a selection signal for one data line. In the figure, the address buffer and decoder are collectively represented as YADB and OCR.

FIG. 7 shows a data line and a dummy data line D for explaining an example of the operation of the static RAM of this embodiment.
A waveform diagram D is shown.

During the precharge period, both the data line and the dummy data line DD are precharged to a high level H.

In the read L7 period, the read word line is selected.

Further, due to the end of the precharge period, the dummy cell MO3FETQ4 and the like are turned on. If,
If the input/output terminal of the launch circuit in the selected memory cell is at a high level, MO5FETQ1 etc. are in an on state. Therefore, the data line is connected to the readout address selection switch MO3FET and the readout MOSFET.
It is discharged to low level L through ET.

At this time, since the conductance of the MO3FET Q4 of the dummy cell is set to about 1/2 of the conductance of the MO3FET Q1 etc. of the memory cell, the reference voltage VR formed by the discharge operation on the dummy data line DD is made half of that of the data line. The differential amplifier SA amplifies this level difference (VR-L) to form an output signal Dout corresponding to the low level L read signal.

On the other hand, if the input/output terminal of the latch circuit in the selected memory cell is at a low level, MO5FETQ1 etc. are in an off state. Therefore, the read word line VO
R is selected to high level and address selection switch MO
Even when the 3FET Q2 etc. are turned on, the data line DO etc. are kept at the high level I (precharge level).At this time, the dummy cell performs the above-described discharge operation to form the reference voltage VR. A differential sense amplifier SA amplifies this level difference (H-VR) and outputs an output signal D corresponding to the high level H read signal.
Form oat.

Further, during a write operation, write data supplied from the input terminal Dln is transmitted to the common data line CD through the input buffer circuit DIB.

High level/low level writing transmitted to this common data kICD (No. 8 is column switch circuit ysw
, to one memory cell corresponding to the selected write word line through the data line. That is, the memory cell of this example is
MOS FET that makes inverter circuit N2 1Iti
Since the conductance of MO3FETQ3 is set to be small, its holding level is determined according to the signal level transmitted through the selection path and switch MO3FETQ3.

Since the static type RAM of this embodiment uses single-ended type memory cells as described above,
The cell area can be reduced and high integration becomes possible. Since this read signal is amplified by a differential sense amplifier with reference to a reference voltage formed by a dummy cell, it is read out at high speed and with high stability.

FIG. 3 shows a circuit diagram of another embodiment of the static RAM according to the present invention.

In the memory cell in this embodiment, the input/output terminals of a latch circuit made up of inverter circuits Nl and N2 as described above are connected to a data line DO through address selection switches MO3FETQl and Q2. Above switch MO3FE
The gate of the TQI is connected to the word line WO extending in the horizontal direction in the figure, and in this embodiment, the gate of the above-mentioned switch M
The gate of O3FETQ2 is connected to Y selection 'ayo, which extends vertically in the figure.

The other memory cells provided in the same row of the memory array M-ARY have the same configuration as described above, and the gate of the address selector switch MO5FET corresponding to the word line WO is connected. The figure exemplarily shows a specific circuit of two memory cells in the row direction.

Other memory cells provided in the same column constituting the memory array M-ARY have the same configuration as described above, and are connected to the data line L)0. The gates of the address selection switches MO3FET corresponding to the Y selection line are connected in common. The figure also exemplarily shows a specific circuit of two memory cells in the vertical direction.

The data lines D1, Dl... and dummy data 100D, which will be described later, are provided with P-channel precharge MO
Three FETs Q5, Q6 and Q7 are provided. These M.O.
SFETQ5. A precharge signal PC is commonly supplied to the gates of Q6 and Q7.

In this embodiment, a dark cell is provided which forms a reference voltage used in a read operation from the memory cell. The dummy cell DC is MO3F arranged in series.
tl is removed from ETQ3 and Q4. The above dummy cell DC
The gate of one MOSFET Q3 constituting the transistor is connected to the corresponding word line. The gate of the other MO3FET Q4 is connected to a dummy selection line DY'. The -E precharge signal PC is transmitted to the dummy selection line DY'. As a result, MO during the precharge period
When 3FETQ4 is turned on, the information held in the dummy cell is reset to low level, and when memory access is performed, MO3FETQ3 corresponding to the selected word line is
is turned on, the above-mentioned low-level held information and dummy data, %iDD are combined, and -C and dummy data line DD are connected.
The potential of this dummy data line, from which the precharge potential is extracted, is set to half the potential drop of the data line in the low-level read operation from the memory cell. Therefore, the dummy cell DC is a MOSFE
If the parasitic capacitance at the connection point between TQ3 and Q4 is insufficient, a capacitive element is added.

The data lines DO, DI, etc. are connected to the common data line CD via column switch circuits similar to those described above.

Similarly, the dummy data 100 is also connected to the dummy common data line C.
Coupled to OD.

The above common data line CD and dummy common data A11CDD
signal is amplified by a sense amplifier similar to that described above. The output signal A of the inverter circuit N5 in the sense amplifier is transmitted to the next rewriting circuit. The rewrite circuit includes an inverter circuit *N8 for forming rewrite data RWD, a cascade type inverter circuit N6. N7 and a MOS that receives the output control signal output from the inverter circuit N7 and transmits the rewrite data RWD to the common data line CD.
It is composed of FETQ22.

The outline of the read operation of the static RAM of this embodiment is as follows.

When the precharge signal PC (clock pulse CLK) is at a low level, the RAM becomes inactive, and the precharge MO3FETs Q5 to Q7 are turned on, causing the data lines DO, DI, . . . , dummy data 1iDD, etc., to go to a high level. It is pre-charged. At this time, the output signal AεB from the sense amplifier is also applied to the precharge MO3FE provided at the input of the corresponding inverter circuits N4 and N5.
It is set to low level by the on state of T.

As a result, the outputs of the pair of push-pull circuits enter a high impedance state, and the output signal held by the launch circuit is transmitted to the output terminal Dout.

When the precharge signal PC (cross clock pulse CLK) changes from a low level to a high level, an address signal is taken in accordingly, a decoder decodes it, and, for example, the word line WO and Y selection line YO are set to a selected state. Ru.

As a result, only one memory cell provided at the intersection of the word vAwo and the Y selection line YO is selected, and the input/output terminal of the latch circuit is coupled to the data line DO.

When the holding level of this memory cell MC is low level,
The precharge level of data IDO is
It is lowered to the wah level side by the low level. That is, a charge share occurs that corresponds to the capacitance ratio between the parasitic capacitance of the data line DO and the parasitic capacitance of the input/output terminal of the circuit in the memory cell MC. At this time, since the capacitance value of the memory cell is smaller than the capacitance value of data line 00, the potential of data 1DO drops slightly, while the holding potential of memory cell MC rises rapidly and latches. The logic threshold voltage of the inverter circuit INI constituting the circuit is exceeded, so the retention level of the memory cell MC is inverted from low level to high level.In other words, the memory cell in this embodiment The read operation is performed by destroying the holding level to the high level as a reaction to pulling the precharge level to the low level when the holding level is low as described above.

The main cell DC is used to detect a slight drop in the precharge potential of the data IDO as described above. That is, MO corresponds to the Ai level of word 1wo.
The 3FET Q3 is turned on, and the dummy data 11iDD is connected to the node at the connection point between the MO3FETs Q3 and Q4, which was kept at a low level by the MO3FET Q4, which was turned on during the precharge period. As a result, the potential of the dummy data line DD becomes equal to the potential of the data IDO.
The parasitic space ratio between the dummy data line and the dummy cell is set so that the dummy data line and the dummy cell are reduced by about half of the reduction in low level reading.

The potential change between the data IDO and the dummy data 11DD is transmitted to the sense amplifier SA through the column switch circuit and the common data line CD and the common data line vCDD'4c, where it is amplified. As mentioned above, when the read signal from the memory cell is low level,
The output of the sense amplifier (A) becomes high level, and the potential of the common data IcD becomes low level through the inverter circuit N8.

Therefore, the potential of data 1DO changes to low level, and the selected memory cell is rewritten to low level, and the retained information once destroyed by the read 5 operation described above is restored to low level. . Further, due to the high level of the signal A and the low level of the signal B, the output circuit sends out a low level output signal from the output terminal Dout, and holds the output signal in the launch circuit.

Note that the other memory cells coupled to the selected word line WO are in a non-selected state with the Y selection line Y1 and the like being at a low level. Therefore, the other memory cells corresponding to the word line WO are held by the latch circuit, and the other data lines D1 and the like correspondingly maintain the precharge potential.

For example, in the next operation cycle, if Yl is selected instead of word line YO and the memory cell corresponding to word line Yl holds a high level, data line D
The potential of i is left at the precharge potential. At this time, the output signal A of the sense amplifier SA becomes low level, and the switch MO3FETQ22 of the rewrite circuit remains in the off state. That is, during the high-level read operation as described above, the information held in the memory cell is not destroyed, so the rewrite operation is omitted.

In the RAM of this embodiment, a Y selection line is added in place of one word line, but in reality one
Since only one memory cell is selected, power consumption can be reduced.

FIG. 4 shows a circuit diagram of still another embodiment of the static RAM according to the present invention. That is, in this embodiment, which is an embodiment of a 2-baud 1-RAM, the data lines are divided into read and write data lines, and adjacent data lines for write use are shared. That is, the memory array M-ARY is provided with Y selection &IYO3Y1, etc. as in the embodiment shown in FIG. 3, and is supplied to the gate of the address selection switch MO3FETQ3' of the write A of the memory cell MC. Switch M
OSFETQ3° is connected to the switch MO3F of the adjacent memory cell. Common connection point of these adjacent switches MO3FET and write data IWDO
The switch MO5FETQ3 to which the write word lines WOW+ and WOW+ are connected is provided between the write word lines WOW+ and WOW+. This sinch MO3FET Q3 is commonly used for memory cells in two adjacent columns.

Although not particularly limited, in this embodiment, the read signal from the memory cell has the same polarity as the write signal. Invert circuit N for writing
MO5FETQI for reading and a switch MO5FETQ2 are provided on the output terminal side of 1. Instead of this configuration, the reading and writing may be performed from the same input/output terminal side of the launch circuit.

With this configuration, since data lines for writing and reading are provided, the write signal can be read in the same cycle. That is, the write operation can be confirmed during the same memory cycle. When executing such an operation mode, both write and read word lines are selected.

FIG. 5 shows a block diagram of an embodiment of a 2-baud RAM to which the present invention is applied.

The memory array is ms from M-ARYI and M-ARY2.
be done. These memory arrays M-ARY1 and M-AR
Y2 is constructed using a single-ended memory cell as in the previous embodiment.

Therefore, the dummy array DC1,D for its readout
C2 is the respective memory array M-ARY1, M-AR
It is provided corresponding to Y2.

The address buffer is composed of a read-related address buffer RAB that reduces the read-out address signal AR4, and a write-related address buffer WAB that receives the read-in address signal AWi.

The output signals of the address buffers RAB and WAB are sent to the respective pair of read-related address decoders RDCR1.
It is supplied to the write system address decoder circuit WDCR.

The X-system selection signal formed by the address decoder RDCRεWDCH is the read-system word driver R.
It is transmitted to the read word line and write word line of RY 2 to the memory arrays M-ARY 1 and M through DV and the write system word driver WDV.

The Y-system selection signals formed by the address decoders RDCR and WDCR are supplied to the Y selection circuits YSW1. Y.S.
W2 is transmitted to the write-type Y word driver.

A memory array M-ARYI consisting of the above pair.

The read signals and reference voltages from M-ARY2 and dummy cells DCI and DC2 are input to the sense amplifier SA, where they are amplified and output through the data output circuit T)OB.

The output signal of the write circuit (data input cover sofa) DIB that receives the write signal Din is output from the Y selection circuit YSW.
I, conveyed to YSW2.

The read clock signal RC is input to a read system timing generation circuit RTG, where an internal timing signal necessary for the read operation is formed. ! The writing clock signal WC is a writing system tie generation circuit W.
The internal timing signals necessary for the write operation are generated by the TG.

The address comparison circuit ACOMP has a read-related internal address signal ari and a write-related internal address signal avy.
1, it detects that there is a conflict between the write address and the read address 2, and sends the detection output to the Y selection circuit Y.
SW1. Tell YSW2.

When the actual address signals ari and avi match, the address comparator circuit A COMP gives priority to the bypass data and causes the selected memory cell to perform a write operation. Then, without performing reading from the memory cell, the writing system common data line and the reading system common data line are short-circuited to output the write data as is as read data. By adopting this configuration, writing and reading to the same memory cell can be performed substantially simultaneously.

In this embodiment, the memory array M-ARY is divided into two, and correspondingly, dummy cell columns DCI and DC are divided into two.
2 will be provided. The reason for this is, for example, the memory array M-AR
When data line Y1 is selected, memory array M
- Select the cell column DC2 on the ARY2 side to form a reference voltage. Conversely, when the data line of memory array M-ARY2 is selected, the dummy cell column DCI on the memory array M-ARY l side is selected to form a reference voltage. In this precept, No. 8 read from the data line of memory array M-ARY 1 is output from the common data line of memory array M-ARYl (or M-ARY2), and read from the dummy cell column DC2 (or DCI). The reference voltage is memory array M-ARY2 (or memory array M-ARYI
) I is output through the common data line. This results in
The vf4 signal is transmitted to the sense amplifier SA through a common data line that both have the same parasitic capacitance. As a result, the parasitic capacitance of the signal transmission path is balanced, and it is possible to obtain a read signal and a reference voltage having a level difference according to the conductance ratio of the MOS FET that controls the memory cell and the dummy cell.

FIG. 6 shows a circuit diagram of an embodiment of a write-related common data line and a read-related common data line in the two-bottom RAM.

If the write address and read address match,
Swissochi MO3FETQ3 that short-circuits the write system common data bIDi and the read system common data IRcDI
0. Q31 and Q32. Q33 will be established. That is, when the address comparison circuit ACOMP forms a high-level comparison match output, the NISOCH MO3FETs Q31 and Q3
3 on state 1? At this time, if the inverted address signal AR9 that selects the memory array M-ARYi is at a high level, the switch MO3FETQ32 is turned on and connected to the write system common data line Di and the read system common data line RDC1. The write signal is transmitted as is. At this time,
On the memory array M-ARY2 side, the signal on the write system common data line D1 is inverted via an inverter circuit and transmitted to the read system common data line RDC2.

As a result, the differential signal No. 13 is input to the sense amplifier SA, and its amplified output signal is output as a read signal. Note that when the memory array M-ARY 2 side is selected, the signal of the writing system common data line D1 is inverted by the inverter circuit N30 and the switch MO3F
Read common data line Rc through ETQ31 and Q32
The voltage is transmitted to D1, and is transmitted to the sense amplifier SA as a pseudo reference voltage as described above.

Although not shown, the sense amplifier SA is 6. A single-ended differential amplifier circuit is installed on two sides, and its input is differentially connected to the common data lines RCDI and R of the readout system.
CD2 may be connected and one sense amplifier may be activated by the address signals AR9 and AR9. In other words, in a single-ended differential amplifier circuit using a current ξ error circuit as a load, the output extraction side has high sensitivity, so the sense amplifier with high sensitivity is selected by the address signals AR9 and AR9. be.

FIG. 8 shows a circuit diagram of an embodiment of the dummy cell array in the two-bottom RAM shown in FIG. 5 above.

In this embodiment, the dummy cell corresponding to the memory array M-ARY1 is composed of one MOS FET, and is connected in series with a similar MOS FET constituting the dummy cell corresponding to the other memory array M-ARY2. . That is, memory arrays M-ARY1 and M-ARY
The data lines consisting of the two pairs of data lines are connected by two single 5FETs constituting the dummy cells.

In this embodiment, the data lines and dummy data lines of the memory array are P-channel MO3FETs Q32 and Q3.
It is precharged to a low level, such as the ground potential of the circuit, by MOSFET 7. On the other hand, the common data ICDI and CD2 are N-channel MO8FETs.
It is precharged to a high level such as power supply voltage Vcc by Q3o and Q31.

Also in this configuration, when the data line of memory array M-ARYl is selected, the dummy data line DD2 on the memory array M-ARYI side is selected, and the dummy data line DD2 of memory array M-ARYI is selected.
When the data line of RY2 is selected, the memory array M-
Dummy data line DDI on the AR\1 side is selected. As a result, the data line and dummy data line are transmitted to the sense amplifier via the common data lines CDI and CD2, respectively.
The parasitic capacitance of the common data line can be made equal.

In addition, when the precharge level is set as described above, when the data line and dummy data line are selected, the readout No. 16 level becomes a half precharge potential due to charge coupling between the two, and the half precharge potential is used as the reference. Then, as shown in FIG. 7, the low level L and the reference voltage VR change. Thereby, it is possible to form a difference signal for each intermediate potential, which has the highest sensitivity of the differential sense amplifier.

At this time, since the parasitic capacitance of the common data line is smaller than the parasitic capacitance of the data line and the dummy data line, if the half precharge potential drops too much, the sensitivity of the sense amplifier becomes worse. At this time, after the column selection operation is performed, the switch MO3F
ET'Q30 and Q31 may be turned on again to raise the DC level of the read signal.

The effects obtained from the above examples are as follows. In other words, (1) If high integration is achieved by using a memory cell with a single-ended configuration using a latch circuit that allows writing from one input/output terminal, both L and L By amplifying the formed reference voltage using a differential sense amplifier, high-sensitivity and high-speed readout is possible.

(2) The read signal path is balanced by dividing the memory array into two, providing a dummy cell column in each, and outputting read signals from the memory cells and dummy cells through common data lines corresponding to the divided memory arrays. Therefore, the effect of further stabilizing the read operation can be obtained.

(3) By precharging the data line, dummy data line, and common data line to the opposite I novel, and setting it to half potential by column selection operation, the differential sense amplifier has the highest sensitivity. The effect is that it can be operated in a specific area.

(4) In (3) above, when the half potential drops too much, the sense amplifier can be set to high sensitivity by putting the precharge MO3FET into operation again. The effect is that it can be operated in the iw range.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. For example, the structure of the data cell can take various embodiments depending on the reading method of the memory cell. In addition to having the latch circuit as described above, the output circuit may be configured to output the output signal of the sense amplifier in accordance with the operation timing signal.

The RAM may be operated by the clock signal CLK, or may be started by a chip enable signal or a chip selection signal. R
The AM may be built in a custom large-scale integrated circuit such as a standard cell system or a gate array. In this case, the address buffer is omitted and the address No. 13 supplied from an internal address bus etc. is used. A configuration may also be adopted in which the signal is directly supplied to the decoder circuit.

The present invention can be widely used as a static RAM using memory cells with a single-end configuration.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, high integration is achieved by using a memory cell with a single-end configuration using a latch circuit that allows writing from one input/output terminal, and a reference voltage formed using a read signal from the memory cell and a dummy cell. By amplifying this with a differential sense amplifier, high-sensitivity and high-speed readout becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a static RAM according to the present invention, FIG. 2 is a circuit diagram of a main part showing an embodiment of a static RAM according to the invention, and FIG. FIG. 4 is a circuit diagram of a main part showing still another embodiment of a static RAM according to the invention. FIG. 5 is a circuit diagram of a main part showing still another embodiment of a static RAM according to the invention. FIG. 6 is a block diagram showing an embodiment of a 2-bot RAM to which the present invention is applied. FIG. FIG. 7 is a waveform diagram for explaining an example of a read operation of a memory cell with a single-end configuration according to the present invention, and FIG. A circuit diagram is shown. XADB, YADB, ADB...address buffer, R
AB: Read system address buffer, WAB: Write system address buffer, DCR: Decoder circuit, R
DCR...Reading address decoder circuit, WDCR
・Write system address decoder circuit, DRV driver, RDV ・Read system word driver, write system word driver, WYDVI, WYDV2 ・-Write system Y word driver, M-ARY, M-ARYl,
M-ARY2...Memory array, DCA...Dummy cell array, DCI, DC2...Dummy cell column, YSW...
Y selection circuit (column switch circuit), SA...Sense amplifier, RWA...Rewrite circuit, DOB...Data output cover sofa, DIB...Data input bumper, TG...
Timing control circuit, RTG: read timing generation circuit, WTG: write timing generation circuit,
ACOMP...Address comparison circuit Fig. 1 Fig. 4 (Support) Fig. Fig. Fig. 6 Fig. Fig. Fig.

Claims (1)

[Claims] 1. A differential sense amplifier that receives a read signal from a static memory cell with a single-end configuration and a reference voltage formed by a dummy cell provided at the intersection of a word line and a dummy data line. A semiconductor memory device characterized by amplification by. 2. A memory array in which the static type memory cells are arranged in a matrix and a corresponding dummy array are provided as a pair, and a common data line is provided, and when a read operation is performed from one memory array, a data line is provided corresponding to the other memory array. 2. The semiconductor memory device according to claim 1, wherein the dummy cells are selected and the signals of the respective common data lines are inputted to a differential sense amplifier. 3. The data line is precharged to one potential, the common data line is precharged to the other potential, and corresponding dummy cells are connected in series. The semiconductor memory device according to scope 2.