JPH03181067A - Waveform shaping circuit - Google Patents

Abstract

PURPOSE:To prevent the variance in duty ratio of the waveform shaped output by controlling a DC bias so that the time of the low level and that of the high level of a square wave outputted from a comparator are equal to each other. CONSTITUTION:The signal sent from an analog signal processing circuit 1 to a digital signal processing circuit 2 through an input terminal 2A is compared with the threshold level by a comparator 4 and has the waveform shaped. The output of the comparator 4 is supplied to the inverted input terminal of an operational amplifier 7, and a reference voltage 1/2VDD is given to the non- inverted input terminal of the operational amplifier 7. When the time of the level higher than the reference voltage 1/2VDD and that of the level lower than the reference voltage 1/2VDD of the output from the comparator 4 are equal to each other, an average value of the output current of the operational amplifier 7 is 0. The DC bias is so controlled that the time when the output from the comparator 4 is in the high level is equal to the time when it is in the low level. Thus, the change of the duty ratio of the waveform shaped output is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a waveform shaping circuit suitable for use in connection between an analog circuit and a digital circuit in, for example, a reproduction system of a digital audio recorder.

[Summary of the invention]

In a waveform shaping circuit suitable for use in connection between an analog circuit and a digital circuit in, for example, a playback system of a digital audio tape recorder, the present invention superimposes a DC bias on a signal from an analog circuit. The output signal is supplied to a comparator, and the comparator outputs a rectangular wave whose waveform has been shaped.
By controlling the DC bias according to the time difference between the low level time and the high level time of the rectangular wave output from the comparator, waveform shaping can be performed without changing the duty ratio.

In a waveform shaping circuit suitable for connection between an analog circuit and a digital circuit in, for example, a playback system of a digital audio recorder, the present invention is similar to an inverter-type comparator that shapes the waveform of an input signal from an analog circuit. An inverter is provided, the input end of this inverter is connected to its output end, and this connection point is connected to the input end of an inverter-type comparator via a resistor, and the input end and its output are connected to the input signal from the analog circuit. By superimposing a DC bias using an inverter connected to the terminal, supplying the input signal with this DC bias superimposed to an inverter-type comparator, and causing the inverter-type comparator to output a waveform-shaped rectangular wave, This allows waveform shaping without changing the duty ratio.

[Conventional technology]

In a digital audio tape recorder, a reproduced signal from a tape is first supplied to an analog signal processing circuit, where processing such as amplification of the reproduced signal and equalization of frequency components lost in the tape head system are performed. The reproduced signal, which has been subjected to necessary processing in this analog signal processing circuit, is shaped into a rectangular wave and supplied to the digital signal processing circuit.

In digital signal processing circuits, for example, TTL level (5
signal processing is performed in (vp-p).

That is, FIG. 4 shows an example of a reproduction system of a digital audio tape recorder. In FIG. 4, 61 is an analog signal processing circuit, and 62 is a digital signal processing circuit. The analog signal processing circuit 61 includes an RF amplifier 52A.
and 52B, an equalizer 54, and a limiter 55 are provided. In the analog signal processing circuit 61, the reproduced signals from the two heads 51A and 51B are transmitted to the RF amplifiers 52A and 5.
2B respectively to the switch circuit 53.

The output of the switch circuit 53 is supplied to an equalizer 54. The equalizer 54 equalizes frequency components lost in the tape head system and the like. The output of equalizer 54 is supplied to limiter 55.

The digital signal processing circuit 62 includes a comparator 56,
Demodulation circuit 57, PLL 58. A signal processing circuit 59 is provided. In the digital signal processing circuit 62, the comparator 56 shapes the output of the limiter 55 into, for example, a TTL level rectangular wave. The output of the comparator 56 is supplied to the demodulation circuit 57 and also to the PLL 5B. A demodulation circuit 57 demodulates the reproduced signal. PLL5
At 8, the pit clock is played. The output of demodulation circuit 57 is supplied to signal processing circuit 59. Also, PLL58
The recovered clock is supplied to the demodulation circuit 57 and also to the signal processing circuit 59. Signal processing circuit 5
In step 9, processing such as error correction is performed.

The output of the signal processing circuit 59 is supplied to a D/A converter 60. A D/A converter 60 converts the signal from the signal processing circuit 59 into an analog signal.

The output of D/A converter 60 is taken out from output terminal 63.

[Problem to be solved by the invention]

In a digital audio tape recorder, when connecting the analog signal processing circuit 61 and the digital signal processing circuit 62, it is easiest to connect the analog signal processing circuit 61 and the digital signal processing circuit 62 directly, as shown in FIG. It is. However, in this case, the output of the analog signal processing circuit 61 needs to be a rectangular wave with large amplitude and sharp rises and falls.

This is because the threshold level of the comparator 56 is constant, so if the output from the analog signal processing circuit 61 has a waveform with slow rises and falls and small amplitude, a slight change in the DC level will cause the comparator and comparator to This is because the duty ratio of the output of 56 will fluctuate. However, if the output of the analog signal processing circuit 61 is made into a rectangular wave with large amplitude and sharp rises and falls, a problem that the influence of unnecessary radiation becomes large tends to occur.

Therefore, as shown in FIG. 6, the analog signal processing circuit 61 and the digital signal processing circuit 6 are connected via a capacitor 64.
2 and the digital signal processing circuit 62.
It is conceivable to provide a DC bias circuit consisting of resistors 65 and 66 on the input side of the circuit. In this way, the DC fluctuation is removed by the capacitor 64, and the resistors 65 and 66
It is possible to provide a stable DC bias with a DC bias circuit consisting of: Therefore, the analog signal processing circuit 6
Even if the output from the comparator 56 is a waveform with slow rise and fall and small amplitude, the duty ratio of the output of the comparator 56 is likely to fluctuate. If the output from the analog signal processing circuit 61 can be made into a waveform with gradual rise and fall and small amplitude, the problem of unnecessary radiation can be improved.

However, in this case, there is a problem in that a capacitor 64 and resistors 65 and 66 need to be externally connected between the analog signal processing circuit 61 and the digital signal processing circuit 62. In addition, it is necessary to accurately match the DC bias set by the resistors 65 and 66 with the threshold level of the comparator 56, and if there are variations in the DC bias set by the resistors 65 and 66, the comparator 56
The duty ratio of the output of No. 6 changes.

Further, as shown in FIG. 7, the analog signal processing circuit 61
A capacitor 64 is connected between the
It has been proposed that an inverter be used as the comparator 56 and that the output end of the comparator 56 and the input end of the comparator 56 are connected via a feedback resistor 67. In this way, the DC bias applied to the human power of the comparator 56 will be at the threshold level, and even if the DC level of the signal from the analog signal processing circuit 61 changes, the duty ratio of the output of the comparator 56 will not change. At the same time, only the capacitor 64 is required as an external component.

However, the feedback resistor 67 actually constructed within the integrated circuit has polarity, as shown in the equivalent circuit of FIG. Therefore, in reality, the DC bias applied to the input of the comparator 56 cannot be brought to the threshold level, and the duty ratio of the output of the comparator 56 fluctuates.

Therefore, an object of the present invention is to provide a waveform shaping circuit in which unnecessary radiation is not generated from a signal sent from an analog signal processing circuit to a digital signal processing circuit, and the duty ratio of the output after waveform shaping does not change.

Another object of the present invention is to provide a waveform shaping circuit that can connect an analog signal processing circuit and a digital signal processing circuit without requiring almost any external components.

[Means to solve the problem]

This invention superimposes a DC bias on an input signal, supplies the input signal on which the DC bias is superimposed to a comparator 4, causes the comparator 4 to output a rectangular wave whose waveform has been shaped, and also generates a rectangular wave output from the comparator 4. This is a waveform shaping circuit that controls the DC bias according to the time difference between the low level time and the high level time.

This invention provides an inverter 15 which is the same as an inverter type comparator 14 that shapes the waveform of an input signal, connects the input end of the inverter 15 to its output end, and connects this connection point to the inverter type comparator 14 through a resistor 16. 140
A DC bias is superimposed on the input signal by an inverter 15 connected to the input end, and the input end and its output end are connected to the input signal,
This is a waveform shaping circuit that supplies an input signal on which a DC bias is superimposed to an inverter type comparator 14, and causes the inverter type comparator 14 to output a waveform-shaped rectangular wave.

[Effect]

so that the time difference between the low level time and the high level time of the rectangular wave output from the comparator 4 is equal.
DC bias is controlled. In the case of a DC-free modulation method, in the long run, the time for high level and the time for low level become equal. Therefore, if the DC bias is controlled so that the time when the output from the comparator 4 is at high level and the time when it is at low level are equal, in the case of a DC-free modulation method, the analog signal processing circuit can Even if the output of comparator 4 is a waveform with slow rise and fall and small amplitude,
The duty ratio of the output does not change.

Further, by setting the DC bias using an inverter whose input terminal and output terminal are connected to the input signal, the threshold level of the comparator and the DC bias can be made to match. Therefore, even if the output from the analog signal processing circuit is a waveform with slow rises and falls and small amplitude, the duty ratio of the output of the comparator 56 does not change.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the invention.

In FIG. 1, 1 is an analog signal processing circuit, and 2 is a digital signal processing circuit. Output terminal 1A of analog signal processing circuit 1 and input terminal 2 of digital signal processing circuit 2
A capacitor 3 is connected between A and A.

A comparator 4 is provided at the input stage of the digital signal processing circuit 2 . A resistor 5 and a capacitor 6 are connected in series between the input end of the comparator 4 and ground.

The output terminal of the waveform shaping signal is derived from the output terminal of the comparator 4, and the output terminal of the comparator 4 is connected to the inverting input terminal of the current output type operational amplifier 7. The non-inverting input terminal of operational amplifier 7 is %V. . is connected to a reference voltage source 8. The output terminal of the operational amplifier 7 is connected to the connection point between the resistor 5 and the capacitor 6.

A signal from the analog signal processing circuit 1 is sent via the input terminal 2A. This signal is compared with its threshold level by a comparator 4 and shaped into a waveform. The output of the comparator 4 is supplied to the inverting input of the operational amplifier 7. The non-inverting input terminal of the operational amplifier 7 has a reference voltage %
v. . is given. The time when the output from comparator 4 is at a higher level than the reference voltage %VI and the reference voltage K V
The average value of the output current of the operational amplifier 7 becomes O when the time for which the level is lower than lll+ is equal.

Charge is stored in the capacitor 6 according to the time difference between the time when the output from the comparator 4 becomes a high level higher than the reference voltage %Vllll and the time when the output becomes a lower level than the reference voltage %VDD. An output corresponding to this time difference is fed back to the input terminal of the comparator 4 via the resistor 5. In other words, the time and reference voltage when the output from the comparator 4 is at a higher level than the reference voltage %VDD! The comparator 4
A DC bias is applied from capacitor 6 to .

In digital audio tape recorders, 8-
A C-free modulation method such as 10 modulation is used. In the case of such a C-free modulation method, in the long run, the time for high level and the time for low level become equal. Therefore, as mentioned above, if a DC bias is applied to the comparator 4 so that the time when the output from the comparator 4 is at high level and the time when it is at low level is equal, the duty ratio of the waveform shaping output can be changed. No change has occurred.

FIG. 2 shows a second embodiment of the invention. In FIG. 2, 11 is an analog signal processing circuit, and 12 is a digital signal processing circuit. Output terminal ILA of analog signal processing circuit 11 and input terminal 1 of digital signal processing circuit 12
A capacitor 13 is connected between the terminal 2A and the terminal 2A.

An inverter 14 is provided at the input stage of the digital signal processing circuit 12 . At the same time, the input end of the inverter 15 and its output end are connected, and the input end and the output end of the inverter 15 are connected to the inverter 14 through a resistor 16.
connected to the input end of the Inverter 14 and inverter 1
5 are the same elements. The input signal is waveform-shaped by the inverter 14, and an output terminal for the waveform-shaped signal is derived from the output terminal of the inverter 14.

Since the output of inverter 15 is fed back to inverter 15, the output of inverter 15 is at its threshold level. The output of the inverter 5 is applied to the input terminal of the inverter 14 via a resistor 16. Inverter 14
Since the inverter 15 and the inverter 15 are the same element, their threshold levels are the same. Therefore, inverter 14
A DC bias equal to the threshold level of the inverter 14 is applied to the input terminal of the inverter 14. Therefore, with such a configuration, there is no change in the duty ratio of the waveform shaping output.

FIG. 3 shows a third embodiment of the invention.

In FIG. 3, 21 is an analog signal processing circuit, and 22 is a digital signal processing circuit.

The output terminal 2LA of the analog signal processing circuit 21 and the input terminal 22A of the digital signal processing circuit 22 are connected, and the terminal 21B of the analog signal processing circuit 21 and the terminal 22B of the digital signal processing circuit 22 are connected. A current output type operational amplifier 27 is included in the analog signal processing circuit 21.
and a capacitor 6 that stores a charge corresponding to the output current of the operational amplifier 27. An output signal from the comparator 24 of the digital signal processing circuit 22 is supplied to an inverting input terminal of the operational amplifier 27. A reference voltage from a reference power supply 28 is applied to a non-inverting input terminal of the operational amplifier 27 . Further, within the analog signal processing circuit 21, an operational amplifier 29 is provided whose output terminal and inverting input terminal are connected via a resistor 30. The output of the connection point between the operational amplifier 27 and the capacitor 26 is supplied to the non-inverting input terminal of the operational amplifier 29. A signal from a signal source 31 is supplied to an inverting input terminal of the operational amplifier 29 . Operational amplifier 29
The output is sent to the digital signal processing circuit 22.

In this way, the output of the operational amplifier 29 becomes a signal based on the level of the connection point between the output terminal of the operational amplifier 27 and the capacitor 26. That is, the DC level of the output of the operational amplifier 29 is set so that the high level period and the low level period of the output level of the comparator 24 are equal.

In this way, a signal is sent from the operational amplifier 29 to the comparator 24 in which the period in which the DC level is high is equal to the period in which the DC level is low. Therefore, if a DC-free modulation system signal is being reproduced,
No fluctuation in duty ratio occurs in the output from the comparator 24. Although the configuration shown in FIG. 3 increases the number of connections between the analog signal processing circuit 21 and the digital signal processing circuit 22, it has the advantage that a coupling capacitor is not required.

〔Effect of the invention〕

According to this invention, the DC bias is controlled so that the time difference between the low level time and the high level time of the rectangular wave output from the comparator becomes equal. In the case of a DC-free modulation method, the time for high level and the time for low level are equal in terms of IJI. Therefore, if the DC bias is controlled so that the time when the output from the comparator is at high level and the time when it is at low level are equal, in the case of a DC-free modulation method, the output from the analog signal processing circuit can be reduced. Even if the output has a waveform with slow rise and fall and small amplitude, the duty ratio of the comparator output does not change.

Further, according to the present invention, the threshold level of the comparator and the DC bias can be matched by setting the DC bias using an inverter whose input terminal and output terminal are connected to the input signal. For this reason,
Even if the output from the analog signal processing circuit is a waveform with slow rise and fall and small amplitude, the duty ratio of the output of the comparator does not change.

[Brief explanation of drawings]

Fig. 1 is a connection diagram of the first embodiment of this invention, Fig. 2 is a connection diagram of the second embodiment of this invention, Fig. 3 is a connection diagram of the third embodiment of this invention, and Fig. 4 is a connection diagram of the third embodiment of this invention. The figure is a block diagram of an example of the configuration of a conventional digital audio tape recorder, FIG. 5 is a connection diagram of an example of a conventional waveform shaping circuit, FIG. 6 is a connection diagram of another example of a conventional waveform shaping circuit, and FIG. FIG. 7 is a connection diagram of still another example of the conventional waveform shaping circuit, and FIG. 8 is a connection diagram used to explain still another example of the conventional waveform shaping circuit. Explanation of main symbols in the drawings 1.11, 21: Analog signal processing circuit. 2.12, 22: Digital signal processing circuit. 4 14.24: Comparator. 7.27, 29: Operational amplifier. 15: Inverter.

Claims (2)

[Claims] (1) Superimpose a DC bias on the input signal, supply the input signal with the DC bias superimposed to a comparator, output a waveform-shaped rectangular wave from the comparator, and A waveform shaping circuit that controls the DC bias according to a time difference between a low level time and a high level time. (2) Provide an inverter that is the same as the inverter-type comparator that shapes the waveform of the input signal, connect the input end of the inverter to its output end, and connect this connection point to the input end of the inverter-type comparator through a resistor. and superimposes a DC bias on the input signal by an inverter having the input terminal and its output terminal connected, and supplies the input signal with the DC bias superimposed to the inverter type comparator. A waveform shaping circuit that outputs a shaped rectangular wave from a comparator.