JPH03180952A - Identification signal generating circuit - Google Patents
Identification signal generating circuitInfo
- Publication number
- JPH03180952A JPH03180952A JP1319916A JP31991689A JPH03180952A JP H03180952 A JPH03180952 A JP H03180952A JP 1319916 A JP1319916 A JP 1319916A JP 31991689 A JP31991689 A JP 31991689A JP H03180952 A JPH03180952 A JP H03180952A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- gates
- identification signal
- exor
- generating circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 12
- 230000010365 information processing Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、情報処理装置に関し、特にその装置番号など
の装置識別信号を発生する識別信号発生回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and more particularly to an identification signal generation circuit that generates a device identification signal such as a device number.
従来、この種の識別信号発生回路は１、装置製造工程に
おいてジャンパ布線工事が必要であった。Conventionally, this type of identification signal generation circuit requires jumper wiring work in the device manufacturing process.
したがって、上述した従来の識別信号発生回路は、製造
原価が高くなるという欠点がある。Therefore, the above-described conventional identification signal generation circuit has the disadvantage of high manufacturing cost.
本発明の識別信号発生回路は、ＯＲゲートＡＮＤゲート
、Ｎ Ａ Ｎ Ｉ）ゲート、またはＥＸＯＲゲートで構
成され、入力に固定値が与えられ、必要とする情報処理
装置の識別信号に応じて前記ＯＲゲート、ＡＮＤゲート
、ＮＡＮＤゲート、またはＥＸＯＲゲートを選択的に用
いて回路を構成するようにしたことを特徴とする。The identification signal generation circuit of the present invention is composed of an OR gate, an AND gate, a NAN I) gate, or an EXOR gate, and a fixed value is given to the input, and the OR The present invention is characterized in that the circuit is configured by selectively using a gate, an AND gate, a NAND gate, or an EXOR gate.
本発明の識別信号発生回路は、ＯＲゲート、ＡＮＤアゲ
ートＮＡＮＤゲート、およびＥＸＯＲゲートで構成され
、入力に固定値が与えられ、必要とする情報処理装置の
識別信号に応じて前記ＯＲゲート、ＡＮＤゲート、ＮＡ
ＮＤゲート、ＥＸＯＲゲートを選択的に用いて回路を構
成するようにしたことを特徴とする。The identification signal generation circuit of the present invention is composed of an OR gate, an AND gate, a NAND gate, and an EXOR gate, and a fixed value is given to the input, and the OR gate, the AND gate is ,NA
The present invention is characterized in that the circuit is constructed by selectively using ND gates and EXOR gates.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。こ
の識別信号発生回路１は、ＯＲゲート１ａ、２ａと、Ａ
ＮＤゲートｌａ、２ｂと、ＮＡＮＤゲートｌｃ、２ｃと
、ＥＸＯＲゲート１ｄ、２ｄとで構成され、４種のゲー
トのうちの１つが使用される。同様に、接続線１０，２
０．３０．４０、または接続線１１，２１，３１，４１
．または接続線１２，２２，３２，４２、または接続線
１３．２３，３３．４３が使用される。接続線１５は接
続線１０．１１，１２，１３のいずれかの接続され、接
続線２５は接続線２０，２１，２２゜２３のいずれかと
接続され、接続線３５は接続線３−
３０．３１，３２．３３のいずれかと接続され、接続線
４５は接続線４０，４１，４２．４３のいずれかと接続
される。これらの接続はいずれもプリン１へパターンに
より行われる。接続線３５は＋５■と接続されて論理値
゛↓′″が与えられ、接続線４５はＧＮＤと接続されて
論理値ＩｔＯ”が与えられる。FIG. 1 is a block diagram showing one embodiment of the present invention. This identification signal generation circuit 1 includes OR gates 1a, 2a, and A
It is composed of ND gates la, 2b, NAND gates lc, 2c, and EXOR gates 1d, 2d, and one of the four types of gates is used. Similarly, connection lines 10, 2
0.30.40, or connection wire 11, 21, 31, 41
．． Alternatively, connection lines 12, 22, 32, 42 or connection lines 13.23, 33.43 are used. The connecting line 15 is connected to any one of the connecting lines 10, 11, 12, 13, the connecting line 25 is connected to any of the connecting lines 20, 21, 22, 23, and the connecting line 35 is connected to the connecting line 3-30, 31. , 32.33, and the connection line 45 is connected to any of the connection lines 40, 41, 42.43. All of these connections are made to printer 1 by pattern. The connection line 35 is connected to +5■ and given a logic value "↓'", and the connection line 45 is connected to GND and given a logic value ItO".
ＯＲアゲートａ、２ａは２人力ＯＲゲートであり、入力
の論理値が“０” ＩＪ Ｏ７１の場合、出力の論理値
は０”であり、入力の論理値がｚｒｏ”（Ｌ Ｏ７＋以
外の場合、出力の論理値はｔｌ １ ｕとなる。OR gates a and 2a are two-man operated OR gates, and when the input logic value is "0" IJ O71, the output logic value is 0", and the input logic value is zro" (other than L O7+, The logical value of the output is tl 1 u.
ＡＮＤゲーｌへｉｂ、２ｂは２人力ＡＮＤゲートであり
、入力の論理値がｌ １ ＋ｊ １１１ ｔＴの場合、
出力の論理値は１１１ ｊｌであり、入力の論理値がｔ
ｌ １ ｔＴＩＩ Ｉ Ｉ＋以外の場合、出力の論理値
は′Ｏ″となる。ib and 2b to AND game l are two-man powered AND gates, and when the logic value of the input is l 1 + j 111 tT,
The logical value of the output is 111 jl, and the logical value of the input is t
l 1 tTII I In cases other than I+, the logical value of the output is 'O'.
ＮＡＮＤゲートｌｃ、２ｃは２人力ＮＡＮＤゲ］・であ
り、入力の論理値がｉｔ １ ｎ ｔｔ １″′の場
合、出力の論理値はＯ′″であり、入力の論理値が′１
′″ （（Ｉ Ｉ＋以外の場合、出力の論理値は′１”
となる。The NAND gates lc and 2c are two-man NAND gates, and when the input logic value is it 1 n tt 1'', the output logic value is O'', and the input logic value is '1'.
’” ((I If other than I+, the logical value of the output is ’1”
becomes.
４−
ＥＸＯＲゲートｌｄ、２ｄは２人力ＥＸＯＲゲートであ
り、入力の論理値が“Ｏ”０”またはパ１′″ １″′
の場合、出力の論理値はＩｔ ＯｊＦであり、入力の論
理値がＩＩ ＯＩＩ Ｅｌ ｉ ＩＩまたは１１１１
７１１ Ｏ＋１の場合、出力の論理値はＩｔ １９１と
なる。4- EXOR gates ld and 2d are two-man powered EXOR gates, and the logic value of the input is “O” 0” or
If the logical value of the output is It OjF and the logical value of the input is II OII El i II or 1111
711 O+1, the logic value of the output will be It 191.
第２図は、第１図の識別信号発生回路においてＯＲアゲ
ートａ、２ａを構成部品として使用したときの識別信号
発生回路を示す。FIG. 2 shows an identification signal generation circuit when the OR agates a and 2a are used as components in the identification signal generation circuit of FIG.
表１は識別信号発生回路を構成する電子部品としてＯＲ
アゲートａ、２ａまたはＡＮＤゲート１ｂ、２ｂまたは
ＮＡＮＤゲートｌｃ、２ｅまたはＥＸＯＲゲートｌｄ、
２ｄを各々を使用した場合の接続線１５．１６に表われ
る論理値を示す。Table 1 shows OR as the electronic components that make up the identification signal generation circuit.
Agate a, 2a or AND gate 1b, 2b or NAND gate lc, 2e or EXOR gate ld,
The logical values appearing on the connection lines 15 and 16 when using each of 2d and 2d are shown.
以上の説明において分かるように、２つの出力信号が表
わすことのできる論理値は、表１に示すように２つの出
力信号ね表わされる４種の論理値が使用するゲートを種
別により各々得られる。また、以上の説明においては、
２つの出力についてのみ説明したが、２つ以上の出力に
ついても同様な回路構成で得られることは明白である。As can be seen from the above description, the logical values that can be expressed by the two output signals are obtained depending on the type of gate used by the four types of logical values that are expressed by the two output signals, as shown in Table 1. Also, in the above explanation,
Although only two outputs have been described, it is clear that two or more outputs can be obtained with a similar circuit configuration.
５−
６−
〔発明の効果〕
以上説明したように本発明は、識別信号発生回路を構成
する電子部品を選択することにより必要とする全ての論
理値を得ることができ、また、構成部品が全て電子部品
であるため、製造工程を増加させることがなく装置製造
を行なうときの製造原価を上げないという効果を奏する
。5-6- [Effects of the Invention] As explained above, the present invention makes it possible to obtain all necessary logical values by selecting the electronic components constituting the identification signal generation circuit, and also allows the component parts to be Since all of the components are electronic components, there is no need to increase the number of manufacturing steps and there is an effect that the manufacturing cost when manufacturing the device does not increase.
【図面の簡単な説明】
第１図、第２図は本発明の一実施例のブロック図である
。
ｌａ、２ａ−ＯＲゲート、１ ｂ、２ｂ・ ＡＮＤゲー
ト、１ ｃ、２ｃｍＮＡＮＤゲート、ｌｄ。
２ｄ・・・ＥＸＯＲゲート、１０〜１３，１５．２０〜
２３，２５．３０〜３３，３５．４０〜４３゜４５・・
・接続線、１・・・識別信号発生回路。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are block diagrams of an embodiment of the present invention. la, 2a-OR gate, 1 b, 2b AND gate, 1 c, 2cm NAND gate, ld. 2d...EXOR gate, 10~13, 15.20~
23, 25.30~33, 35.40~43°45...
- Connection line, 1...Identification signal generation circuit.
Claims (1)
はＥＸＯＲゲートで構成され、入力に固定値が与えられ
、必要とする情報処理装置の識別信号に応じて前記ＯＲ
ゲート、ＡＮＤゲート、ＮＡＮＤゲート、またはＥＸＯ
Ｒゲートを選択的に用いて回路を構成するようにしたこ
とを特徴とする識別信号発生回路。 ２、ＯＲゲート、ＡＮＤゲート、ＮＡＮＤゲート、およ
びＥＸＯＲゲートで構成され、入力に固定値が与えられ
、必要とする情報処理装置の識別信号に応じて前記ＯＲ
ゲート、ＡＮＤゲート、ＮＡＮＤゲート、ＥＸＯＲゲー
トを選択的に用いて回路を構成するようにしたことを特
徴とする識別信号発生回路。[Scope of Claims] 1. Consisting of an OR gate, AND gate, NAND gate, or EXOR gate, a fixed value is given to the input, and the OR gate is configured according to the identification signal of the required information processing device.
gate, AND gate, NAND gate, or EXO
An identification signal generating circuit characterized in that the circuit is constructed by selectively using R gates. 2. Consists of an OR gate, an AND gate, a NAND gate, and an EXOR gate, a fixed value is given to the input, and the OR gate is configured according to the identification signal of the information processing device required.
An identification signal generation circuit characterized in that the circuit is configured by selectively using a gate, an AND gate, a NAND gate, and an EXOR gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1319916A JPH0831078B2 (en) | 1989-12-08 | 1989-12-08 | Identification signal generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1319916A JPH0831078B2 (en) | 1989-12-08 | 1989-12-08 | Identification signal generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03180952A true JPH03180952A (en) | 1991-08-06 |
| JPH0831078B2 JPH0831078B2 (en) | 1996-03-27 |
Family
ID=18115665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1319916A Expired - Fee Related JPH0831078B2 (en) | 1989-12-08 | 1989-12-08 | Identification signal generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0831078B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61145786A (en) * | 1984-12-19 | 1986-07-03 | Pioneer Electronic Corp | Address allocating circuit |
-
1989
- 1989-12-08 JP JP1319916A patent/JPH0831078B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61145786A (en) * | 1984-12-19 | 1986-07-03 | Pioneer Electronic Corp | Address allocating circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0831078B2 (en) | 1996-03-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |