JPH0318025A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0318025A
JPH0318025A JP15191689A JP15191689A JPH0318025A JP H0318025 A JPH0318025 A JP H0318025A JP 15191689 A JP15191689 A JP 15191689A JP 15191689 A JP15191689 A JP 15191689A JP H0318025 A JPH0318025 A JP H0318025A
Authority
JP
Japan
Prior art keywords
oxide film
silicon oxide
film
silicon substrate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15191689A
Other languages
Japanese (ja)
Inventor
Tomoyuki Sasaki
智幸 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP15191689A priority Critical patent/JPH0318025A/en
Publication of JPH0318025A publication Critical patent/JPH0318025A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To make it possible po remove an insulating film without damages such as scraping of the surface of a substrate and causing of crystal defects by using a silicon oxide film containing carbon as impurities as an interlayer insulating film between wirings, and forming a protecting film on the surface of a silicon substrate in dry etching. CONSTITUTION:A silicon oxide film 12 containing carbon as impurities is deposited on a silicon substrate 11. A pattern 13 of a photoresist film is formed on the silicon oxide film. Then, the silicon oxide film 12 is removed by dry etching, and a pattern is formed. At this time, particles 14 of carbon incorporated in the silicon oxide film 12 as impurities flow out into the atmosphere of the system, and polymerization reaction occurs. Thus, macromolecular-state protecting film 15 containing carbon is formed on the surface of the silicon substrate 11. When the macromolecular-state protecting film 15 is deposited on the surface of the silicon substrate 11 in this way, the etching selecting ratio between the silicone oxide film 12 and the silicon subsstrate 11 as a ground can be improved. Thus, the interlayer insulating film can be selectively removed without damages on the surface of the silicon substrate.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、コンタクト形成に於いてシリコン基板の一主
面上にドライエッチング工程でシリコン基板に損傷を与
えずに除去できる層間絶縁膜を備えた半導体装置の製造
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor having an interlayer insulating film on one main surface of a silicon substrate that can be removed by a dry etching process without damaging the silicon substrate during contact formation. The present invention relates to a method of manufacturing the device.

従来の技術 従来、第2図に示す様にシリコン基板41の一主面上に
層間絶縁膜としてシリコン酸化膜42を形成した後(a
)、フォトレジスト膜43でパターン形成し(b)、さ
らにCHF3等のガスを用いたドライエッチングでシリ
コン酸化膜42を除去しパターン形成を行い(C)、フ
ォトレジスト膜43を除去した後(d)、アルミ配線4
6を形成する(e)方法が知られている。
Conventionally, as shown in FIG. 2, after forming a silicon oxide film 42 as an interlayer insulating film on one main surface of a silicon substrate 41 (a
), a pattern is formed with the photoresist film 43 (b), and the silicon oxide film 42 is further removed by dry etching using a gas such as CHF3 to form a pattern (c), and after the photoresist film 43 is removed (d ), aluminum wiring 4
A method (e) of forming 6 is known.

発明が解決しようとする課題 従来、第2図に示す様に層間絶縁膜として使われている
シリコン酸化膜22をドライエッチングで除去する時、
シリコン酸化膜と下地のシリコン基板とのエッチングの
選択比は、エッチングガスの反応系での圧力やRFバワ
ー(印加高周波電力)等の条件によって決められていた
。しかしこの場合、シリコン基板21とシリコン酸化膜
22とのドライエッチングの選択比(SiO2/Si)
は4.5程度しか得られず、シリコン酸化膜22をドラ
イエッチングで除去する時、シリコン基板2lも同時に
削り取るなどの損傷を与える事が問題であった。
Problems to be Solved by the Invention Conventionally, as shown in FIG. 2, when removing a silicon oxide film 22 used as an interlayer insulating film by dry etching,
The etching selectivity between the silicon oxide film and the underlying silicon substrate has been determined by conditions such as the pressure in the etching gas reaction system and RF power (applied high frequency power). However, in this case, the dry etching selectivity (SiO2/Si) between the silicon substrate 21 and the silicon oxide film 22
The problem is that when the silicon oxide film 22 is removed by dry etching, the silicon substrate 2l is also damaged by being scraped off at the same time.

本発明の目的は、下地のシリコン基板に対して高い選択
比で除去する事の出来る絶縁膜を備えた半導体装置の実
現することにある。
An object of the present invention is to realize a semiconductor device including an insulating film that can be removed with a high selectivity with respect to the underlying silicon substrate.

課題を解決するための手段 本発明は上記目的を達戒するために、層間絶縁膜に従来
のシリコン酸化膜の代わりに、不純物として炭素を含む
シリコン酸化膜を形威するものである。
Means for Solving the Problems In order to achieve the above object, the present invention uses a silicon oxide film containing carbon as an impurity in place of the conventional silicon oxide film as an interlayer insulating film.

作用 フロン系ガスを使ったドライエッチングでは、ドライエ
ッチング工程時に、シリコン基板表面上に高分子状の保
護膜を堆積することで、シリコン酸化膜と下地のシリコ
ン基板とのエッチングの選択比を向上させることは良く
知られている。これは、エッチングガスに含まれている
炭素やフッ素がシリコン基板表面上で重合反応を起こす
ためである。このとき、エッチングガスのC/F比が高
いと、重合反応の反応速度が増加することも知られてい
る。
In dry etching using fluorocarbon-based gases, a polymeric protective film is deposited on the silicon substrate surface during the dry etching process to improve the etching selectivity between the silicon oxide film and the underlying silicon substrate. This is well known. This is because carbon and fluorine contained in the etching gas cause a polymerization reaction on the silicon substrate surface. At this time, it is also known that when the C/F ratio of the etching gas is high, the reaction rate of the polymerization reaction increases.

本発明の構成によって、ドライエッチング工程でシリコ
ン酸化膜に含まれていた炭素が反応系に流出する。この
ため反応系のC/F比が高くなり、下地のシリコン基板
表面上で高分子状の保護膜の重合反応が促進される。
With the configuration of the present invention, carbon contained in the silicon oxide film flows out into the reaction system during the dry etching process. Therefore, the C/F ratio of the reaction system becomes high, and the polymerization reaction of the polymeric protective film on the surface of the underlying silicon substrate is promoted.

この保護膜により、シリコン基板表面はドライエッチン
グから守られ、シリコン酸化膜とシリコン基板とのエッ
チングの選択比が向上し、下地のシリコン基板表面には
損傷を与えず、不純物として炭素を含むシリコン酸化膜
だけを除去する事ができる。
This protective film protects the silicon substrate surface from dry etching, improves the etching selectivity between the silicon oxide film and the silicon substrate, and prevents damage to the underlying silicon substrate surface. Only the film can be removed.

実施例 以下本発明の実施例について、図面を参照しながら説明
する。
EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

第1図は本発明の第一の実施例を示したものである。ま
ずシリコン基板上11にCVD法により不純物として炭
素を含むシリコン酸化膜12を堆積させる(a)。次に
前記シリコン酸化膜上12にフォトレジスト膜のパター
ン13を形戒する(b)。
FIG. 1 shows a first embodiment of the present invention. First, a silicon oxide film 12 containing carbon as an impurity is deposited on a silicon substrate 11 by the CVD method (a). Next, a pattern 13 of a photoresist film is formed on the silicon oxide film 12 (b).

次にドライエッチングによりシリコン酸化膜12を除去
しパターンを形威する。この時シリコン酸化膜中12に
不純物として含まれている炭素の粒子14が系の雰囲気
中に流出し、重合反応を起こして、シリコン基板表面上
に炭素を含む高分子状の保護膜15を形成する(C)。
Next, the silicon oxide film 12 is removed by dry etching to form a pattern. At this time, carbon particles 14 contained as impurities in the silicon oxide film 12 flow out into the atmosphere of the system, cause a polymerization reaction, and form a polymeric protective film 15 containing carbon on the silicon substrate surface. (C).

次にアッシング,洗浄等によりフォトレジスト膜13及
び保護膜15を除去する(d)。
Next, the photoresist film 13 and the protective film 15 are removed by ashing, cleaning, etc. (d).

さらにシリコン基板,シリコン酸化膜上にスパッタ等に
よりアルミ配線16を形成する(e)。
Furthermore, aluminum wiring 16 is formed on the silicon substrate and silicon oxide film by sputtering or the like (e).

以上の方法により公知の技術を用いて形成された層間絶
縁膜はシリコン基板表面に損傷を与えずに選択的に除去
することができる。
By the above method, an interlayer insulating film formed using a known technique can be selectively removed without damaging the silicon substrate surface.

なお上記実施例においてシリコン基板上に絶縁膜を形成
するとしたが、シリコン基板は多結晶シリコン膜しても
よい。また、層間絶縁膜に不純物として炭素を含むシリ
コン酸化物を形成するとしたが、層間絶縁膜に不純物と
して炭素と燐の酸化物を含むシリコン酸化物、あるいは
、不純物として炭素と燐の酸化物ホウ素の酸化物を含む
シリコン酸化物を形威してもよい。
In the above embodiment, an insulating film is formed on a silicon substrate, but the silicon substrate may be a polycrystalline silicon film. In addition, we have assumed that silicon oxide containing carbon as an impurity is formed in the interlayer insulating film. Silicon oxide containing oxides may also be used.

発明の効果 以上のように本発明は、配線の層間絶縁膜に炭素を不純
物として含むシリコン酸化膜を用いることにより、ドラ
イエッチング行程時にシリコン基板表面上に保護膜を形
成し、シリコン基板表面を削り取る、結晶欠陥をひき起
こす等の損傷を与えずに絶縁膜を除去する事が実現でき
るものである。
Effects of the Invention As described above, the present invention uses a silicon oxide film containing carbon as an impurity for the interlayer insulating film of wiring, thereby forming a protective film on the silicon substrate surface during the dry etching process and scraping the silicon substrate surface. , it is possible to remove the insulating film without causing damage such as crystal defects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による断面構造を実現するための実施例
の断面工程フロー図、第2図は従来例の断面工程フロー
図である。 11・・・・・・シリコン基板、12・・・・・・不純
物として炭素を含むシリコン酸化膜、13・・・・・・
フォトレジスト膜、14・・・・・・ドライエッチ工程
で反応系に流出した炭素粒子、15・・・・・・ドライ
エッチ工程で堆積した保護膜、16・・・・・・アルミ
配線、21・・・・・・シノコン基板、22・・・・・
・シリコン酸化膜、23・・・・・・フォトレジスト膜
、24・・・・・・エッチングにより除去されたシリコ
ン粒子、25・・・・・・ドライエッチェ程で損傷した
シリコン基板部分、26・・・・・・アルミ配線。
FIG. 1 is a cross-sectional process flow diagram of an embodiment for realizing a cross-sectional structure according to the present invention, and FIG. 2 is a cross-sectional process flow diagram of a conventional example. 11...Silicon substrate, 12...Silicon oxide film containing carbon as an impurity, 13...
Photoresist film, 14... Carbon particles leaked into the reaction system during the dry etching process, 15... Protective film deposited during the dry etching process, 16... Aluminum wiring, 21 ...Shinocon board, 22...
・Silicon oxide film, 23... Photoresist film, 24... Silicon particles removed by etching, 25... Silicon substrate portion damaged during dry etching, 26 ...Aluminum wiring.

Claims (3)

【特許請求の範囲】[Claims] (1)シリコン基板の一主面上に、配線の層間絶縁膜に
不純物として炭素を含むシリコン酸化膜を被着する工程
と、該不純物として炭素を含むシリコン酸化膜上にホト
レジストをパターン形成する工程と、ドライエッチング
により該不純物として炭素を含むシリコン酸化膜をパタ
ーン形成する工程を含む半導体装置の製造方法。
(1) A step of depositing a silicon oxide film containing carbon as an impurity on one main surface of a silicon substrate as an interlayer insulating film for wiring, and a step of patterning a photoresist on the silicon oxide film containing carbon as an impurity. and a step of patterning a silicon oxide film containing carbon as an impurity by dry etching.
(2)層間絶縁膜に、不純物として炭素と燐の酸化物を
含むシリコン酸化膜を用いた特許請求の範囲第1項に記
載の半導体装置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is a silicon oxide film containing oxides of carbon and phosphorus as impurities.
(3)層間絶縁膜に、不純物として炭素と燐の酸化物と
ホウ素の酸化物を含むシリコン酸化膜を用いた特許請求
の範囲第1項に記載の半導体装置の製造方法。
(3) The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is a silicon oxide film containing oxides of carbon, phosphorus, and boron as impurities.
JP15191689A 1989-06-14 1989-06-14 Manufacture of semiconductor device Pending JPH0318025A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15191689A JPH0318025A (en) 1989-06-14 1989-06-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15191689A JPH0318025A (en) 1989-06-14 1989-06-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0318025A true JPH0318025A (en) 1991-01-25

Family

ID=15529002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15191689A Pending JPH0318025A (en) 1989-06-14 1989-06-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0318025A (en)

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