JPH03179775A - Semiconductor read-only memory - Google Patents

Abstract

PURPOSE:To obtain a ROM adapted for densification by a method wherein an auxiliary bit line connected to a memory cell is connected to another wiring once through the intermediary of a selection MOSFET, and the memory cell is made to read out data through a primary bit line. CONSTITUTION:Auxiliary bid lines bm.2l-2, bm.2l-1, bm.2l... are made to run between banks, and selection MOSFETs QO and QE used for the selection of banks are connected to the auxiliary bid lines so as to be located at both the sides of a bank B where n memory cells are provided. When a memory cell Mm.2l.2 is made to read out data, the memory cell concerned belongs to a bank Bm.2l located on a m-th column and a 2l-th row of a bank matrix and is connected to a second word line WL2. As it is located on a 2l-th row, it is an even-numbered bank. Therefore, when a bank selection line BEm is made high in level, auxiliary bid lines bm.2l-1 and bm.2l connected to the memory cell Mm.2l.2 are connected to primary bit lines Mbl-1 and Mbl respectively, because both bank selection MOSFETs QEm.2l-1 and QEm.2l are turned ON.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is directed to a semiconductor read-only memory (hereinafter referred to as ROM).
In particular, it relates to a ROM in which memory MOSFETs are connected in parallel.

<Prior Art> FIG. 3 is a diagram showing a ROM that has been widely used in the past, and has a horizontal ROMK configuration in which memory cells each consisting of a MOS FET are connected in parallel to a bit line.

In the figure, 1 is a word line, 2 is a bit line, and 3 is a memory cell. When reading ROM data, the word line of the corresponding memory cell is set to high level, one of the bit lines to which the source and drain of the memory cell are connected is grounded, and the other is connected to the sense amplifier as a read data line. The on/off state of the memory cell is detected (that is, data 1 or 0 is identified) and the data is read out.

<Problems to be Solved by the Invention> The above-mentioned horizontal ROM is more sensitive to memory cells during read operation than the vertical ROM in which a memory cell (memory cell) is connected in series to a bit line as shown in FIG. The on-resistance of JMOSFET is small,
It had the advantage of being easy to speed up.

However, as the capacity of ROMs increases, the number of memory cells connected to one bit line increases, which increases the parasitic capacitance of the bit line, which is mainly due to junction capacitance, and this becomes a factor that impedes speed increases. was. As a way to solve this problem, methods such as dividing the bit line to reduce parasitic capacitance have been devised, but this has the disadvantage of increasing the chip size.

Further, the horizontal ROM shown in FIG. 3 above uses metal wiring for the bit line, and the connection between the bit line and the memory cell is made by metal-diffusion (memory M
It is common to use a contact between the bit lines (corresponding to the source or drain of an OSFET) (hereinafter referred to as the metal bit line method), but as shown in A memo IJ M
A method of forming an O5FET gate (hereinafter referred to as a diffusion bit line method) is described in Japanese Patent Laid-Open No. 59-44787. In this case, the resistance of the diffusion layer is usually 10
00 times or more, so if the capacitance is increased, in addition to the increase in the parasitic capacitance of the bit line, the wiring resistance cannot be ignored, and factors that impede speeding up will further increase.

On the other hand, in the case of a metal bit line method in which bit lines are formed with metal wiring, wiring resistance is hardly a problem, but as microfabrication progresses, the space between metal wiring becomes narrower, so the capacitance between wiring increases rapidly. As the operating speed of the bit lines decreases, coupling noise between bit lines increases,
A shadow tII is also given to the operating margin. In addition, due to the increase in the number of metal-diffusion contact holes and metal wiring due to the increase in capacitance, contact hole-drilling defects during the process,
There is a problem in that the number of disconnections in metal wiring and short circuits between metal wiring increases, which causes a decrease in yield.

The present invention has been made in view of the problems of the conventional ROM described above, and provides an fcROM suitable for high density.

<Means for solving the problem> Press a button on a ROM consisting of multiple memory lJMO3FETs connected between adjacent bit lines, and select MOs on both sides of the bit lines.
A node that connects SFETs and connects the adjacent bit lines as a pair, and is connected with the pair relationship shifted between one side and the other side of the bit lines, and is connected to one node of the bit lines. The ROM is constructed by wiring the other node with a conductor different from that of the bit line. is connected to another wiring (hereinafter referred to as the main bit line), and in order to make it possible to read the data of the υ memory cell using this main bit line, a MOS F for selecting a sub-bit line that does not need to be read is used.
M for selecting the sub-bit line to be read with ET unselected
It is now possible to select only the OSFET, and the MOSFETs connected to the main bit supply are only the selection MOSFETs connected to unselected subbit lines, other than the memory sep connected to the selected subbit line.
The junction capacitance caused by the source or drain diffusion layer can be significantly reduced, making it possible to increase the speed. In particular, when the present invention is applied to a diffused bit line method, a low resistance wiring layer such as a metal wiring can be used for the main bit line.
The resistance caused by the diffusion wiring is only the resistance valve of the selected sub-bit line, and after passing through the selection MOSFET, it is connected to the low-resistance main bit line, so the overall resistance is sufficiently small and even higher speeds are possible. It is. In addition, since the present invention requires fewer main bit lines than the metal bit line method, the wiring pitch becomes gentler and the number of contact holes on the main bit lines is reduced.

<Example> FIG. 1 is a circuit diagram showing an embodiment of the present invention.

N memory cells in a parallel relationship are configured as one bank (area surrounded by a broken line in the figure), and the banks are arranged in a vertical and horizontal play pattern. A sub-bit line bm between each bank,
2g-21bm, 21-11E)m, 26. , , are running, and selection MOSFETs QO and QE for bank selection are connected to the respective sub-bit lines so as to be located on both sides of one puncture B in which n memory cells are provided. The selection MOSFET QO located on one side of the sub-bit line, that is, on one side of each puncture, is connected to the odd bank Bm, 2l-1t.
``Select, and the selection MOSFETQE on the other side is an even puncture BrrL.

2a, and the gate of each zV OS FET has a signal BO for selecting odd or even puncture gold.
m, BEm are given. MOS for selecting the above puncture
The output node X of the FET is connected to the adjacent outputs, e.g.
Em, 21-2 and Q Ern, 21-x are connected as a pair.

Here, the upper (QOIII) and lower (QEgll) nodes X 1 and X 2 of the puncture BrrL form a pair using the outputs of the puncture selection MOSFETs connected to different sub-211 212 bit lines. That is, the upper and lower sides form a pair with a shift of one sub-bit line tree length.

The outputs from the second group of punctures B71'L+1 located symmetrically in the column direction are also connected to the node to which the pair of outputs are connected. At this time, for the second group bank B1+1, the commonly connected output node X2 of the puncture selection MOSFET QE of the puncture BrrL has a shared structure.

In the large-capacity iROM, a plurality of punctures B are arranged in the row and column directions, and the arranged punctures are divided into even punctures and odd punctures depending on whether they belong to an odd numbered column or an even numbered column. The main bit line Mb is wired with a front tone 1. In this embodiment, as shown in FIG. 1, the main bit line Mb runs in a meandering manner, with the connection nodes alternating the nodes between odd punctures and the nodes between even banks every other bank row. The operation of reading a memory cell of a ROM consisting of the following configuration will be described.

First, the case of reading memory cell A/MrrL, 21.2 will be explained. This memory cell belongs to the puncture Bm, 2g in the breast row, column 2a, and is located on the second word line WL2.
connected to. Since it was the 21st row, it was an accidental puncture. Therefore, when puncture selection #1BErrL is set to high level, sub bit line b connected to memory cell Mm-21-2
rn, 21-1 and b-, 2g 'l''!, Nokunk selection MOSFET QErn, 21-1 and QEm, 2
g are both turned on, each main bit line Mbl-
1 and Mbl become conductive. Main bit line M b 1
-1 MOS for setting the Peng 11 bit line to ground level
The main bit line MJB is connected to the sense amplifier SA.The sense amplifier SA discriminates whether the selected memory cell has a conduction path with the ground level p. , and outputs it as data "1" or 0", and one sense amplifier SA is arranged for each of the four rows of negative groups. In this embodiment, presence of conduction path is 1", absence is "0". ”.

When the gate signal fv of the MOSFET Qg-t connected to the ground level is set to high level to turn it on, and the word line WL2 is set to high level, the memory cell Mrn, 211
-2 is on (detector "1"), main bit line MIB
is Q Ern, 2IJ"bm-21→Mm, 21-3→
bffl'21-1''QE9, 21-1→Mbl-1→
Since the Ql-t path has a conduction path with the ground level, the memory cell Mm, 21.2 is identified by the sense amplifier SA as having data "1'. Off (data "0") memo! In the JMOSFET If there is, the conduction path is cut off and the data is output as "0".

Next, the case of reading memory cells MrrL, zl-1, and 2 will be described. Since this belongs to odd bank Bm, 21-t,
Except for setting the puncture selection line BOrrL to high level, the memories MO8FETM, rrL, 21! , 2, and when the data is "1", the main bit line Mbl is Q01rL, 21-x→bWL, 21-1"My
rL, 2J? -1,2゜bm, 21-2゜QOrIL,
Since it is electrically connected to the ground level through the path 21-2→MJ-1-+J-1, it can be read as data "1" by the sense amplifier SA.

Among them, the method of setting the data of the memory MO3FET, that is, the method of setting on or off, is the conventional field method (also called diffusion method), which is set by the presence or absence of a transistor, or the ion method, which is set by the level of the threshold voltage of the transistor. Any method such as injection method may be used.

Also, when reading the data of memory cell)'Mm, 21+1.2, the sense amplifier SA is the same as the method described above, and the main beep)! ON/OFF of the memory MOSFET is identified through I M b 1, but the conduction path to the ground level is different and MOSFET Ql+1 is connected to the main bit line MJ+t.
The gate signal V6 is set to high level to turn it on, and the ground level and C conduction are identified through this path. The pan true selection line and the word line are selected in the same manner as in section m.

According to this embodiment, compared to the structure in which all memory IJM OSFETs in the column direction are connected to each pin M as shown in FIG. 3, the number of M□5FETCs connected to the main bit line is as shown in the following table. , and the reduction in parasitic capacitance due to junction capacitance is obvious.

Here, k is the number of punctures arranged in the column direction, and n is the number of memory MOSFETs in the puncture.

In the conventional configuration, memory cells are located on both sides of one bit line, so there are 2-n memory cells.

- In the old book embodiment, the n included in the puncture is determined for each of the main bit lines on the sense amplifier side and the ground level side to which the selected memory cell is related via the puncture selection MOSFET.
yt Morrissey w number, that is, 2n memory cells are positioned, and 4(k++) selection MOSFETs whose output nodes are connected to the main bit line are positioned,
The result will be as shown in the table above.

Although it cannot be compared simply by the number of MOS FETs, n
=16 and =128, the number of MOSFETs connected to the main bit line is 4096 in the conventional system and 548 in this embodiment, which is a reduction of about 14%.

Next, FIG. 2 shows a pattern diagram when the circuit of FIG. 1 is implemented using a diffused bit line method. In the figure, a region under polysilicon that is located between adjacent sub-bit lines formed from a diffusion layer and becomes a word line is a memory cell/L.
/MOSFET channel N, and M for puncture selection is formed on both sides 1 of the bank of each sub-bit mb.
O3FETs QO and QE are formed, and a contact hole X for connection to a main bit line Mbl formed by a metal line is provided in a diffusion region corresponding to the output of the MO9FET. The contact at the upper end of the puncture) Therefore, a total of four puncture selection M□5FETCs from two punctures are connected to one contact l-X.

According to this embodiment, as described above, the junction capacitance of the bit line (the former is the main bit M) is reduced compared to the ordinary metal bit line method shown in FIG. The number of contacts and the wiring pitch are reduced to about -1, and the number of contacts is reduced to about -1 (however, the number of contacts is reduced to about -1
The number of contact holes and metal wiring can be reduced (n pieces/puncture), which greatly affects product yield. On the other hand, in terms of operating speed, it is possible to reduce the parasitic junction capacitance of metal bit lines and the capacitance between metal interconnects, making it possible to increase the speed.Furthermore, the coupling noise due to the capacitance between bit lines is reduced, which improves the operating margin. Improvements can also be expected.

Furthermore, in the structure of this embodiment, since it is only necessary to arrange one metal bit line as a main bit line for every two diffused sub-bit lines, the bit line pitch is the same as that of the conventional diffused bit line system shown in FIG. The main bit line resistance can be reduced to the same level as the metal bit line method while maintaining the same level of resistance.

Is the above embodiment a mask ROM'? Although E
It is applicable to any semiconductor read-only memory such as PROM, E2PROM, etc. in which a plurality of memory cells are arranged in a matrix.

<Effects of the Invention> According to the present invention, it is possible to reduce the parasitic capacitance of bit lines, the number of wiring resistance lines, and the number of contacts of memory cells, and therefore it is possible to provide a highly integrated and high-performance ROM. .

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a pattern diagram of the surface of a semiconductor substrate of the same embodiment, Figs. 3 and 4 are circuit diagrams of a conventional device, and Fig. 5 is a conventional device. FIG. 6 is a surface view of a conventional metal bit line type substrate. B: Puncture M: Memory cell QO, QE: MOSFET for puncture selection BO, BE: Puncture selection line
WL: Word line Mb: Main bit m b: Sub bit line SA: Sense amplifier

Claims (1)

[Claims] 1. A plurality of bit lines, a plurality of memory MOSFETs whose sources and drains are the adjacent bit lines, a selection MOSFET whose one end is connected to the bit line, and mutually adjacent bits. Selection MOSFE connected to line
A node that is commonly connected as a pair between the other ends of T, and in the selection MOSFETs on both sides of the same bit line, the pair is selected by shifting the adjacency relationship between one and the other, and the node on one side of the bit line 1. A semiconductor read-only memory comprising: and a wiring that is tangential between the nodes on the other side.