JPH02306496A - Address decoder circuit - Google Patents

Abstract

PURPOSE:To obtain an address decoder circuit where the characteristics are unified in response to the minute memory cells by arraying the transistors of a column gate at two stages and collecting four transistors into a single block. CONSTITUTION:Four N channel transistors TR T0 and T3 are set at an upper stage together with the N channel TR T1 and T2 set at a lower stage respectively. These four TRs form a single block. In other words, the sources of T0 - T3 are common to each other via a dispersion part. As a result, the space factor is improved. The address lines are arranged descendingly like AD0, AD3... AD1, AD2.... The extended positions of polysilicon are set equal to each other between the TR T0 and T3, and the extended positions of polysilicon are increased by an extent equal to about one stage for the TR T1 and T2 respectively. Thus the characteristics of these TRs are uniformed. As a result, an address decoder circuit which can withstand a minute state is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application 1] The present invention relates to an address decoder circuit, particularly a column decoder circuit, for selecting addresses of memory cells used in ROM, RAM, etc. in a semiconductor memory device.

[Prior Art] The increase in the capacity of semiconductor memory devices has been so remarkable that even in recent years, there is no sign of stopping.

In general, semiconductor memory devices have been developed with a capacity 2'' times larger, but if memory cells are configured using the same design rules as before, the area of the memory cell will naturally become 21' times larger.ROM, RAM The chip size of semiconductor memory devices such as the Therefore, the chip size must be kept down and the design rules must be tightened to reduce the area per unit capacity.If we aim for the same chip size, the vertical and horizontal dimensions per unit capacity are IJ2''' is the goal.

Decoder circuits for address selection are arranged in a pattern closely related to the pitch of memory cells. Therefore, as the memory capacity increases, the arrangement pitch of the decoder circuits becomes narrower. Furthermore, the capacitance and resistance per bit line increase as the capacity increases, even when taking into account the division of the memory cell array for higher speed. Therefore, the size of the deduper buffer also becomes large.

Placing large size decoder circuits on a narrow pitch leads to a significant increase in length in the opposite direction to the pitch. This is not a big problem if the arrangement method is taken into consideration, since there is some distance from the memory cell except for the part directly connected to the memory cell. However, bit lines directly connected to memory cells must be arrayed at the same pitch as the memory cells, so even if the pattern design is the same as the design rules for memory cells, the size of the MOS transistors must be smaller than that of the memory cells. Since they are very large, how to arrange them becomes an important issue.

FIG. 2 shows a typical column address decoder circuit used conventionally.

In Figure 2, A. ~The address of An is (n+1)/
Assume that the states of the two addresses are indicated by positive logic. P channel Mo whose above address is indicated by MPO to MPn
5) It is input to an (n+1) input NAND gate consisting of a transistor and an N-channel MOSI-transistor indicated by MNO to MNn, and one address is selected. The output signal of this NAND gate is the P of M1 and M2.
It becomes a positive logic output through an impark composed of an N-channel MOS transistor and is input to the column gate of M3, which is an N-channel MC1S transistor. The drain side of this column gate becomes a bit line and is directly connected to the memory cell at the address, and the other source side is connected to the number of decoded (n+1) 72 addresses, that is, 2 + n + N/i real addresses. It is common and input to the sense amplifier.

FIG. 3 shows a conventional column gate layout diagram corresponding to four bit lines.

In Figure 3, four N-channel MOS transistors are arranged horizontally in a row, and the sources of each two transistors are shared by a diffusion part, and are further connected by an AL wiring below the transistors for sensing. It is passed to the amplifier side. As memory capacity increases, arranging memory cells at a narrower pitch means narrowing the pitch of the bit lines, which simply means that the lateral width of the gate, drain, and source of the transistor will increase. This also applies to narrowing the width. When thinking about reducing the size of transistors, the first option is to narrow the width of the polysilicon of the gate electrode, but this has limitations in the manufacturing process and requires a significant reduction in size. can't do what you want. There is also a method of narrowing the width of the diffusion portion, but this also may cause the characteristics of a MOS transistor to be unsatisfactory due to slight mask misalignment in the process. Therefore, there is a natural limit to the method of miniaturizing the lateral width of a transistor, and it can be said that it is difficult to narrow the pitch of bit lines in the conventional arrangement.

[Problems to be Solved by the Invention] For the above reasons, there is a process limit to narrowing the pitch in the bit line spacing direction by miniaturizing MOS transistors, so the present invention narrows the pitch by changing the arrangement. The purpose is to provide column gates.

[Means for Solving the Problems] The column gate of the present invention is not one in which MOSI transistors are arranged in a line in the bit line spacing direction as in the conventional case, but in which MOSI transistors are arranged in multiple stages to increase the lateral width of the gate, drain, and source. It is characterized by narrowing the pitch in the bit line spacing direction without impairing the bit line spacing.

〔Example〕

FIG. 4 is a pattern layout diagram of a column gate according to an embodiment of the present invention, and similarly to FIG. 3, it shows a pattern layout corresponding to four bit lines.

In Figure 4, four N-channel transistors are T
It has a two-stage configuration with O and T3 arranged in the upper row and T1 and T2 arranged in the lower row.In contrast to the two bare transistors in the pattern layout in Figure 3, there are four transistors. constitute one block. In other words, the source of To-T3 is common in the diffusion section,
This improves the space factor. If the number of stages is three, six transistors will form one block, and the source will be common, further improving the space factor. Furthermore, by making the shapes of the upper and lower transistors as similar as possible during pattern design, variations in transistor characteristics are reduced.

Another point worth noting is the polysilicon (shaded area in the upper right corner of the figure) that also serves as the gate electrode. The bit lines connected to the memory cells are arranged in a good order with directionality, and in FIG. 3.4, the BLO side is on the lower side and the BLB side is on the higher side. If the transistors are lined up in a horizontal line as shown in Figure 3, the AL wiring ADO to AD3 of the address lines input to the column gates can also be lined up regularly, and by making the length of the polysilicon uniform, the gate electrode The capacitance component added to can also be made uniform. However, when transistors are arranged in two stages as shown in Figure 4, if the entire length of the polysilicon is extended to a certain position (for example, the AL wiring position of the topmost address line), the transistor Since the length of the polysilicon from the gate of the upper stage is different from that of the lower stage, the capacitance component added to the gate is naturally different, and there is a possibility that the characteristics of each transistor cannot be maintained uniformly. Therefore, the AL wiring of address lines ADO to AD3 is arranged irregularly to compensate for the length of polysilicon due to the arrangement of transistors, and to make the capacitance components attached to the gate electrodes almost equal. Address line is ADO from above
1AD3...ADl, AD2... and TO
The extension positions of the polysilicon of T3 and T3 are made equal, and Tl and T3 are
The characteristics of each transistor are made uniform by arranging them so as to be extended by about one stage of transistors.

If transistors are arranged with such consideration, it is possible to configure a column gate with three or more stages.

Therefore, by arranging the transistors according to the present invention, the space factor in the bit line spacing direction is improved, and an address decoder circuit that can withstand increasingly finer technology in which the characteristics of each transistor are made uniform can be created.

[Effect of the invention 1 As explained above, by arranging column gate transistors in two stages and arranging four transistors in one block, the characteristics can be made uniform to accommodate miniaturized memory cells. We can provide address decoder circuits,
Furthermore, by increasing the number of column gate transistors, it becomes possible to support a semiconductor memory device with a larger capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a typical semiconductor memory device (ROM). FIG. 2 is a typical conventional address decoder circuit diagram. FIG. 3 is a pattern layout diagram of a conventional column gate. FIG. 4 is a pattern layout diagram of a column gate according to the present invention. MPO~MPn%Ml...P channel MOS transistor MNO~MNn, M2, M3, TO~T3...
・N-channel MOS transistors BLO to BL3 ・Bit line 5AIN...Input signal ADO to sense amplifier
AD3...AL wiring N+ of real address...
Diffusion layer CN of N-channel M○s transistor... Connection contact between N+ and AL CA... Connection contact between polysilicon and AL Applicant: Seiko Epson Corporation Agent Patent attorney Suzu Ki Sanbu (1 person) (Bi Zhuoken, <<<

Claims (1)

[Scope of Claims] A region having a function of selecting a column line in a memory array, and arranged adjacent to the memory array region and having MOS transistors arranged two-dimensionally; a plurality of selection line regions for supplying signals to the gates of each of the MOS type transistors in the address decoder circuit, the address decoder circuit comprising: The gate is taken from a selection line in the selection line region that is as far away as possible from the adjacent transistor, and the gate of a transistor located away from the selection line region among the transistors in the transistor array region is taken from the selection line region. The wiring length from the gate of each transistor in the transistor array area to each selection line in the selection line area is taken from the selection line close to the transistor array area among the selection lines in the transistor array area. Characteristic address decoder circuit.