JPS6057962A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the area of isolation regions between elements, and to enhance the degree of integration of memory cells at a mask ROM consisting of MOSFETs by a method weherein the drain regions of the memory cells of the plural number are made in common. CONSTITUTION:The gates of the MOSFETs of respective memory rows in a memory array 11 are connected to common word lines W (4) and the drains of the MOSFETs of respective memory columns are connected to common data lines of three pieces D1-D3 (6). The word line of one piece corresponding to the address signal Ax of an X interrelated group out of the word lines W is set to a selection level by an X decorder 12, the word line of one piece corresponding to an address signal Ay of Y interrelated group out of the data lines D is set to a selection level by a Y decorder 13, and reading out of data is executed by detecting existence of a current flow to the drain of the MOSFET positioning at the cross point thereof. Accordingly, storing and reading out of information of three bits can be attained by the MOSFET of one piece, and enhancement of the degree of integration of the memory cells can be attained.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor technology and also to semiconductor storage devices. It is about effective techniques.

[Background technology]

For example, insulated gate field effect transistor (MOSF)
In a read-only mask ROM (read-only memory) using a memory cell (ET), the data rewriting method is determined by whether or not a contact hole is formed at the drain of the MOSFET that constitutes the memory cell. There is a method of writing information of 0'' or 1'' depending on whether or not the drain terminal is connected to the data line.

However, in such a mask ROM, one MOSFET is formed for one memory cell, so even if the microfabrication technology is Advanced X7, the isolation region for each memory element can be omitted. As the memory capacity increases, the chip size becomes larger and larger, resulting in a lower yield.

[Purpose of the invention]

An object of the present invention is a) to provide a semiconductor integrated circuit device that can achieve high integration.

Another object of the present invention is to provide a semiconductor memory device which can increase the capacity without increasing the chip size by 11@VC.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows.

That is, in a mask ROM composed of MO8FE'l'', the area of the isolation region between elements is reduced by making the drain region of a plurality of memory cells common, and the chip size is reduced by improving the degree of integration of the memory cells. This is to achieve the above purpose.

[Embodiment 1] FIGS. 1 and 2 show a first embodiment in which the present invention is applied to a memory cell of a mask ROM consisting of a MOSFET.

In this embodiment, one MOSFET constitutes a 3-bit memory cell, and two such 3-bit MOSFETs are shown in the figure. That is, an N-channel type or P-channel type MOSFET is mounted on a single semiconductor substrate 1 such as a silicon chip.
Diffusion layers 2d, 2d constituting the drain regions of , and diffusion N2S forming the common source region of the two MO8FETQ, . . . Qt are formed by selective thermal diffusion. Diffusion layer 2
A gate oxide film 3 is formed on the substrate surface between S and 2d, 2d.
is formed, and a game ht made of polysilicon etc. is formed on it.
&4.4 is formed 4. ing.

These gate electrodes 4, 4 are formed continuously so as to traverse the inside of the memory array, and constitute a common word line for each memory row.

Further, an interlayer insulating film 5 such as a PSG film (phosphorus silicon glass film) is formed on the gate electrodes 4, 4, and aluminum wiring lines 6, 6°, etc. are formed on the interlayer insulating film 5. . This aluminum wiring 6 is formed continuously so as to cross within the memory array, and constitutes a common data line for each memory column. In this embodiment, the diffusion layer 2d serving as the drain region is a conventional memory cell (MO
SFET), the aluminum wiring 6 is formed to be wider in the line width direction, and three aluminum wirings (data lines) 6 can be arranged at an appropriate pitch on one diffusion layer 2d. .

Further, the diffusion layer 2s as the common source region is formed to be continuous in the vertical direction of the memory array, similarly to the polysilicon gate electrode 4 as the word line, and is connected to the ground of the circuit at one end. There is.

In this embodiment, each horizontal aluminum wiring (data M) 6
However, by appropriately designing a mask for making a hole in the interlayer insulating film 5, it is possible to decide whether or not to connect the diffusion layer 2d as a drain region. ℃, '1'' or O'' depending on whether to form the contact hole 7 for contact at
information is written.

When the contact hole 7 is formed, the aluminum wiring (data line) 6 and the diffusion layer 2d (drain region) are connected.
If the contact hole 7 is not formed, there will be no connection between the two. Therefore, when the appropriate word line (4) and data line (6) are set to the selection level, if the data line and drain region are connected in the memory cell at the intersection, a current will flow between the source and drain. flows between the source and drain, and if no connection is made, no current will flow between the source and drain. By determining the presence or absence of this current, the data
It is possible to read out ``1'' or ``0''.The surface of the aluminum wiring 6 is covered with a thin film 8 shown in FIG.
A field fermentation film 9 is formed on the top of the substrate surface around S F E T Q + , t Qt, and other MOSFE
The elements are separated from each other.

FIG. 3 shows a circuit configuration of a mask ROM using the MOSFET having the above configuration as a memory cell. As is clear from this drawing, the gates of MO8F'ETs in each memory row in the memory array 11 are connected to a common word line W(4), and the drains of MOSFETs in each memory column are connected to three common data lines. ri1. Connected to Dt, D, (6). and.

One of the word lines W corresponding to the Y-system address signal AXVC is set to a selection level by the X decoder 12,
One of the data lines corresponding to the Y-system address signal Ay is set to a selection level by the X decoder 13, and a sense amplifier (not shown) detects whether or not current flows to the drain of the MOSFET located at the intersection. Data reading is performed by.

In other words, according to this embodiment, 3-bit information can be stored and read using one MOSFET, making it possible to highly integrate memory cells. Moreover, X, X
The peripheral circuits including the decoders 12 and 13 may have the same configuration as before.

[Embodiment 2] FIGS. 4 and 5 show a second embodiment in which the present invention is applied to a mask ROM.

This example uses a known multilayer wiring technology, and
Four data lines (
6) can be connected, and the degree of integration of memory cells can be further increased.

In other words, the width of the aluminum wiring 6 constituting the data line is made as small as possible to reduce the wiring pitch of the data line. The aluminum wiring fl bulge 16 is formed in consideration of the alignment margin with the mask. In addition, adjacent wirings are each formed of separate aluminum layers with interlayer insulating films 10 interposed therebetween, thereby making it possible to further reduce the wiring pitch. That is, in FIG. 4, the second and fourth aluminum wirings 6b and 6d are formed of the first layer of aluminum, and the first
The third and third aluminum wirings 6a and 60 are formed by photo-etching the second layer of aluminum deposited on the surface of the interlayer insulating film 10 such as the PSG film formed on the aluminum wirings 6b and 6d. It is. Moreover, the contact holes 7 to the first layer aluminum wirings 6b and 6d and the second
Contact hole 7' to layer aluminum wiring 6a, 6c
and are alternately shifted in the horizontal direction so that they are not lined up on the same straight line. As a result, when the wiring pitch is minimized, the contact holes 7/t of the second layer aluminum wirings 5a and 6c, the first layer aluminum wiring 6b,
The distance from the bulge 16 where the contact hole 7 of 6d is formed can be increased compared to the case where the contact holes are arranged on the same straight line, which prevents short circuits between wirings and also reduces the wiring pitch. You will be able to make it smaller.

According to this embodiment, one MOSFET can constitute a 4-bit memory cell.

Note that the other configurations except for the multilayer wiring of the data lines and the number and arrangement of contact holes are completely the same as in the first embodiment, so explanations thereof will be omitted.

In the first and second embodiments, three and four contact holes 7 are provided for the common drain region 2dK, respectively.
Although it is possible to form a 3-bit or 4-bit memory cell with one MOSFET, the number of bits is not limited to this, and can also be 2 or 5 or more bits.

In addition, by applying the VC two-layer wiring technology of the first embodiment, wiring is formed in parallel to the word line (4) instead of providing a diffusion layer that connects the common source region 2S vertically to the ground. Then, the source regions of the MOSFETs in each memory row may be connected to this.

Furthermore, the aluminum wiring is made into a three-layer structure, the pitch of the data lines is made smaller, and the number of bits of one MO5FET is increased to improve the degree of integration of the memory cell. It is also possible to provide and connect aluminum wiring instead of the diffusion layer for coupling.

Moreover, in a mask ROM of the type described in the embodiment, the rewriting of stored data is performed by changing the mask used to form contact poles. Compared to mask ROMs that use rewritable methods or ion implantation, the process of changing the truncation process is later in the process.
RO called TAT (turn around time)
Although there is an advantage that the period required for changing the M IC is short, there is a disadvantage that the area occupied by the memory array increases. The area of the array can be reduced. Therefore, it is possible to shorten TA'l' in the mask ROM and reduce the chip size.

〔effect〕

(1) MO8F forming memory cells of mask ROM
Since the drain region of the ET can be shared by a plurality of memory cells, there is no need for an element isolation region at least between memory cells that share a common drain region, which improves the degree of integration of memory cells. This has the effect of reducing the chip size ζ and improving the chip yield.

(2) MO8F constituting the memory cell of mask ROM
In addition to allowing multiple memory cells to share the drain region of the ET, the data lines can be wired in multiple layers using multilayer wiring technology, reducing the pitch of each data line in the memory array. Due to this ability, the chip size of the memory can be further reduced.

(3) Mask R in which stored data is rewritten by changing the mask used to form contact holes.
In OMVC, the MOSFET that constitutes the memory cell
By sharing the drain region of the memory cell with multiple memory cells, the element isolation region between the memory cells is reduced, which has the effect of shortening the TAT and reducing the chip size. .

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the embodiment described above, the mask ROM is applied to a type of mask ROM in which rewriting is performed by changing the contact hole. It can also be applied to ROM.

Furthermore, in the above embodiment, a plurality of memory cells have a common drain region and a data line is connected thereto, but a plurality of memory cells have a common source region and a data line is connected thereto. May be busy to be joined. For example, in FIG. 1, 2d may be the source region and 2S may be the drain region. In this way, the region to which the data line should be coupled is one output region (drain region or source region) for forming the main conductor path of the MOSFET.
That's fine.

[Application field]

In the above explanation, the invention made by the present inventor has mainly been explained in terms of the technology for configuring memory cells in mask ROM, which is the field of application behind the invention, but is not limited thereto, and can be applied to MO8 integrated circuits in general. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment in which the present invention is applied to a memory cell of a mask ROM, FIG. 2 is a sectional view taken along the line T in FIG. 1, and FIG. 3 is a memory cell of the above embodiment. FIG. 4 is a plan view 1 showing another embodiment of the present invention, and FIG. 5 is a sectional view taken along the line V--■ in FIG. 4. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2d... Diffusion layer (drain region), 2s... Diffusion layer (source region), 3... Gate oxide film, 4... Gate electrode (word line), 5, 10・
...Interlayer insulating film, 6,6a-6C...aluminum wiring (data line), 7.7'...contact hole, 11...
・Memory array. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. A plurality of wirings are made contactable with one of a source region and a drain region formed on a semiconductor substrate so as to sandwich a channel portion below a gate electrode. A semiconductor integrated circuit device comprising an insulated gate field effect transistor. 2. The above-mentioned insulated gate field effect transistor can be used as a memory element in which information is stored by connecting an arbitrary data line or word line to the source or drain region depending on whether a contact hole is formed or not. A semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is used. 3. The above-mentioned plurality of wirings are formed in a multilayer state and are made to be able to contact a common source or drain region of the insulated gate field effect transistor. Semiconductor integrated circuit device # according to item 1 or item 2.