JPH0317891A - Dynamic memory refresh system for computer - Google Patents

Abstract

PURPOSE:To reduce fresh time by switching a refresh fundamental clock to a different frequency with a first selector, and switching a refresh request cycle with a second selector. CONSTITUTION:A clock CK1 from a clock oscillator 7 and a clock CK2 from a clock oscillator 8 are supplied to the first selector 10. Also, a clock CK3 from a clock oscillator 9 and a clock CK4 from a clock oscillator 12 are supplied to the second selector 11. A mode switching register 13 controls the switching operation of the selectors 10 and 11. Here, the selector 10 is the one to switch the fundamental clock of a refresh controller 4, and the cycle speed of refresh can be doubled and the refresh time can be reduced to the half by switching a clock from the clock CK2 to the clock CK1. Also, the selector 11 switches the refresh request cycle. Thereby, the refresh time can be reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a dynamic memory refresh method in a small computer such as a personal computer, and in particular to a method for reducing refresh time while maintaining compatibility with existing models. Regarding improvements to make it possible. [Summary of the Invention] In a computer having a dynamic main memory, an expansion bus slot, etc., by configuring the memory and expansion bus slot to be refreshed by switching, the computer is compatible with existing models, and the refresh time is shortened. It is designed to shorten the . [Conventional technology] Some personal computers having an expansion bus slot supply a refresh timing signal to a dynamic memory (DRAM) added to the expansion bus. Figure 2 shows an example of such a conventional computer. In the figure, 1 is the central processing unit (CPU), 2 is the dynamic main memory (main board D
RAM), 3 is an expansion bus slot, 4 is a refresh controller, 5 is an address bus switching switch circuit, 6
is an address bus, 7 is a clock oscillator for supplying a clock to the CPUI, and 8 is a refresh controller 4.
A clock oscillator 9 supplies a basic refresh timing signal to the refresh controller 4, and a clock oscillator 9 supplies a refresh cycle to the refresh controller 4. Using this clock, the refresh controller sends a bus hold request signal to the CPU, and the refresh cycle starts when a hold response signal is returned from the CPU. The counter 4a counts this clock and supplies a refresh address according to the count value to the dynamic memory and dynamic main memory of the expansion bus slot 3. In addition, each timing signal (REF, MRD) of the refresh cycle is also supplied at the same time. In the computer described above, the dynamic main memory and the dynamic memory on the expansion bus are refreshed by the timing signal, and the timing of this signal may also be specified as an expansion bus slot signal. For this reason, even if the CPU speed becomes faster or the dynamic main memory 2 becomes more high-performance, the refresh timing needs to be kept at the old slow timing in order to maintain compatibility with conventional models. However, with the recent increase in the speed of personal computers, attention has been focused on reducing the time required for refreshing, and the following methods are available. (B) A method to do this by finding free time on the bus (1) A method to divide memory into blocks and alternate access and refresh (3) A method to have the CPU perform refresh [Problem to be solved by the invention] However, the above-mentioned problem Each method is not compatible with existing models. Moreover, the circuit changes required to implement this method are large-scale, making it impractical. [Object of the Invention] Therefore, the object of the present invention is to provide a dynamic memory refresh method for a computer that ensures compatibility with existing models and also enables reduction of refresh time with a slight circuit change. [Means for Solving the Problems] In order to achieve the above object, the present invention provides at least a central processing unit, a dynamic main memory expansion bus slot, control of refresh of the central processing unit, and control of the dynamic main memory and bus. In a computer equipped with a refresh controller that performs refresh to a slot, first and second selectors are provided, and in response to a mode switching signal, the first selector changes the basic refresh clock given to the refresh controller to a different frequency. The purpose of the second selector is to switch the refresh request cycle. [Function] Refresh basic clock and refresh request cycle that can maintain compatibility with existing models by switching the first and second selectors. Alternatively, the basic clock and refresh request cycle can be selected to reduce the refresh time.

[Examples] The present invention will be described below with reference to examples shown in the drawings. FIG. 1 shows an embodiment of a dynamic memory refresh method for a computer according to the present invention, and the same reference numerals as in FIG. 2 indicate the same or similar circuits. In this figure, the structure differs from that in FIG. 2 in that first and second selectors 10 and 11, a clock oscillator 12, and a mode switching register 13 are provided. The first selector 10 includes a clock oscillator 7
clock CK1 (for example, 16 MHz) from clock oscillator 8 and clock GK. (e.g. 8M&) is supplied. The second selector 11 also receives a clock GK from the clock oscillator 9 (for example, 64 KHz (1
5. ) and the clock GK.6 μs) from the clock oscillator 12. (For example, 8KHz (125μs)) is supplied. The mode switching register 13 controls the switching operation of the first and second selectors 10 and 11. For example, the mode switching register 13 controls the switching operation of the first and second selectors 10.11. Perform switching. In other words, if there is no expansion board in the expansion bus slot that requires refreshing, and if the specifications of the dynamic main memory (access time, refresh request timing) are known, and if these conditions are established, the information In order to set the mode switching register 13 and select a clock that can reduce the refresh time,
Switch between the first and second selectors 10.11.
For example, the first selector 10 switches the basic clock of the refresh controller 4. If the clock CK2 is switched to the CPU clock CK1, the refresh cycle speed will be doubled, and the refresh time will be halved. Reduced. In this case, as mentioned above, the CPU clock GK, is 16M&,GK,
If the existing CPU clock is set to 8MHz, compatibility with existing models will be ensured.

For example, if the timing of the refresh request cycle of the dynamic memory used as the main memory is 78 msec (15.6 μs) at the 5/2 address, the second selector 11 selects the clock GK, and reduces the refresh rate. If the main memory is composed only of dynamic memory with a refresh request cycle specification of 5/2 addresses/64 msec (125 μs), the clock GK. If you select , the number of refreshes will be reduced to 1/8. In addition,
The clock CK1 is not exclusive to the CPU, but may be obtained from a separately provided clock oscillator, and the mode switching register is not limited to one operated by software. [Effects of the Invention] As explained above, according to the present invention, it is possible to reduce refresh time of dynamic memory by adding a simple structure while maintaining compatibility with existing models, and moreover, it is possible to reduce refresh time of dynamic memory while maintaining compatibility with existing models.
It is possible to respond to future technological trends such as faster PUs and higher performance dynamic memory (DRAM), and is particularly effective when applied to small computers such as personal computers.

[Brief explanation of drawings]

Claims (1)

[Claims] A computer comprising at least a central processing unit, a dynamic main memory expansion bus slot, and a refresh controller that controls refresh of the central processing unit and refreshes the dynamic main memory and bus slot. A selector is provided, the first selector switches a refresh basic clock given to the refresh controller to one of a different frequency in response to a mode switching signal, and the second selector switches a refresh request cycle. Dynamic memory refresh method.