JPH031786A - Picture quantization circuit - Google Patents

Abstract

PURPOSE:To quantize lots of difference picture element data at a high speed by providing an address register for an external quantization table ROM independently so as to attain quantization with a minimum clock cycle number. CONSTITUTION:A picture data before quantization is read out of an internal RAM 31 and stored tentatively in an external address register 33. In the next clock cycle, the stored picture data of the external address register 33 is used to access a quantization table memory 32 and the address to the internal RAM 31 is updated is to read a picture data. Thus, the readout access to the internal RAM 31 and the quantization table memory 32 is implemented simultaneously in the same clock cycle to attain high speed quantization processing. Moreover, a selector 34 is controlled to fix a high-order bit of an external address register 33 and only the word length of the quantized picture data is written in the external address register 33 and the index of the memory to an external expansion port is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to an image quantization circuit that quantizes image data in an image signal processing processor or the like.

The purpose is to speed up the quantization process and to facilitate the allocation of memory addresses to external expansion boards.It is equipped with an internal RAM for storing image data and an external quantization table memory, and is equipped with an internal RAM that stores image data and an external quantization table memory that can be read from the internal RAM. An image quantization circuit reads quantized image data from an external quantization table memory using the pre-quantized image data as an address and stores it in an internal RAM. It is characterized by comprising an external address register that provides an address to an external quantization table memory, and a selector that inputs pre-quantized image data to the external address register while fixing the upper bits of the external address register.

[Industrial Field of Application] The present invention relates to an image quantization circuit used in an image signal processing processor or the like, for example, when differentially quantizing a difference pixel block between a current pixel block and a predicted pixel block.

With the recent demand for faster image signal processing, nXn (
n = 4.8.16, etc.) The pixel block is band-compressed by differential quantization processing, sent to the transmission path, and then dequantized and added to the predicted pixel block on the receiving side. Image processing codec (encoder/decoder) to obtain reproduced images
There is a need to realize this using digital signal processing circuits. For this reason, 2-bot RAM and address generation circuits that can handle pixel data at high speed are provided, but there is a need for even faster image signal processing, and it is also necessary to miniaturize the circuit. It is said that

[Conventional technology] A conventional example of an image quantization circuit is shown in FIG.

In the figure, 1 is a 2-port RAM, which has two independently accessible output ports A and B.

2.3 is boat A with 2 boats RAMI each.

An address generation circuit that generates an address for B. 4 is a data bus on the side that carries data on the side of boat A of the 2-bot RAMI. 5 is a data bus on the B side that carries data on the side of boat B of the 2-bot RAM 1. It is. Further, 1O111 is a terminal as an external expansion board for connecting a quantization table ROM 12 etc. externally attached to the quantization circuit,
Terminal 10 is an external address terminal that outputs an external address signal EA to an external circuit, and 11 is an external data terminal that takes in external data ED from the external circuit. External data input from the external data terminal 11 is transferred to the B-side data bus 5 via the buffer circuit 9. Quantization table I2
is a conversion table for quantizing differential pixel data, and using the differential pixel data as an address manual, the invented differential pixel data is output as data.

A configuration example of the address generation circuit 2 is shown in FIG. As shown, the two-dimensional address (x, y) of the image block
a two-dimensional address calculation circuit 21 that sequentially calculates and outputs
An external address register 22 that holds data on the forward side data bus as an external address EA,
It includes a selector 23 which selects the output of the dimensional address calculation circuit 21 or the external address register 22 and inputs an address to the A-board RAMI and the quantization table ROM 12.

This conventional image quantization circuit has a structure that reduces the number of terminals and makes the circuit more general-purpose.In addition to the quantization table ROM 12, an external expansion RAM is connected to terminals 10 and 11. It is also possible. in this case,
When connecting the quantization table ROM 12, the output from the external address register 22 can be selected, and when connecting the external expansion RAM, the output from the two-dimensional address generation circuit 21 can be selected using the selector 23 to manually input the address.
can.

The operation of this conventional circuit will be explained below. First, an overview of quantization of pixel blocks will be explained. As the pixel block, for example, an 8×8 pixel block as shown in FIG. 8 can be used, and this is assumed to be digitized with quantization characteristics as shown in FIG. In Figure 9, the horizontal axis is the differential pixel data before quantization, the vertical axis is the differential pixel data after quantization, and the two-dimensional address (x ry
) pixel data P (x, y) is the quantized value T (x, y)
This shows how it is quantized.

Difference pixels are calculated in advance for each of the 8×8 (=64) pixels in FIG. 8, and the difference data is converted into a code of a predetermined word length using the quantization characteristics shown in FIG. The advantage of this differential quantization processing is that compared to sending the data of a certain pixel block as-is to the transmission line and reproducing it on the receiving side, the amount of information to be transmitted is smaller by the difference and digitization.
It has a band compression effect.

The quantization timing when the conventional image quantization circuit shown in FIG. 5 performs quantization processing on this nxn pixel is shown in the time chart of FIG. 7.

It is assumed that differential pixel data is currently stored in the two-bottom RAM1. The A boat address generation circuit 2 uses a two-dimensional address (x.

y) is generated in the two-dimensional address calculation circuit 21, and by selecting this address (x, y) with the selector 23, 2
Pixel data P (x, y) is read from the A boat data output Dta side of the boat RAMI and set in the external address register 22.

In the next clock cycle, the pixel data P (x) held in this external address register 22.

y) with the selector 23 and the quantization table ROM1
The external quantization table ROM 12 is accessed using the external extension address EA for 2. As a result, pixel data P (x,
quantized pixel data T (x, y) corresponding to y) is read out as external data ED. This arsenalized pixel data T (x, y) is transferred to the 2-point RAM 1 via the B-side bus 5.
B boat address generation circuit 3 generates 2
It is stored at the storage address (f2.m) of point RAM1.

The above processing is for all pixels in the pixel block.

That is, by repeating nXn times, a quantized pixel block is generated in the 2-bot RAMI.

[Problems to be Solved by the Invention] In a conventional quantization circuit, when quantizing one pixel data, it takes one clock cycle to access the pixel data to be quantized to the two-bottom RAM, and the read pixel 1 to access the external quantization table ROM with data.
Each clock cycle requires a separate and independent clock cycle. Therefore, in order to quantize an nXn pixel block, at least twice as many clock cycles as the nXn clock cycles are required, and the processing time increases if the pixel block to be quantized is large or the number of blocks is large. There is a problem.

In addition, during quantization processing, pixel data is directly used as an address for the external quantization ROM, so there is a problem that it is difficult to allocate memory when connecting other external expansion memory to the external expansion port. If left as is, the number of address lines in the external quantization ROM increases, necessitating a large-capacity ROM, and increasing the size of the circuit.

Therefore, an object of the present invention is to realize high-speed quantization processing and to facilitate allocation of memory addresses to external expansion ports.

[Means to solve division problems] FIG. 1 is a diagram explaining the principle of the present invention.

In order to solve the above-mentioned problems, the present invention includes an internal RAM 31 for storing image data and an external quantization table memory 32, and stores the pre-quantized image data read from the internal RAM 31 as an address in the external quantization table. In an image quantization circuit that reads quantized image data from the memory 32 and stores it in the internal RAM 31, an external address register 33 holds the pre-quantized image data from the internal RAM 31 and provides it as an address to the external quantization table memory 32. There is provided an image quantization circuit characterized by comprising: and a selector 34 that inputs pre-quantized image data to the external address register 33 while fixing the upper bits of the external address register 33.

[Operation] The image data before quantization is read from the internal RAM 31 and is temporarily held in the external address register 33. In the next clock cycle, the quantization table memory 32 is accessed using the image data held in the external address register 33, and at the same time, the address is updated and accessed to the internal RAM 31 to read the image data. This allows read access to the internal RAM 31 and the quantization table memory 32 to be performed simultaneously in the same clock cycle, thereby speeding up the quantization process.

Furthermore, by controlling the selector 34, the upper bits of the external address register 33 can be fixed, and only the word length of the image data to be quantized can be written to the external address register 33. This allows memory allocation to the external expansion board. It's easy to do.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 2 shows an image quantization circuit as an embodiment of the present invention. In the figure, there is a 2-bot RAMI.

A boat address generation circuit 2, B boat address generation circuit 3, A picture data bus 4, B picture data bus 5, buffer circuit 9, external expansion terminal l0111, quantization table RO
M12 and the like have the same functions as those explained in the conventional example shown in FIG.

The difference is that the pixel data on the claw side data bus 4 is input to the external address register 6 through one input end of the selector 7, and the address is transferred from this external address register 6 to the quantization table ROM 12 via the selector 8. It is now output. The output from the A port address generation circuit 2 is led to the other input of the selector 8. Further, each output bit of the external address register 6 is led to the other input side of the selector 7.

The configuration of the selector 7 is such that the circuits shown in FIG. AND circuit 72 receives selection signal 5ELn
The terminal to which is input is an inverted input. In this circuit, when the selection signal 5ELn is -1'', the bit signals from the eight data buses are selected, and when the selection signal 5ELn is 0'', the bit signals from the external address register 6 are selected. Therefore n
It is possible to fix the contents of the upper bits of the external address register 6 by setting only the selection signal corresponding to the upper bits of the bit signals to "0"'.

The operation of the example circuit will be described below with reference to FIG. FIG. 4 is a time chart explaining the quantization timing of the embodiment circuit.

First, an initial value is set in the external address register 6 using the A-picture data bus 4 in consideration of external memory allocation. Then, by controlling the selection signals SEL, ~5ELn to the selector 7, the upper bit part of the external address register 6 is circulated and fixed via the selector 7, and only the word length of the pixel data to be quantized is set to the external address. Eight pieces of pixel data are written into the register 6 from the data bus 4. That is, in this case, a value is set such that the upper bit becomes "O" as the initial value, and the selection signal SEL corresponding to the upper bit is set to "0".

As explained in the above-mentioned conventional example, the 2-bot RAMI independently allocates areas for pixel blocks to be quantized and areas for quantized pixel blocks, and as shown in the time chart of FIG. Reading, writing and reading are performed simultaneously.

That is, in the first clock cycle, the A-boat address generation circuit 2 generates an address (x, y'), reads the pixel data P (x v y ) from the 2-baud RAMI, and transfers it to the external address via the selector 7. Interpret into register 6.

In the next clock cycle, this pixel data P(x,y)
External quantization table 1 using as external address EA
Pixel data T quantized by accessing 10M12
Read out (x, y). At the same time, the A-vote address generation circuit 2 generates the next address (x+1.y), accesses the 2-vote RAM 1, and holds the read pixel data P (x+1, y) in the external address register 6. .

Furthermore, in the next clock cycle, the quantization table ROM1
The quantized pixel data T (x, y) read from 2 is sent to the 2 port I-1/ designated by the B boat address generation circuit 3.
Write 9 into the address (12, m) of ~M1. At the same time, pixel data P (x+L
, y) to access the start table ROM 12. As a result, the pixel data at the (x, y) coordinates in the two-board RAM 1 is converted into counterfeit pixel data at the (Q, m) coordinates.

According to the above processing, the pixel data to be quantized is
Since the process of accessing port RAM 1 and the process of accessing the external π invention table 110M+2 using the read pixel data can be executed simultaneously in the same one clock cycle, the muntinization process It becomes possible to reduce the speed of

[Fuka Prefecture, published in November] According to the present invention, in image quantization processing, quantization is performed with the minimum number of clock cycles by separately installing the address register for the external atomization table ROM in Iγ. Therefore, it becomes possible to quantize a large amount of differential pixel data at high speed.

Further, the upper bits of unused addresses can be fixed so that the external expansion memory can be used effectively, and the external quantization table ROM can be configured with the minimum necessary memory capacity. Note that the fixed upper bits can be configured to be decoded externally to enable the memory.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention; FIG. 2 is a block diagram showing an image quantization circuit as an embodiment of the present invention; FIG. 3 is a diagram showing an example of the configuration of a selector in the embodiment circuit; Fig. 4 is a time chart showing the quantization timing of the embodiment circuit, Fig. 5 is a block diagram showing a conventional example of an image quantization circuit, Fig. 6 is a diagram showing a configuration example of an A boat address generation circuit, Fig. 7 8 is a time chart showing the quantization timing of the conventional circuit; FIG. 8 is a diagram showing the configuration of an 8×8 pixel block; and FIG. 9 is a diagram explaining the quantization characteristics. In the figure, l...2-bottom RAM 2.3...address generation circuit 4.5...data bus 6.22...external address register 7.8.23...selector 9...・Buffer circuit 10.11...External expansion terminal 12...Quantization table ROM 21. ・Two-dimensional address calculation circuit 71.72...AND circuit 73...OR circuit misfire March 1 Tei thread 3 Figure 1 of the principle blue moon map

Claims (1)

[Claims] The internal RAM (31) includes an internal RAM (31) for storing image data and an external quantization table memory (32).
In an image quantization circuit that reads out quantized image data from the external quantization table memory (32) using the pre-quantized image data read out from the internal RAN (31) as an address, the internal RAN ( an external address register (33) that holds pre-quantization image data from (31) and supplies it as an address to the external quantization table memory (32); An image quantization circuit comprising: a selector (34) for inputting pre-quantization image data to the external address register (33).