KR100228554B1 - Memory controlling method in video encoder - Google Patents

Abstract

The present invention relates to a memory control method in a video encoder that improves the efficiency of using the frame memory by controlling the respective access time when accessing the memory through the frame memory module in each module in the MPEG-2 TV-class video encoder In addition, by dividing the access time of the DRAM controlled by the FMM so that each module can access the DRAM in an optimal state, there is an advantage of improving the access speed and reducing the capacity of the buffer used in the submodule. .

Description

Memory Control Method in Video Encoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control method in a video encoder. Each module in umpec-2 (hereinafter referred to as MPEG-2) TV class video encoder controls each access time when a memory is accessed through a frame memory module. The present invention relates to a memory control method in a video encoder that improves the efficiency of using frame memory.

In general, currently used MPEG-2 based TV-grade video encoder stores input image data, encoded image data, and encoded bit string data by sequentially sequentially mapping the plurality of frame memories.

As a result, a large number of memories are used, and as the area occupied by hardware increases, a waste of each memory (particularly using a DRAM) may be generated.

In addition, there is a problem in that the access data width of the DRAM memory is increased because the time required for accessing stored data or writing new data is lengthened according to an inefficient storage method of data.

In the present invention, in consideration of the conventional problems as described above, when each sub-module in the frame memory module accesses the DRAM, the access timing is controlled to store data in the DRAM in the most optimal state, The purpose is to reduce the buffer capacity and DRAM memory used by submodules.

1 is a schematic block diagram of a video encoder to which the present invention is applied.

2 is a schematic block diagram of a frame memory module in a video encoder.

3 is a timing diagram illustrating memory access time for each submodule according to the present invention.

4 is a timing diagram showing a fast page mode timing of a DRAM according to the present invention.

* Explanation of symbols for main parts of the drawings

1: Video input module 2: Frame memory module

3: coder module 4: variable length coding module

5: motion estimation module 6: memory module

21: video input submodule 22: coder submodule

23: motion estimation submodule 24: variable length encoding submodule

25: DRAM Control Sequencer 215,233: MUX

211 ~ 214, 221, 231, 232, 241, 242: buffer

In order to achieve the above object, the present invention provides a memory control method in a video encoder for controlling memory access through a frame memory module (FMM), wherein each submodule in the frame memory module is shared. Dividing an access time (clock count) of a DRAM memory having a single address structure for each submodule and assigning each of them; Create a timing schedule for each sub-module to access memory exclusively according to the input / output state and change state of the data in the allocated time; The memory may be accessed only during the allotted time under the control of the FMM incorporating the created timing schedule.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In general, in order to design an MPEG-2 based TV-grade video encoder as a digital circuit, a frame memory module (hereinafter referred to as FMM) for temporarily storing input video, intermediate coded video, and coded bit string data is referred to. As shown in FIG. 1, a schematic block of a universal video encoder including the same may be modified by converting color data of a field unit input from a camera (not shown) into frame data. An image input module (IP) 1 for outputting; A FMM (2) for controlling its operation when storing and reading data generated by each module in the encoder in an external memory; A coder module 3 for outputting intermediate encoded data; A variable length coding module (VLC) 4 for generating a coded bit stream; A motion estimation module (ME / MC) 5 for performing motion estimation and motion compensation; It includes a memory module (6) for storing data input and output from the FMM (2).

At this time, the memory module 6 has a single address memory structure using the FMM 2. That is, instead of using a plurality of memories corresponding to each of the modules 2, 3, 4, and 5, one shared memory (hereinafter referred to as DRAM) is used, and access control thereof is performed using the FMM 2. Through.

Referring to the schematic operation of the video encoder configured as described above, when color (RGB) data in units of frames is input through the image input module 1, the coder module 3 outputs the intermediate coded data. This data is stored in the DRAM 6 by the FMM 2.

The data stored in the DRAM 6 is input to the motion estimation module 5 to output the data of the motion estimation and compensation state through the past frame data and the current data to the coder module 3.

The coder module 3 outputs the intermediate coded data using the data output from the motion estimation module 5, and the data is input to the variable length coding module 4 and output as a variable length coded bit stream. .

Subsequently, the coded bit string is again input to the FMM 2 and then output to the outside of the video encoder (not shown in the figure) by 8 bits.

2 is a detailed block diagram of the FMM to which the present invention is applied and includes: an image input submodule 21 serving as an auxiliary memory when data is input / output between the image input module 1 and the DRAM 6; A coder submodule 22 serving as an auxiliary memory when inputting / outputting data between the coder module 3 and the DRAM 6; A motion estimation submodule 23 serving as an auxiliary memory when inputting / outputting data between the motion estimation module 5 and the DRAM 6; A variable length encoding submodule 24 serving as an auxiliary memory when inputting / outputting data between the variable length encoding module 4 and the DRAM 6; And a DRAM control sequencer 25 for controlling data and generating an address of the DRAM 6 when data input / output of each of the sub-modules 21 to 24 and the DRAM 6 is performed.

In this case, the input image submodule 21 includes buffers 211 and 212 for storing luminance signals and chromaticity signals respectively output from the input image module 1; Buffers 213 and 214 for storing the macro block luminance signal and the macro block chromaticity signal output from the DRAM 6, respectively; And a mux 215 for selectively outputting the outputs of the buffers 213 and 214.

The coder submodule 22 includes a buffer 221 for storing coded data output from the coder module 3.

The motion estimation submodule 23 includes buffers 231 and 232 for dividing and storing past frame data output from the DRAM 6 into luminance and chroma signals, respectively; A mux 233 for selectively outputting the output of each of the buffers (231, 232).

The variable length encoding submodule 24 includes a buffer 241 for storing encoded bit string data (vstream) output from the variable length encoding module 4; A buffer 242 for storing encoded bit string data (cstream) output from the DRAM 6 is included.

Looking at the operation of the FMM (2) configured as described above, each of the sub-modules 21 to 24 stores the data output from each of the external modules (1, 3 to 5) connected to the sub-module ( The data generated by the submodule to which the DRAM 6 access time is allocated among the 21 to 24 is written to or read from the DRAM 6.

The reason for configuring the sub-modules serving as buffers for the respective modules in the FMM 2 is various types of data stored in the DRAM 6 or read from the DRAM 6. This is because the data generated or required in these fields may occur simultaneously.

Therefore, since these simultaneous data cannot be processed at one time by the DRAM 6, the data are temporarily stored in the buffers and then stored in the DRAM 6.

As described above, in order for the FMM 2 to control the connection of the external DRAM 6 and to appropriately process that the generation and request of various data are randomly generated in each external module of the FMM 2, the FMM 2 When designing the internal buffer, design using RAM (S-RAM, etc.) that has faster access speed than DRAM (6).

The main aspect of the video encoder operating through the above configuration and the data storage method of the DRAM through the above configuration is to reduce the capacity of the S-RAM used as the buffer as much as possible, and in consideration of the access timing schedule of the related DRAM, the external module Is to handle various service requests for data in real time.

Accordingly, the present invention provides a DRAM control method for controlling the access time of each module accessing the DRAM to use the shared DRAM 6 as efficiently as possible.

The control method of the present invention will be described below.

Generally, a TV-class video encoder generates a pick signal to indicate the start of an image. When the macro start block clock (hereinafter referred to as MBCK) is generated according to the clock generation, the macroblock address generated by this clock is -3. to be. Where -3 means the third point at which the first macroblock is actually processed.

At this time, the hardware of the FMM operates when the macroblock address by the MBCK clock is -2. When the macroblock address becomes -2, the motion estimation submodule 23 configured inside the FMM 2 is an external motion estimation module. Start operation with (5).

In addition, the motion estimation submodule 23 receives a motion vector from an external motion estimation module 5 at the time when the macroblock address becomes 2, and then interprets the motion vector and stores as much as the value indicated by the transmitted motion vector. The color signal CbCr necessary for motion compensation is outputted to the external motion estimation module 5 by shifting the address (which is a DRAM in the present invention).

When the macroblock address is 3 by the MBCK clock, the coder module 2 outputs the encoded luminance signal and the color signal to the FMM 2.

Accordingly, the coder submodel 22 configured in the FMM 2 stores the output data in the DRAM at the time when the use of the DRAM 6 is approved.

In addition, when the macroblock address becomes 4 by the MBCK clock, the variable length encoding module 4 performs variable length encoding to output data having a variable rate to the FMM 2, and the data is a variable length encoding sub in the FMM. The data is stored in the module 24 at the time the next DRAM 6 usage is accepted.

As described above, referring to FIG. 3, a time point at which each submodule allocates an access time of the DRAM 6 and processes data is described as follows.

The DRAM control sequencer 25 configured inside the FMM 2 is a time when each submodule accesses the DRAM 6 in synchronization with a clock (SCK2: 27 MHz) multiplied by a double of a system clock (using SCK: 13.5 MHz). At this time, the clock (SCK2) has a number of 660 clocks, and divides the number of clocks to allow each module to use the DRAM (6).

FIG. 3 is a timing diagram showing the time when each server module accesses the DRAM 6. FIG. 3 (a) shows the timing at which the motion estimation submodule 24 will access the DRAM, and FIG. FIG. 3 (c) shows the timing at which the image input server module 21 will access the DRAM, and FIG. 3 (d) shows the coder submodule. Denoted at 22 is the timing of accessing the DRAM, and FIG. 3E shows the timing at which the refresh mode performed at the DRAM 6 is operated.

According to the clock as described above, each submodule uses the DRAM 6 at a predetermined time (a part where the clock becomes a high value) for 660 clocks SCK2 when the macro block clock notifies the start. ) Access times are summarized in Table 1 below.

In this case, the number written between start and end in Table 1 means the 'SCK2' clock sequence between 0 and 659, and the start-end means the number of clocks from the end to the start. These are the times of using memory (DRAM).

Summarizing the above table, the number of clocks required by the motion estimation submodule 23 is 204 clocks for 6 Y macroblocks ((1ra (random access) + 31fps (fast page) = 34clks)). 6) is required, and 50 clocks ((5ra + 10fp) x 2) are required to output the encoded color signal CbCr.

The number of clocks required by the image input submodule 21 requires 92 clocks (4ra + 78fps + 2SCK2) to store input data, and the number of clocks required for outputting data is Y data. In the case of a clock (4ra + 28fp) and an encoded color signal, 60 clocks (8ra + 36fp) are required.

The number of clocks required by the coder submodule 22 requires 34 clocks (1ra + 31fps) to store Y, and 20 clocks (2ra + 14fps) for the encoded color signal.

The number of clocks required by the variable length encoding submodule 24 requires 10 clocks to output the data of the constant rate, and up to 146 clocks (2ra + 140fps) are required to receive the data of the variable rate as an input. need.

Finally, four clocks are required for the refresh operation of the DRAM 6.

4 is a timing diagram related to the fast page mode of a DRAM referred to in the present invention, in which the fast page mode changes only the column address on the same row address in succession, thereby accessing the DRAM while the row address and the column address are sequentially changed. It's a fast way.

(A) of FIG. 4 shows the clock SCK2, (b) of FIG. 4 is an enable signal for operating the fast page mode, and (c) of FIG. 4 shows the ras signal RAS and FIG. d) represents a cas signal CAS.

As shown in the timing diagram, it can be seen that the cas signal (d) of FIG. 4 changes several times when the las signal (c) of FIG. 4 remains enabled.

Therefore, in the present invention, in order to provide the DRAM access request generated at the same time as fast as possible while maintaining the optimal buffer capacity, the method of storing data in the DRAM 6 is performed using the same method as the fast page mode. Control it to save, and read it in fast page mode when you read it.

For reference, the time division described in the present invention is a division value most optimally used in a memory to which the present invention is applied, and this clock division value can be changed as much as hardware changes.

As described in detail above, the present invention divides the access time of the DRAM controlled by the FMM so that each module can access the DRAM in an optimal state, thereby improving the access speed, and used in the submodule. The advantage is to reduce the capacity of the buffer.

In addition, a preferred embodiment of the present invention is disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (7)

A memory control method of a video encoder for controlling memory access through a frame memory module (FMM), wherein the access time (number of clocks) of a single memory shared by each submodule in the frame memory module is divided for each submodule. Assign each; Create a timing schedule for each sub-module to access memory exclusively according to the input / output state and change state of the data in the allocated time; And allowing the memory to be accessed only at the allotted time under the control of the FMM incorporating the created timing schedule. The method of claim 1, wherein each of the submodules reads or writes data in a fast page mode when reading or writing data in a memory accessed at an allotted time. 2. The apparatus of claim 1, wherein the number of clocks allocated to an image input submodule among the submodules in the frame memory module is configured to allocate 92 clocks to store input data in the memory; Allocate 40 clocks for outputting luminance data of blocks to be processed; Allocating 60 clocks for outputting the color data of the block to be processed; A method for controlling memory in a video encoder, characterized by allocating a total of 192 clocks. 2. The method of claim 1, wherein the number of clocks allocated to coder submodules among the submodules in the frame memory module is configured to allocate 34 clocks to store an input luminance signal in the memory; Allocating 20 clocks to store the encoded color signal in a memory; A method of controlling memory in a video encoder characterized by allocating 54 clocks in total. The number of clocks allocated to the motion estimation submodules among the submodules in the frame memory module is configured to allocate 204 clocks for six luminance signal macroblocks; Allocating 50 clocks for output of the encoded color signal; A method of controlling memory in a video encoder characterized by allocating a total of 254 clocks. 2. The method of claim 1, wherein the number of clocks allocated to the variable-length encoding submodules among the submodules in the frame memory module allocates 10 clocks for outputting data of equality; Allocating 146 clocks to receive data; A method of controlling memory in a video encoder characterized by allocating a total of 156 clocks. The method of claim 1, wherein the timing schedule is the same as the timing schedule of the following table. TABLE 1a

TABLE 1b

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