JPH03174743A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03174743A JPH03174743A JP24652290A JP24652290A JPH03174743A JP H03174743 A JPH03174743 A JP H03174743A JP 24652290 A JP24652290 A JP 24652290A JP 24652290 A JP24652290 A JP 24652290A JP H03174743 A JPH03174743 A JP H03174743A
- Authority
- JP
- Japan
- Prior art keywords
- metal fine
- thermosetting resin
- semiconductor device
- fine wires
- short
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000011347 resin Substances 0.000 claims abstract description 21
- 229920005989 resin Polymers 0.000 claims abstract description 21
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000000465 moulding Methods 0.000 claims abstract description 6
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体装置の組立構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an assembly structure of a semiconductor device.
ＩＣチップをプラスチックパッケージに組立てる場合の
一般的構造は第３図のように、タブ２上にＩＣチップｌ
をエポキシ系接着剤などで固定し、パッド電極４とリー
ド電極３を金属細線５で接続し、しかる後に樹脂モール
ドをするものであった。The general structure when assembling an IC chip into a plastic package is as shown in Figure 3, where the IC chip is placed on tab 2.
The pad electrode 4 and the lead electrode 3 were connected with a thin metal wire 5, and then resin molded.
〔発明が解決しようとする課題１
最近ＩＣパッケージの多ビン化が進み、２００ビン以上
のものが増えているが、この場合問題になるのはリード
電極３のピッチを０．２ｍｍ程度以下に加工する事は技
術的に困難であることから、リード電極３をパッド電極
４に十分近づけられない事である。この結果金属細線５
の長さが従来２．５〜３．０ｍｍだったのが、３ｍｍを
越えるようになり更に５ｍｍ以上のものと現われつつあ
る。このため金属細線のたるみが生してタブ２とショー
トしたり、樹脂モールデインク時に金属細線同士ショー
トする問題点を有する。[Problem to be solved by the invention 1 Recently, the number of IC packages has been increasing, and the number of IC packages with more than 200 bins is increasing.In this case, the problem is that the pitch of the lead electrodes 3 is processed to be about 0.2 mm or less. Since it is technically difficult to do so, the lead electrode 3 cannot be brought sufficiently close to the pad electrode 4. As a result, metal thin wire 5
Previously, the length was 2.5 to 3.0 mm, but it has now exceeded 3 mm, and even 5 mm or more is appearing. For this reason, there is a problem in that the thin metal wires become slack and short-circuit with the tab 2, or the thin metal wires short-circuit with each other during resin mold inking.
本発明は上記課題を解決すべくなされたちのて、その目
的とするところは、かかる金属細線のタブショートや金
属細線同士のショートを防止した半導体装置を提供する
ところにある。The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a semiconductor device in which tab short-circuits of thin metal wires and short-circuits between thin metal wires are prevented.
［課題を解決するための手段］
本発明の半導体装置は、リードフレームの裏面と絶縁性
裏打板を貼付し、ＩＣチップと金属細線を覆うように熱
硬化性樹脂でコーティングした事を特徴とする。[Means for Solving the Problems] The semiconductor device of the present invention is characterized in that an insulating backing plate is attached to the back side of a lead frame, and a thermosetting resin is coated to cover the IC chip and the thin metal wire. .
また、滴下法等によりコーティングする前記熱硬化性樹
脂に対して流れ止めを有することを特徴とする。Further, it is characterized in that it has a flow stopper for the thermosetting resin coated by a dripping method or the like.
［実 施 例１
第１図は本発明の実施例の模式図である。なお前述の従
来例と同一または相当部分には同し符号を付しである。[Example 1 FIG. 1 is a schematic diagram of an example of the present invention. Note that the same or equivalent parts as in the conventional example described above are given the same reference numerals.
本発明の構造を得るためにはリードフレームの裏面には
絶縁性の裏打板を絶縁性の接着剤などを用いて貼付する
。これはワイヤボンディング直後の工程あるいはワイヤ
ボンディングよりも前の工程で貼付されていなければな
らない。ワイヤボンディング後にＩＣチップ１と金属線
ｖ８５の上からこれらを覆うように熱硬化性樹脂で滴下
法等によりコーティングする。この時、裏打板の上に熱
硬化性樹脂がたまり第１図のようなコーティング形状が
得られる。このあと−旦樹脂を硬化させてから、樹脂モ
ールディングを行ない、端子表面処理、マーキング、お
よびリード成形を行って半導体装置を完成させれば良い
。In order to obtain the structure of the present invention, an insulating backing plate is attached to the back surface of the lead frame using an insulating adhesive or the like. This must be applied in a process immediately after wire bonding or in a process before wire bonding. After wire bonding, the IC chip 1 and the metal wire v85 are coated with a thermosetting resin by a dripping method or the like so as to cover them. At this time, the thermosetting resin accumulates on the backing plate, resulting in a coating shape as shown in FIG. Thereafter, after the resin is cured, resin molding is performed, terminal surface treatment, marking, and lead molding are performed to complete the semiconductor device.
この様に一旦ＩＣチップｌと金属細線５とを一次到止し
てから樹脂モールディングを行うので、金属細線のタブ
ショートや、樹脂モールディング時の金属細線同士のシ
ョートが防止できる。In this way, since resin molding is performed after the IC chip 1 and the metal wire 5 are first brought together, tab short-circuits of the metal wires and short-circuits between the metal wires during resin molding can be prevented.
第１図の構造の場合、滴下法等によりコーティングした
熱硬化性樹脂７が、リード電極３側で不定形に広がりす
ぎる場合が有る。これを防止するためには、第２図の如
く、流れ止め８を貼付し、広がり具合を形状を管理する
のが有効である。ちちろん、流れ止めとこれを固定する
接着剤は共に絶縁性の材料でなくてはならない。In the case of the structure shown in FIG. 1, the thermosetting resin 7 coated by the dropping method or the like may spread too much in an irregular shape on the lead electrode 3 side. In order to prevent this, it is effective to attach a flow stopper 8 as shown in FIG. 2 and control the shape of the spread. Of course, both the stopper and the adhesive that holds it in place must be made of insulating material.
［発明の効果］
以上述べた様に本発明によれば、リードフレームの裏面
に絶縁性の裏打板を貼付し、ＩＣチップと金属細線を覆
うように熱硬化性樹脂でコーティングしたことにより、
３〜５ｍｍの長い金属細線のタブショートや金属細線同
士のショートの問題を解決でき、２００ビンを越える半
導体装置の組立を容易ならしめるという効果を有する。[Effects of the Invention] As described above, according to the present invention, an insulating backing plate is attached to the back surface of the lead frame, and the IC chip and the thin metal wire are coated with a thermosetting resin.
This has the effect of solving the problems of tab shorts between long thin metal wires of 3 to 5 mm and shorts between thin metal wires, and facilitating the assembly of semiconductor devices with more than 200 bins.
また、絶縁性裏打板およびリード電極上に、流れ止めを
設けたので、熱硬化性樹脂が流れ止めを赳えて不必要に
流れてしまうことがないという効果を有する。Further, since the flow stopper is provided on the insulating backing plate and the lead electrode, there is an effect that the thermosetting resin does not flow unnecessarily due to the flow stopper.
第１図は本発明の半導体装置の一実施例を示す模式図。
第２図は本発明の半導体装置の他の実施例を示す模式図
。
第３図は従来の半導体装置の模式図である。
ｌ・・・ＩＣチップ
２・・・タブ
・リード電極
・パッド電極
・金属細線
・絶縁性裏打板
・熱硬化性樹脂
・流れ止めFIG. 1 is a schematic diagram showing an embodiment of the semiconductor device of the present invention. FIG. 2 is a schematic diagram showing another embodiment of the semiconductor device of the present invention. FIG. 3 is a schematic diagram of a conventional semiconductor device. l...IC chip 2...Tab, lead electrode, pad electrode, thin metal wire, insulating backing plate, thermosetting resin, flow stopper
Claims (2)
ように樹脂モールドをして組立てる半導体装置において
、前記リードフレームの裏面には絶縁材からなる裏打板
を貼付し、前記ＩＣチップと前記金属細線を覆うように
熱硬化性樹脂で滴下法等によりコーティングした事を特
徴とする半導体装置。(1) In a semiconductor device assembled by resin molding to cover an IC chip, a lead frame, and a thin metal wire, a backing plate made of an insulating material is attached to the back surface of the lead frame, and the IC chip and the thin metal wire A semiconductor device characterized by being coated with a thermosetting resin by a dripping method or the like so as to cover the semiconductor device.
脂に対して流れ止めを有する事を特徴とする請求項１記
載の半導体装置。(2) The semiconductor device according to claim 1, further comprising a flow stopper for the thermosetting resin coated by a dropping method or the like.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24116089 | 1989-09-18 | ||
| JP1-241160 | 1989-09-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03174743A true JPH03174743A (en) | 1991-07-29 |
Family
ID=17070153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24652290A Pending JPH03174743A (en) | 1989-09-18 | 1990-09-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03174743A (en) |
-
1990
- 1990-09-17 JP JP24652290A patent/JPH03174743A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5139969A (en) | Method of making resin molded semiconductor device | |
| JPH02278740A (en) | Packaging of semiconductor device | |
| JPH03174743A (en) | Semiconductor device | |
| TW324852B (en) | Improved fabricating method of semiconductor device | |
| JP3306981B2 (en) | Method for applying adhesive to lead frame for semiconductor device | |
| JPH0760881B2 (en) | Solder application method for semiconductor devices | |
| EP0736225A1 (en) | Method of attaching integrated circuit dies by rolling adhesives onto semiconductor wafers | |
| JPS57114263A (en) | Semiconductor device | |
| JPH04206553A (en) | Semiconductor device | |
| JPS6327029A (en) | Manufacture of resin-sealed semiconductor device | |
| JPS6344998Y2 (en) | ||
| JPH0379044A (en) | Resin-sealing of semiconductor element | |
| JPS61225891A (en) | Mounting of semiconductor | |
| JPH03104131A (en) | Semiconductor device | |
| JPS57148362A (en) | Semiconductor device | |
| JPS63177429A (en) | Sealing method for semiconductor component | |
| JPH01272124A (en) | Manufacture of semiconductor device | |
| JPS63310147A (en) | Manufacture of semiconductor device | |
| JPS61285730A (en) | Manufacture of semiconductor device and resin mold member used therefor | |
| JPS63215368A (en) | Solder feeding method | |
| JPH0722165B2 (en) | Method for manufacturing semiconductor device | |
| JPH0637123A (en) | Semiconductor device | |
| JPH0660146U (en) | Semiconductor chip resin sealing device | |
| JPH0327562A (en) | Semiconductor device | |
| JPS61271848A (en) | Manufacture of semiconductor package |