JPH03171979A - Signal processing circuit of solid-state image pickup device - Google Patents

Abstract

PURPOSE:To satisfactorily execute the image enhancement processing by selecting a detail signal generating means and an interpolating means to a characteristic in which even/odd number of the number of pieces of zero points of each digital filter coincide with each other. CONSTITUTION:In the case even/odd numbers of degrees (m), (n) of each digital filter of interpolation processing parts 13R, 13G and 13B and a detail signal generating part 11 do not coincide with each other, a group delay by the digital filter for an interpolation processing in the interpolation processing parts 13R, 13G and 13B, and a group delay by the digital filter for a differential processing for generating a detail signal in the detail signal generating part 11 are shifted from each other, and an image enhancement processing cannot be executed satisfactorily. Accordingly, by allowing the even/odd numbers of the degrees (m), (n) of each digital filter to coincide with each other, the group delay by the digital filter for the interpolation processing and the group delay by the digital filter for the differential processing for generating the detail signal are allowed to coincide with each other. In such a way, even if the detail signal is added to the signal whose interpolation processing is ended, the image enhancement processing can be executed satisfactorily.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Field of Application The present invention digitizes an imaging output signal from a solid-state image sensor for generating a video signal, and forms a detail signal for image enhancement processing by digital signal processing. Regarding the signal processing circuit of the solid-state imaging device, in particular, the solid-state image sensor for green image sensing, the solid-state image sensor for red image sensing, and blue image sensing are spatially spaced by 1/2 of the repetition pitch of each pixel. The present invention relates to a signal processing circuit of a solid-state imaging device that employs a so-called spatial pixel shifting method in which picture elements are arranged in a shifted manner in an imaging section.

B. Summary of the Invention The present invention provides a so-called spatial picture element in which a solid-state image sensor for green image sensing and a solid-state image sensor for red and blue images are spatially shifted by 172, which is the repetition pitch of each pixel. In a signal processing circuit of a solid-state imaging device, which digitizes the imaging output signal from each solid-state image sensor of an imaging unit that adopts the shifting method, and forms a detail signal for image enhancement processing by digital signal processing. , a green image imaging signal and a red image imaging signal are obtained by digitizing each imaging output signal read out from each of the solid-state image sensors at a sampling rate of fs by an analog-to-digital conversion means at a cross rate equal to the sampling rate fs. A detail signal with a clock rate of 2fs, which is twice the sampling rate}fs, is formed from a signal obtained by adding an equal amount of the signal, the blue image pickup signal, or the sum of both signals, and the digital output is applied to this detail signal. Image enhancement processing is performed by interpolating and adding signals at a clock rate of 2 fs using a digital filter, and the digital filter for generating the detail signal and for interpolation processing has a zero point at the frequency of fs and each digital filter has a zero point at the frequency of fs. Image enhancement processing at a clock rate of 2 fs can be performed satisfactorily by selecting a characteristic in which the number of zero points of the filter is even or odd.

C Conventional technology Charge coupled device (CCD)
In a solid-state imaging device that uses a solid-state image sensor with a discrete pixel structure as the imaging unit, such as those used in devices such as devices, the solid-state image sensor itself is a sampling system, so the solid-state image sensor shown in FIG. 17 is shaded. As shown, the imaging output signal from the solid-state image sensor is mixed with the aliasing signal from the spatial sampling frequency fs. Conventionally, by providing a birefringent optical low-pass filter in the imaging optical system and suppressing the high frequency side of the baseband component of the imaging signal, the Nyquist condition of the sampling system using the solid-state image sensor is satisfied, and the imaging output is This is to prevent signal aliasing to the baseband. In addition, color television camera devices include two-chip solid-state imaging devices that capture three primary color images using a solid-state image sensor for green image capture and a solid-state image sensor provided with color coding filters for red and blue pixels; Multi-plate solid-state imaging devices, such as a three-plate type, which capture images using individual solid-state image sensors, have been put into practical use.

Furthermore, as a method for improving the resolution of the multi-chip solid-state imaging device, a solid-state image sensor for green image sensing is
A so-called spatial pixel shifting method is known in which the solid-state image sensors for capturing red images and for capturing blue images are arranged offset by 2. By employing this spatial pixel shifting method, an analog output multi-plate solid-state imaging device can achieve high resolution that exceeds the limit of the number of pixels of a solid-state image sensor.

In addition, standardization of the so-called DI/D2 format is underway for commercial digital video recorders used at broadcasting stations, etc., and color television cameras are the digital interface for digital video-related equipment that conforms to these standards. It is also required for equipment. According to the standards for digital interfaces for digital video-related equipment mentioned above, the sampling rate is the sampling rate fs of the current solid-state image sensor.
It is set to about. Furthermore, in general, in order to improve image quality in television camera devices, etc., gamma correction processing is performed on the image output signal obtained by the image pickup unit, or a detail signal is formed from the image output signal to generate the original signal. Image enhancement processing is performed by adding and compositing the images. D. Intelligence that the invention seeks to solve By the way, as mentioned above, the solid-state image sensor for green image sensing, the solid-state image sensor for red image sensing, and blue image sensing are spatially separated by 1/2 of the repetition pitch of each pixel. In a solid-state imaging device equipped with an imaging section that adopts the so-called spatial pixel shifting method in which picture elements are arranged with a shift of There is a problem in that image quality is degraded due to aliasing components included in the signal, and there is also a problem in that image quality is degraded due to cross color interference when horizontal detail signals are mixed into the color subcarrier frequency domain. ．． Accordingly, the present invention provides a solid-state imaging device equipped with an imaging section that employs the so-called spatial pixel shifting method, in which a detail signal is formed by digital signal processing on an imaging output signal, and aliasing components and cross color interference contained in the detail signal are eliminated. It is an object of the present invention to enable image enhancement processing to be performed satisfactorily without deterioration of image quality due to.

E Means for Solving the Problems In order to achieve the above-mentioned object, the signal processing circuit of the solid-state imaging device according to the present invention uses a solid-state image sensor for green image sensing, a solid-state image sensor for red image sensing, and blue image sensing. Each image pickup output signal read out at a sampling rate of fs from each of the solid-state image sensors of the image pickup unit, which is arranged spatially shifted from the sensor by 1/2 of the repetition pitch of each pixel, is read out at a clock rate equal to the sampling rate fs. An analog-to-digital conversion means to digitize, a green image imaging signal and a red image imaging signal among each digital output signal of the analog-to-digital conversion means,
A horizontal detail signal with a clock rate of 2 fs, which is twice the sampling rate fs, is output from a signal obtained by adding an equal amount of the blue image imaging signal or the sum of both signals through a digital filter having a zero point at the frequency of Is. a detail signal generating means; an interpolating means for interpolating each digital output signal of the analog-to-digital converting means to a clock rate of 2 fs using a digital filter having a zero point at the fs frequency; and an addition means for adding to the output signal of the interpolation means, and the detail signal generation means and the interpolation means are characterized in that the characteristics are selected such that an even or odd number of zero points of each of the digital filters is determined. be. F action In the signal processing circuit of the solid-state imaging device according to the present invention, each imaging output signal read out at a sampling rate of fs from each solid-state image sensor of the imaging unit employing the spatial pixel shifting method is converted into the above-mentioned image pickup output signal by the analog-to-digital conversion means. For the digital output signal digitized at a clock rate equal to the sampling rate fs, the interpolation means
Image enhancement processing is performed by forming a fs rate signal, generating a 2 fs rate horizontal detail signal by the detail signal generating means, and adding and combining these signals with the adding means.

The interpolation means converts each digital output signal of the analog-to-digital conversion means into a 2f signal using a digital filter.
Interpolate to the clothocrate of s.

Further, the detail signal generating means includes the analog
A clock rate of 2fs, which is twice the sampling rate fs, is obtained from a signal obtained by adding equal amounts of a green image imaging signal, a red image imaging signal, a blue image imaging signal, or a composite signal of both signals among the digital output signals of the digital conversion means. The horizontal detail signal is shaped and outputted through a digital filter having a zero point at the frequency fs.

The detail signal generating means and the interpolating means exhibit group delay characteristics that are mutually exclusive by selecting characteristics such that the number of zero points of each digital filter is even or odd.

G. Embodiment Hereinafter, one embodiment of a signal processing circuit for a solid-state imaging device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows imaging light L. which is incident from an imaging lens (1) via an optical low-pass filter (2). is separated into the three primary color light components of R, G, and B by a color separation prism (3),
Three primary color images of the subject are captured by three CCD image sensors (
4R), (4G). (4B) shows a color television camera device constructed by applying the present invention to a three-plate solid-state imaging device that captures images.

In this embodiment, the three CCD image sensors (4R) (4G) . (4B) adopts the spatial pixel shifting method, and as shown in FIG. 2, red? A CCD image sensor (4R) for capturing an image and a CCD image sensor (4B) for capturing a blue image are arranged so as to be shifted by 1/2 of the spatial sampling period τ3 of the picture element. And the above three CCD image sensors (4R). (
4G) and (4B) are driven by a CCD drive circuit (not shown), and the imaging charge of each pixel is adjusted to the color subcarrier frequency '
, , or 4 fsc sampling frequency fs
It is read out by the readout cloth.

Three CCD image sensors (JR), (4G) that adopt the above spatial pixel shifting method. (4B) is the CC for the above green image capturing for the three primary color images of the subject image.
D image sensor (4G) and each CCD image sensor (4R) for capturing the red image and blue image.
(4B) and τ. Spatial sampling is performed at a position shifted by /2. As a result, the above CCD image sensor (4R
) , (4G) , (4B) The respective imaging output signals S ll * H S e ■ So have their spectral components as shown in FIG. Output signal S. The above sampling frequency fs and the red image output signal S from each of the above CCD image sensors (4R) and (4B)
11* and blue imaging output signal SN. The above-mentioned sampling frequencies fs and frequency are in opposite phase to each other. Then, each of the CCD image sensors (4R)
．． (4G), each imaging output signal Sj1m+36m read out from (4B). S llm are Banfa amplifiers (5R) (5G), respectively. Analog to digital (8/D) converter (6R) via (5B)
, (6G) . (6B). Each of these A
The /D converters (6R), (6G), and (6B) receive each of the above imaging output signals S*11+S Gl1+S
Croncrate equal to the sampling rate of 8", that is, each CCD image sensor (4R), (4
G), Same as the readout clock of (4B) 4', c
A clock with a clock frequency fs is provided by a timing generator (not shown). And each of the above A/
D conversion H (6R) (6G), (6B) is the image pickup output signal S. ll * 1 S G 11 1S
．． are digitized as they are at the clock rate fs of 4fsc, and each of the above image pickup output signals S. ? ah
Each color data D, t. , D+DIm is the precept. The above A/D converter (6R), (6G). (6B
) Each color data obtained by DI111+ DG+1
+Dso is supplied to the signal processing section (7). As shown in FIG. 4, the signal processing section (7) has red data DI1. and the above A/D converter (6G
) obtained by green data DG. a detail signal generator (11) to which is supplied the A/D converter (6R);
, (6G), (6B), three primary color data D+1m+Dc*+Dm. is the delay circuit (1211)
, (12G) . An interpolation processing unit (13R) supplied via (12B). (13G) , (13B
), and these interpolation processing units (13R), (13G) .
Three primary color data D that has been interpolated from (13B). ■DB
■D. ．． ．． and an adder (14R) to which the detail signal D 11mm is supplied from the detail signal generator (11).
), (14G), (14B) and gamma correction processing circuits (1511), (15G) to which the addition outputs of these adders (14R), (14G), (14B) are supplied.
), (15B). In this signal processing section (7), the interpolation processing section (13
R), (13G), (13B) are the above A/D
Converter (6R), (6G). The three primary color data Dj1. of clock rate fs of 4f, , supplied from (6B) , D Gll+ D lm, the above clothocrate fs is doubled, that is, 8
Croncrate 2fs three primary color data D ll of f,,
It forms il'll D G**+ D @**.

The above interpolation processing section (13R). (13G) , (1
3B) is the three primary color data D 1l11 at the above fs rate.
For 1 0 Gll, D @*, the clock rate 2f is twice the clock rate fs, that is, 8 fsc.
H(z)+r* = (Z-'+1)"...
The filter may include a digital filter that has at least one zero point in fs indicated by (3) and provides a filter characteristic H(Z)+rm as shown in FIG. The interpolation processing units (13R), (13G), and (13B) process the three primary color data DI1 of the 2fs clock rate.
＊＊＋ DGmyuD. ．． The above adder (14R),
(14G), (14B) The detail signal generating section (11) also supplies the A/D converter (6G) to the A/D converter (6G).
The green data of the Is rate obtained by DG. and fs rate red data DI1. obtained by the A/D converter (6R). and an adding means for adding the same amount by multiplexing with a 2fs chronocratic rate;
・・・・The above-mentioned interpolation processing unit (13R) is indicated by ■.
, (13G) . The filter characteristic H(
Z)+! It is configured to include a digital filter that performs differential processing by providing un. Then, the detail signal generating section (11) generates a detail signal DI! that includes the differential output from the digital filter as a horizontal detail signal IEH. ** is added to the adder (14R), (
14G) and (73B).

These adders (14R), (14G), (7
Is 3B) supplementary to the above? Processing section (13R), (13G),
Three primary color data D1*■D Gril from (13B)
Detail signals D1, . By adding , the above three primary color data D,. +DG+DI. Apply image enhancement processing to the image. This image enhancement processed three primary color data D. * 1 D G * * 1 D
@ * 'T is the gamma correction processing time 1 (151?).
Supply to (15G) and (15B). And the gamma correction processing circuit (15!?), (
15G), (15B) is the above adder (141?)
, (14G), (14B) three primary color data D, . D 5s*IDl11
Gamma correction processing is performed on m, and each color data D 1111111 D Ql)+1+ D @m
Output e.

Here, the above-mentioned interpolation processing unit <13R), (13(;
), (13B) and the detail signal generating section 01), if the even/odd orders m and n of the respective dissicle filters are not defeated, the interpolation processing section (131?), (1
The group delay caused by the digital filter for interpolation processing in 3G) and (13B) and the group delay caused by the digital filter for differential processing for detail signal generation in the detail signal generation section (l1) are deviated, Even if a detail signal is added to an interpolated signal, image enhancement processing cannot be performed satisfactorily.

For example, the interpolation processing section (131?), (13G),
If even-order (second-order) interpolation is performed in (13B) and odd-order (first-order) differentiation is performed in the detail signal generator (l1), as shown in FIG. fs rate green data DG. with a phase difference. ．． and red data Do are subjected to quadratic interpolation processing, respectively, to obtain green data D, . and red data D, . ．． Luminance data Y obtained by adding .

0) The center of the group delay is located at the position indicated by P cpv in the figure, but the green data D, . and red data DR. A signal D with a clock rate of 2fs is obtained by multiplying and adding the same amount at a clock rate of 2fs.
(The center of the group delay of the horizontal detail signal IEH.. obtained by first-order differentiation of C4RI*Y is the center of the group delay of the luminance data Y.. as shown by PIER in the figure p c. It is shifted by 1/(4fs) with respect to pv, and the horizontal detail signal IEH is applied to the luminance data Y.
．． ．． The waveform of the horizontal contour-compensated luminance data YIEH** obtained by additively synthesizing the images is not point symmetric. On the other hand, in the signal processing circuit according to the present invention, the above-mentioned interpolation processing units (13R), (13G), (13
B) and the detail signal generating section (I1), by eliminating the even/odd order of m and n of each digital filter,
The group delay and detail signal generated by the digital filter for interpolation processing match the group delay caused by the digital filter for differential processing, and even if the detail signal is added to the interpolated signal, image enhancement processing can be performed well. It can be carried out.

For example, the interpolation processing section (13R). (13G) ,
When even-order (second-order) interpolation is performed in (13B) and even-order (zero-order) differentiation is performed in the detail signal generator (11), as shown in FIG. Adding 2fs rate green data DG*@ and red data D@** obtained by performing quadratic interpolation processing on fs rate green data DG* and red data 1:l1* having a phase difference. The luminance data obtained by YY. The center of the group delay is P GPY in the same figure.
Located at the position indicated by , the green data Dc at the above fs rate
- and red data D, . The center of the group delay of the horizontal detail signal IEH obtained by performing the O-th differentiation of the signal D (G-...) at a 2 fs clock rate obtained by multiplying and demultiplexing and adding the same amount at a 2 fs clock rate is ,
As shown by PIEH in the figure, the luminance data Y. ．．
coincides with the center of group delay pcry, and the luminance data Y above. horizontal detail signal IEH. ．． Luminance data that has undergone horizontal contour compensation processing and is obtained by adding and combining the
IE) The waveform of I** is point symmetrical with respect to the phase of the center of the group delay. In addition, the interpolation processing units (13R), (13G) .
(13B) performs odd-order (first-order) interpolation, and the detail signal generator (l1) performs odd-order (first-order) differentiation, as shown in FIG. 9, 1/(2fs) Green data DG* and red data D.Is rate having a phase difference. Green data DG. at a 2fs rate obtained by performing linear interpolation processing on each of DG. and red data D. ．． Luminance data Y obtained by adding . The center of the group delay is P in the figure. Located at the position indicated by V, the green data DG. and red data D. 2fs clock rate signal D41 which is obtained by multi-branching and adding equal amounts of 2fs clock rate and 2fs clock rate signal D41. 1
Horizontal detail signal IE obtained by second-order differentiation
H. ．． As shown by P1o in the figure, the center of the group delay of Y. ．． The waveform of the horizontal contour compensated luminance data YIEHa which is obtained by adding and combining the horizontal detail signal IEH.. with the luminance data Y. Point symmetry is achieved with respect to the phase of the center of delay.

In this embodiment, the detail signal generating section (1l
) is a first delay circuit (CIl)I which uses green data DG* obtained by the A/D converter (6G) as input data CIl)I, as shown in FIG. 21) and red data DR.21) obtained by the A/D converter (6R). The second delay circuit (22) is provided with a second delay circuit (22) having a human data RIM.

The first delay circuit (2l) includes two IH delay circuits (21a) . (2lb) connected in series. This first delay circuit (21) is connected to the A/D converter (6G)
Regarding the green input data Gl1+ supplied from OH
Delay output G+N, IH delay output G1. , and 2H delayed outputs G,,lDL to the first comb filter (23), and the IH delayed output to the delay circuit (13G).
The data is supplied to the interpolation processing section (14G) through the interpolation processing section (14G). Similarly,
The second delay circuit (22) includes two IH delay circuits (22a) . (22b) are connected in series. This second delay circuit (22) is connected to the A/D converter (6G)
For the red input data RIN supplied from OH delay output RIM, IH delay output R,. , and the 2H delay output R tNIIL to the second comb filter (24), and the IH delay output to the delay circuit (13R).
The data is supplied to the interpolation processing section (14R) through the interpolation processing section (14R). The first comb filter (23) processes the green input data 61N supplied from the A/D converter (6G) to the first delay circuit (2l).
The above three types of delayed outputs from G INI C Il
Based on lOL+02MOL, DC=ω-・GIN... The filter outputs GH, GV, and DC shown by (2) are given to the mixer circuit (25).

Further, the second comb filter (24) includes the A/D
Regarding the red input data RIM supplied from the converter (6R) to the second delay circuit (22), the three types of delay outputs R I N + from the second delay circuit (22)
Based on Rl1IDLI Rt++ot, RH=-{
2+(ω-1+ω)・R1,} ...■4 Or, RH-ω-1・Rll+ ... ■R V= -
{ 2-(ω-'+ω) − R+sl −
■4 Or, RV=0.・・■ ω DR= − (1 +Z”)・R ... [Phase]
2 Or, the filter outputs RH, RV, DR of DR=O...■ are connected to the mixer circuit (2
5).

The mixer circuit (25) outputs the filter outputs GH, GV, DC from the first comb filter (23) and the filter outputs RH, RV, DR from the second comb filter (24). Based on IEH゜=aH+RH
．． -@IEV' =GV+cr・RV (α10, father,'/2.1) ... @LEV-
GH+β・RH...- ■or LEV=DC+β- DR (β=0.1)...■ Combined output IEH'. Outputs IEV' and LEV.

The above-mentioned combined output rEH' from the above-mentioned mixer circuit (25) outputs the filter output GH from the first comb filter (23) and the filter output RH from the second comb filter (24) at a clock rate of 2 fs. The first digital filter circuit (26
).

In this way, even in this color television camera device in which the spatial pixel shifting method is adopted in the imaging section, the above A
The above red data D. obtained by /D converters (6R) and (6G). and green data D. In the detail signal generating section (11) to which the above-mentioned comb filter (22) is supplied, the filter output GH from the above-mentioned I-th comb filter (22) and the filter output RH from the above-mentioned second comb filter (24) are connected to the above-mentioned mixer circuit (25). ), all the first-order carrier components are canceled, and a wideband horizontal detail signal IEH' can be obtained without aliasing distortion.

Here, in this color television camera device in which the spatial pixel shifting method is adopted in the imaging section, in addition to adding equal amounts of the green image imaging signal and the red image imaging signal, the green image imaging signal and the blue image imaging signal are Even if you add an equal amount of the red image signal and the blue image signal, or add an equal amount of the composite signal of the red image signal and the blue image signal to the green image signal, a certain amount of the first-order carrier is completely canceled and aliasing distortion occurs. It is possible to form a wideband horizontal detail signal without the need for Further, the filter output GV from the first comb filter (23) and the filter output RV from the second comb filter (24) are mixed by the mixer circuit (25) at 1:α
The above-mentioned combined output IEV' added at the ratio of is sent to the second digital filter circuit (27) as a vertical detail signal.
is supplied to Furthermore, the filter output GH or DG from the first comb filter (23) and the second comb filter (24)
The filter output RH or DH from the mixer circuit (
25), the above composite output LE added at a ratio of 1:β
V is supplied as a level signal to the level dependent signal generation circuit B (28).

Then, the composite output fE is output from the mixer circuit (25).
The l-th digital filter circuit (
26) uses a high-pass filter characteristic having at least two or more even number of zeros in fs,
Forms a 2fs rate horizontal detail signal. This first digital filter circuit (26) has the following equation, for example, as shown in FIG. 12, which shows an equalizing Bronnok configuration:
) - (The first filter block (41) denoted by the transmission interval number H + (z) of In4, and 1 Hz (z) = - (-z-"+2z-' - 1
) --- A second filter block (42) denoted by the transfer function Hz(z) of @4, and ■ Hx(z) = (z-"+2z-'+l)
--- ■4 The third filter prosoch (43) shown by the transfer function Hs(z) and l Ha(z) = − (Z−'+22−”+1)
--- ■4 A fourth filter block represented by a transfer number H4(z) and weighting coefficients ap, β, . β2. Each coefficient circuit giving β3 (45), (46) . (47),
(4B) and each of the above coefficient circuits (46), (47)
, (48) is composed of an adder circuit (49) that adds the outputs of (48). The first digital filter circuit (26) has 2(s
By operating at a processing rate of 1 TEH= (-z 4+22 ''- 1) 4 β1 × { (z-'+2z z+1) (2 "+2z"-. 1 ) l6 β2 + - (z-"+2z-' + 1 )4 β3 10- (-z-"+2z-' 1) l-I
E H4 ... [Phase] aρ A P = (-z-'+2z-'+1)1
6 × (1zbe+2z-1) ... Each filter output of 0 IEH. Here, the combined output IEH' from the dixa circuit (25) is the first
The filter output GH from the comb filter (23) and the filter output R from the second comb filter (24)
H and each comb filter (23
)． (24), the band is limited in the vertical direction on the two-dimensional frequency space shown in 13l2I. The first digital filter circuit has a high-pass filter characteristic having at least two or more zero points at "S" near the color subcarrier frequency fsc of the composite color video signal! (26)
The horizontal detail signal ■EH obtained by band-limiting in the horizontal direction in the two-dimensional frequency space shown in FIG. , it is possible to perform high-quality horizontal contour enhancement processing without cross-color interference.

The filter output IEH from the first digital filter circuit (26) is supplied to the adder (29) as a horizontal detail signal, and the filter output AP is supplied to the first core circuit (30) that performs nonlinear processing. The output signal is supplied to an adder (34) via the adder (34).

Further, the second digital filter circuit (27) is
For example, as shown in FIG. 14, the equalization block structure is
H+(z) = − (z−′+2z−′+1) to the vertical detail signal IEV′ by the mixer circuit (25).
=-@4 transmission interval number H. (z); and this first filter block (51).
The filter output signal and the above vertical detail signal ■E
A first switching circuit block (52) selects V and switches the filter characteristics, and a first selection output signal from this first switching circuit block (52) is 1 H! (2) = − (z−'t2z−”+1)
--- Select the second filter block (53) that provides the transfer function Hz (z) of @4, the filter output signal from this second filter block (53), and the first selected output signal. a second switching circuit block (54) for switching the filter characteristics;
A coefficient circuit (55) that multiplies the second selected output signal according to 4) by a weighting coefficient α, and a transfer function of l H3(Z) (1+z”) [phase] 2 to the output signal from this coefficient circuit (55). and a third filter block (56) that provides Hz (z).

This second digital filter circuit (27) has the above-mentioned comb filters (23) and (24), so that 1 H(z) = − (Z−”+22−”−.1)
--・@4 For the vertical detail signal IEV' of the chronocrate of Is given the filter characteristic H (z), it operates at the processing rate of fs, and as shown by the dashed line in FIG. A filter characteristic H that has a zero point at fse,
(z) and the filter characteristic Hz(
z), the transfer function Ha as shown by the solid line in the figure
(z) l Ha(z) = − (z−” +2z−′+ 1
)64 X (Z-'+22-"+ 1)
A vertical detail signal IEV is formed and this vertical detail signal IEV is supplied to the adder circuit (29). Here, the vertical detail signal IEV' is the filter output GV from the first comb filter (23),
Filter output R from the second comb filter (24)
V, and each of the above comb filters (23
)． (24), the band is limited in the vertical direction on the two-dimensional frequency space shown in FIG. 13 above. the second digital filter circuit (27) having two or more zero points near the color subcarrier frequency fsc of the composite color video signal;
The vertical detail signal IEV obtained by band-limiting in the horizontal direction in the two-dimensional frequency space shown in FIG. It is possible to perform high-quality vertical contour enhancement processing without causing cross-color interference.

The adder circuit (29) operates at a processing rate of 2 fs and processes the 2 fs Cronk rate horizontal detail signal IEH supplied from the first digital filter circuit (26) and the second digital filter circuit (27). ) is added to the chronocratic vertical detail signal IEV of Is supplied from 2 by this adder circuit (29)
The addition output signal of the fs cross rate is sent to the multiplication circuit (32) via the second core circuit (31) that performs nonlinear processing.
).

Further, the level dependent signal generation circuit i (28) to which the combined output LEV from the mixer circuit (25) is supplied as a level signal is connected to a level dependent signal fg number LD corresponding to the level signal LE■. is generated and supplied to the multiplication circuit (32) via a multiplication circuit (33) that multiplies this level-dependent signal by an LD weighting coefficient.

The multiplier circuit (32) adds the bell-dependent signal LD multiplied by the weighting coefficient by the multiplier circuit (33) by the adder circuit (29) which has undergone nonlinear processing by the second core circuit (31). The output signal is multiplied and the multiplied output signal is supplied to the adder circuit (34).

This addition circuit (34) is the first core circuit (3o)
The above first digit is subjected to non-linear processing by ? The filter output AP from the filter circuit (25) is added to the multiplication output signal from the multiplication circuit (32), and the added output is converted into a detail signal DIE* at a clock rate of 2 fs.
Output as *.

The detail signal IE12m at the clock rate of 2 fs is generated from the detail signal generating section (11) in such a configuration.
The above adders (14R) and (14G) to which m is supplied
(14B) is the interpolation processing unit (13R), (1
3G), (13B) at a 2fs rate. ■D. + DI Image enhancement processing is performed by adding to I■. Then, the adders (14R), (14G) . (14B) is
Three primary color data D, which has undergone image enhancement processing. ,DG
*■D. One is the gamma correction processing circuit (151?),
(15G) and (15B).

The above gamma correction processing circuit (15R), (15G)
, (15B) is the adder (1411), (1
4G). (14B) image enhancement processed three primary color data DIl*■D ellllll DI1
Gamma correction processing is performed on mm, and gamma correction processed three primary color data D lii *+ D G$11+ D 111
Outputs 8.

? The signal processing unit (7) generates 2fs Cronkrate three primary color data D, . ,DGII■D,. ．．
Output. The three primary color data D, at a clock rate of 2 fs, are output from the signal processing section (7). ＋D
G. + DI. are supplied to a color encoder (8), and are also supplied to a digital-to-analog (D/A) converter (9R). (9G) and (9B).

And the above D/A converters (9R), (9G),
(9B) is the 2 signal supplied from the signal processing section (7).
The three primary color data D11111 D611111 D1 which ensured the high resolution of the fs Chronocrate are converted to analog to produce an analog three primary color imaging output signal Rouy.
+ GOUTI Bout as signal output terminal (IOR)
．． Output from (LOG) and (IOB).

Further, the color encoder (8) is connected to the signal processing section (7) as shown in FIG.
). 3 primary color data D at the clock rate of 2 fs from above
lllj)+D G*111 D @*@ is supplied to the matrix circuit (81), and this matrix circuit (
81), the luminance signal data D7. ．． Is it supplied? A delay circuit (82) and this matrix circuit (
8l), each color difference signal data DIl-Yj
+DI i. , D, ■D(H are supplied to each low-pass filter (83), (84), (85) . (86)
and D1, which is expressed by the matrix circuit (8l) above.
■D0. are each of the above low-pass filters (85) and (8
6), an interpolation processing circuit (88) to which modulated output data from this modulation circuit (87) is supplied, and an interpolation processing output data from this interpolation processing circuit (88). Luminance signal data Dvl is supplied and is also formed by the matrix circuit (81).
llll is supplied via the delay circuit (82).

The matrix circuit (8l) receives the three primary color data DI1.1DG*■D 1 m at the clock rate of 2fs.
By performing matrix calculation processing on m, 2
Luminance signal data D7 Yu.fs clock rate. and f
s clock rate color difference signal data D9Y...DI4
...DI., D+* is formed.

This color encoder (8) receives the three primary color data Dll*11+DC. , D@** is transmitted from the matrix circuit (81) through the delay circuit (82) as the luminance signal data D7. ．． At the same time, the matrix circuit (81) outputs each of the low-pass filters (83),
(84) through each color difference signal data DH-y*D.
1,. Output. The delay circuit (82) provides the luminance signal data D V** with a delay characteristic corresponding to each of the low-pass filters (83) and (84).

In addition, in this color encoder (8), the modulation circuit (87) directly outputs D1*IDo data supplied from the matrix circuit (81) via each of the low-pass filters (85) and (86). Performs phase modulation processing. The modulated output data from this modulation circuit (87) corresponds to a modulated color difference signal containing odd harmonics of the color subcarrier frequency fsc.

Further, the interpolation processing circuit (88) includes the modulation circuit (
Regarding the modulated output data according to 87), fsc precept and 7
A digital filtering process is performed to extract the fsc predetermined value, and the modulated color difference signal data of the black crate 2fs corresponding to 8fsc is formed.

The color encoder (8) then receives the luminance signal data D7. which is output from the matrix circuit (81) via the delay circuit (82). ．． and the above interpolation processing circuit (
By adding the modulated color difference signal data of the 2 fs clothocrate formed by 88) by the above-mentioned adding circuit (89), a digital composite video signal DCs is obtained.
... is formed. That is, the color encoder (8) generates three primary color data D at a clock rate of 2 fs, which has been subjected to image enhancement processing and gamma correction processing by the signal processing section (7).

I D G1) * 1 D l. Regarding the above 2fs
A component color image that is controlled by the luminance signal data D'I** ensuring a high resolution at a clock rate of fs, and each of the color difference signal data D*-y*, DBY* at a clock rate of fs. In addition to outputting data, it also outputs a digital composite video signal DCs** ensuring a high resolution at the clock rate of 2 fs.

The component color image data output from this color encoder (8), that is, the brightness? Signal data Dy** and each of the above color difference signal data D-Y11+D
I-1/11 is supplied to digital-to-analog (D/A) converters (9Y), (9R-Y), (9B-Y).

The above D/A converter (9Y), (9R-Y). (
9B-Y) is an analog component color video signal Y by converting the luminance signal data D V** and each of the color difference signal data D*-7■0m-■ into analogs.
. ,,,RYout+B Signal output terminal (IOY) as YOLIT, (101!-Y) . (IOB-
Output from Y).

Furthermore, the digital composite video signal Dcs. output from the color encoder (8). ．． is supplied to a digital-to-analog (D/A) converter (9CS). The D/A converter (9CS) generates an analog composite video signal CSouy by converting the digital composite video signal DCS**, which has a high resolution of the clock rate of 2 fs, into an analog.
output from the signal output terminal (IOCS). H. Effects of the Invention As described above, the signal processing circuit of the solid-state imaging device according to the present invention processes each imaging output signal read out at a sampling rate of fs from each solid-state image sensor of the imaging unit that employs the spatial pixel shifting method. For the digital output signal digitized by the analog-to-digital conversion means at a clock rate equal to the sampling rate Is, a signal at a 2fs rate is formed by the interpolation means, and
Image enhancement processing is performed by generating horizontal detail signals at a 2 fs rate by the detail signal generating means and adding these signals by the adding means. The detail signal generation means and the interpolation means exhibit group delay characteristics that match each other by selecting characteristics such that the number of zero points of each digital filter matches whether even or odd. According to the present invention, the group delay characteristics It is possible to perform good image enhancement processing that yields a waveform output that is symmetrical about the center phase of the image.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a three-panel color television camera device to which the present invention is applied, FIG. 2 is a schematic diagram showing the arrangement of each CCD image sensor in the three-panel color television camera device, and FIG. 4 is a diagram showing the signal spectrum of each imaging output signal from the CCD image sensor in the color television camera device described above, and FIG. 4 shows the structure of the signal processing section constituting the three-panel color television camera device. 5 is a characteristic diagram showing the characteristics of the digital filter provided in the interpolation processing section which constitutes the signal processing section, and FIG. 6 is a characteristic diagram showing the characteristics of the digital filter provided in the detail signal generation section which constitutes the signal processing section. A characteristic diagram showing the characteristics of the filter. FIG. 7 is an explanatory diagram of the horizontal contour enhancement processing operation when the interpolation processing section performs even-order interpolation processing and the detail signal generation section performs odd-order differential processing. 9 is an explanatory diagram of the horizontal contour enhancement processing operation when the above-mentioned interpolation processing section performs even-order interpolation processing and the above-mentioned detail signal generation section performs even-order differential processing. Figure 9 is an explanatory diagram of the horizontal contour enhancement processing operation when the above-mentioned interpolation processing section performs odd-order interpolation processing. An explanatory diagram of the horizontal contour enhancement processing operation when odd-order differential processing is performed in the detail signal generation section, FIG. 10 is a professional diagram showing a specific horizontal example of the detail signal generation section of the signal processing section, and FIG.
12 is a block diagram showing the equalization block structure of the first digital filter circuit of the detail signal generating section, FIG. 12 is a characteristic diagram showing the filter characteristics of the first digital filter circuit, and FIG. 14 is a schematic diagram showing the frequency characteristics of the detail signal generated by the detail signal generation section on a two-dimensional frequency space, and FIG. 14 is an equalization block diagram of the second digital filter circuit of the detail signal generation section. FIG. 15 is a characteristic diagram showing the filter characteristics of the second digital filter circuit, and FIG. 16 is a diagram showing the structure of the color encoder constituting the three-dimensional color television digital camera device. This is a bronc diagram. FIG. 17 is a schematic diagram showing a signal spectrum of an image output signal from a general solid-state image sensor having a discrete horizontal pixel structure. (4R) (4G), (4B) ・・・・・・(6R
), (6G). (6B). ．． ．． ．． ．． (7)...
・・・・・・・・・・・・(8)・・・・・・・・・・・・
・・・・・・(11) ・・・・・・・・・・・・・・・
...(13R). (13G), (13B). ．． ．． (2
6) ・・・・・・・・・・・・・・・・・・ CCD image sensor A/D converter Signal processing section Color encoder Detail signal generation section Interpolation processing section Digital filter circuit

Claims (1)

[Scope of Claims] The above-mentioned imaging unit in which a solid-state image sensor for green image sensing and a solid-state image sensor for red and blue images are spatially shifted by 1/2 of the repetition pitch of each pixel. analog-to-digital conversion means for digitizing each imaging output signal read out from each solid-state image sensor at a sampling rate of fs at a clock rate equal to the sampling rate fs; A horizontal detail signal with a clock rate of 2 fs, which is twice the sampling rate fs, is added to the frequency of the fs from a signal obtained by adding equal amounts of the image pickup signal, the red image pickup signal, the blue image pickup signal, or a composite signal of both signals. interpolation means for interpolating each digital output signal of the analog-to-digital converting means to a clock rate of 2fs using a digital filter having a zero point at the frequency of fs; addition means for adding the output signal of the signal generation means to the output signal of the interpolation means, and the detail signal generation means and the interpolation means are selected to have a characteristic that the numbers of zero points of each of the digital filters are even or odd. A signal processing circuit for a solid-state imaging device, characterized in that: