JPH03171825A - Ternary/binary converter - Google Patents

Abstract

PURPOSE:To reduce the loss error by deciding and correcting erroneously demodulated one of higher-order data and lower-order data at the time of demodulating the lost level and converting data to preliminarily determined data at the time when second decision data is not significant. CONSTITUTION:A series/parallel conversion means 11 converts each pair of data constituting ternary 2-baud data of conversion data to two parallel data and outputs them. First deciding means 21, 15, and 23 detect the difference between distances from higher-order data and lower-order data of two parallel data to the middle value corresponding to ternary level '1' and output binary code decision data. Second deciding means 24 and 25 compare the absolute value of this difference with a preliminarily determined threshold to output binary code decision data. A ternary/binary converting means 19 converts data to 3-bit binary data in accordance with a preliminarily determined conversion format based on first and second decision data. Thus, the loss error is reduced.

Description

Detailed Description of the Invention [Field of Application in Business A] The present invention is directed to a 3-bit system that is used to convert ternary 2-baud data into binary 3-bit data, for example, in a MUSE audio demodulation circuit. Regarding value/binary conversion devices. [Prior Art] NH is a method for multiplexing audio and other independent data (hereinafter referred to as "audio data") transmitted by audio channels of the MUSE system, which is a high-definition transmission system.
``Speech/independent data multiplexing system'' mentioned in the document titled ``Development of rMUSE system'' in K Technical Research Vol. 39, No. 2 (pages 90-92) and JP-A-62-
There is an ``audio baseband multiplexing method'' described in Publication No. 172874. In this method, the bit rate is 1 in the modulation circuit on the transmitting side.
．． 35 [M bit/S] binary NRZ encoded audio/independent data is transferred to Hl.35 [M bit/S]. 225 (time axis compressed to M bit/sj data, then binary NRZ code to ternary NR
By converting to Z code, the baud rate becomes 12.15 [M
Baud/sl (sampling frequency 12.15
[MHz] ) into 3-value NRZ code data, and then convert this 3-value NRZ code data into data with a sampling frequency of 16.2 [MHz], which is the same as the video signal of the MUSE method, and convert the video signal into It is time-base compressed multiplexed and transmitted during the vertical planking period. In addition, the demodulation circuit on the reception side receives this data, resamples it using a digital filter, converts it to data of 12.15 [MHI], and then converts it to data with a baud rate of 12.15 [MHI] using an amplitude discriminator.
Baud/s] into ternary NRZ code data,
Next, the data of this ternary NRZ code is converted to a bit rate of 1.
The data of the binary NRZ code of 8.225 [M b1t/s] is converted, and then the time axis is expanded to 1.35 [M b1t/s].
It is a method for demodulating into binary NRZ code voice/independent data of [it/s]. FIG. 6 shows the vibration #Nm division of the audio demodulation circuit described in Japanese Patent Application Laid-Open No. 62-172874. FIG. 2 is a block circuit diagram showing the configuration of a resample section and a ternary/binary conversion section. In the figure, (1) is a manual terminal, 16.2 [MHz]
Binary 8-bit ternary NRZ code audio/independent data a (
(hereinafter referred to as "data a") is input. (2) is a first comparator that compares the value of input data a and the first judgment value p set to a predetermined value (178 in this example). It compares the size with that and outputs a signal of ``1'' or ``O'' based on the comparison result. (3) is a second comparator that compares the value of the manually input data a with the second judgment value q (78 in this example), and based on the comparison result, determines whether
Comparators (2) and (3) demodulate binary 8-bit data a into binary 2-bit ternary NRZ code data b (hereinafter referred to as "data b"). An amplitude discriminator (4) is configured. (5) is a shift register in which data b is input manually and driven by a clock of 18.2 [MHZ]. (6) is a latch, and the shift register (5
) is input, and is driven by the output clock of a quaternary counter (7) which receives the clock of 16.2[M}IZ]. (8) is a switch to which the output signal of the latch (6) is input, and is driven by the output clock of the ternary counter (9) which uses the clock of 12.15 [MHZ] manually, and the switch registers (5) to 3 Discard the invalid data of data b using the decimal counter (9) and get 12.15 [M}Iz]
The sample section (10) is configured to convert the data into binary 2-bit ternary NRZ code data d (hereinafter referred to as "data d"). (11) is a serial-to-parallel converter, which converts the data d output from the manually operated switch (8) into two parallel data di, d2 for each set of data containing audio data, and outputs it. ) is a three-value/binary converter configured with a ROM, for example, and converts the two parallel data di, d2 input from the serial-parallel converter (11) into 12.15 [MH
z] 3-bit binary NRZ code audio/independent data e
Convert to This serial-parallel converter (l1) and ternary/2
The value converter (12) constitutes the ternary/binary converter (13). (14) is the 3m! of the ternary/binary converter (l2). F
This is the l+ output terminal. ? The operation will be explained below. As shown in FIG. 7, the data rate of data a input to the human input terminal (1) is a clock rate of 16.2 MHz, and there is invalid data once every four clocks. The relationship between the value of the input data a, the classification of the ternary levels r2'', r1'', and rJ, and the first and second determination values p and q is as shown in FIG. The input data a is passed through the comparator (2
) and (3), the comparators (3) and (4) respectively output "1" when p≦a, indicating the ternary level "2". "
11'', and when p>a>q, outputs rQ'' and rIJ to indicate the ternary level ``1''.
01'' into 2-bit data, and when a≦q, r
QJ, rQJ are output and "00" indicating the ternary level "0" is output.
” into 2-bit data b. This data b is
16.2 [M} The shift register (5) operated by the IZI clock divides the data into four consecutive pieces of data, removes invalid data, and latches the three data (6).
) is input. The latch (6) latches three data at the same time, converts them into three parallel data, and outputs them to the next switch (8). The switch (8) is switched by a 12.15 [MHz] clock, and the three parallel data are
[Convert to MHzl serial data. This data d is
1 configuring audio data with a serial-parallel converter (11)
There are two parallel data di and d2 for each set of data, and a ternary/binary converter (l2) converts the data at 12.15 [MHz] according to the ternary/binary conversion format shown in Table 1, for example.
Conversion to binary 3-bit 3-parallel data e Table 1 In the conversion format shown in Table 1, ternary 2-baud data can represent 9 levels of information from "22" to "00", The data with a value of 3 bits is rl
Eight levels of information from 11J to r000J can be expressed. Therefore, from ternary 2 baud data, 2
3-value 2 not used when converting to 3-bit data
There is one level of Beau. This level is called the "erasure level", and the conversion error to binary data that occurs when the "erasure level" is demodulated by the amplitude discriminator (4) is called the "erasure error". In Table 1, the "disappearance level" is "11".

Note that if a "vanishing level" is detected due to noise in the transmission system, jitter in a VTR, etc., no matter how you set the binary 3-bit data corresponding to the r-vanishing level, conversion of 1 bit or more will not be possible. The probability that an error will occur increases.

[Problems to be Solved by the Invention] Since the conventional ternary/binary conversion device is configured as described above, when the "erasure level" is demodulated, a conversion error of 1 bit or more occurs, There is a problem in that when the error rate increases, the audio cannot be reproduced faithfully.

This invention was made to solve the above problems, and when the "erasure level" is demodulated, the original correct data can be estimated and conversion errors can be kept low. The purpose is to obtain a binary conversion device. [Means for Solving the Problems] A ternary/binary conversion device according to the present invention discriminates the value of binary N-bit manual data to obtain ternary levels r2', r2<
1b <1'', rl < la <0'', and ``O''; A serial/parallel conversion means for converting and outputting two parallel data for each set of data composing the lower order data, and a distance from the intermediate value corresponding to each of the above three-value level "1" before conversion of the two parallel data. The second section detects the difference between the values and outputs binary code judgment data indicating whether the difference value is positive or negative. a second determining means that compares the absolute value of the difference value with a predetermined threshold value and outputs determination data in a binary code indicating the result; The present invention is characterized by comprising a ternary/binary conversion means for converting data into binary 3-bit data based on the data and the first and second judgment data regarding the two parallel data. [Operation] The conversion means in the present invention converts the sign of the most significant bit (MSB) of binary N-bit human input data and the value of this input data into a ternary level "2". "1". It distinguishes which of the three categories of "0" it belongs to and converts it into binary 2-bit data by combining it with a code obtained by taking the exclusive OR of the data expressed in binary 2-bits.This converted data is ,
The value of the input data is the ternary level '2J. r2>1b>
IJ, rl>la>0'', r0'' indicates which of the four categories the value belongs to. The serial-to-parallel conversion means outputs the converted data by converting it into two parallel data for each set of data that composes ternary and two-baud data. The first determination means detects the difference in which of the upper data and lower data of the two parallel data is farther from the intermediate value corresponding to the ternary level "1", and Binary sign determination data indicating whether the value is positive or negative is output. The second determination means compares the absolute value of the difference value with a predetermined threshold value and displays the result.
Outputs the value sign judgment data. The ternary/binary conversion means includes two parallel data and a first
Based on the second determination data, the data is converted into binary 3-bit data according to a predetermined conversion format. As a result, if the erasure level is demodulated,
If it can be clearly determined which of the upper data and lower data was demodulated incorrectly, the corrected ternary value 2
The data is converted into binary 3-bit data corresponding to the baud data, and if it cannot be clearly determined, it is converted to data that specifies the erasure level without making any corrections, so erasure errors can be reduced. [Embodiment of the Invention] An embodiment of the invention will be described below. Figure 1 is a block circuit diagram of this embodiment, and the same reference numerals as in Figure 6 indicate the same or corresponding parts, so their explanation will be omitted. In the figure, (20) is an exclusive OR circuit to which the output data d of the amplitude discriminator (4) is input, and the serial/parallel converter (11
) outputs the logic signal g. On the other hand, this serial-parallel converter (
11), the MSB of the serial data C output from the switch (8) is input. (21) is an exclusive OR circuit, which is composed of seven exclusive OR elements as shown in Figure 3, and one input of each element is connected to the 8-bit series output from switch (8). The MSB of data C is input,
The other input receives signals from 2SB to LSB, and outputs 7-bit data κ, (tS
) is a serial-to-parallel converter, which converts a set of data forming the audio data into 7-bit parallel data K1 and K2, respectively, and outputs it. (23) is a subtracter, which outputs the subtracted value data m of KIK2. , (24) is an absolute value circuit that outputs 1 ml of the absolute value of the subtraction value data m, (25) is a comparator that outputs the input absolute value 1 ml and a predetermined comparison value r
When the comparison result is lml≧r, the judgment data n is “1” and when the comparison result is Infer, it is “O”. This exclusive OR circuit (21
), a serial-to-parallel converter (15), and a subtracter (23) constitute the first determination means, and an absolute value circuit (24) and a comparator (2
5) constitutes a second determination means, and the first and second
The determination means constitutes the erasure level determination section (26). (19) is a ternary/binary converter, and a serial/parallel converter (11
) and the combination of the first judgment data m and the second judgment data n input from the erasure level judgment unit (26), the ternary value / of Table 7 and Table 8, which will be described later, is determined. Conversion to binary 3-bit data is performed according to the binary conversion format. Next, we will explain the operation. From the 8-bit data a input to the human input terminal (1), four consecutive data ao, al, a2 and invalid data are taken out simultaneously by a shift register (5) operating at 16.2 MHz, and the invalid data is The other three data aO, al, a2 are output to the latch (6). The latch (6) simultaneously latches the three data ao, at, and a2, thereby converting them into three parallel data and outputting them to the switch (8). The switch (8) is switched at 12.15 [MHz], and the three parallel data ao, al, a2 input from the latch (6) are switched at 12.15 [MHz].
5 Convert to [MHz] serial data C and send to comparator (2)
．． (3) and the exclusive OR circuit (21), and its most significant bit (hereinafter referred to as rMSBJ) is output to the serial/parallel converter (11). As shown in Table 2 below, the MSB of this serial data C is information on whether this serial data C is greater than or less than the intermediate value (127.5>), that is, when the MSB is "1", it is greater than or equal to the intermediate value. Table 2 indicates that the value is below the intermediate value when it is "O".On the other hand, the binary 8-bit serial data C input to the amplitude discriminator (4) is It is compared with the judgment level p in the comparator (3) and with the judgment level q in the comparator (3), and demodulated into binary 2-bit ternary data d (hereinafter referred to as "data d").This 2-bit data d is , exclusive OR circuit (20
), and when the value Dn of the original serial data C of the data d is Dn≧P or Dn<q, “0 no P>Dn≧
9, data g of "1" is output.

Data h, which is a combination of this data g and the MSB of serial data C input from switch (8), is serial data before being converted to data d, as shown in Table 3 and Figure 4 below. The value of C is the ternary level r2 shown in FIG.
rl'', rQ'', the ``1'' category is divided into two by the intermediate value, r2J, ribJ
．． '1a'. It has information indicating which of '0' the value belongs to.

Table 3 In this table, the intermediate value is (127.5), which is the ternary level “
1". These data MSB and g are converted into two parallel data hl . h2 and is input to the ternary/binary converter (19). On the other hand, exclusive OR circuit (
21) is controlled by the MSB of input data C, as shown in Figure 6, and is shown in Table 4 below. 21) is an input/output characteristic diagram. The 7-bit data K output from this exclusive OR circuit (21) has an intermediate value (127.5) of the human data C.
It has information on how far away it is from. That is, when the value of data K is 127, it is closest to the intermediate value, and the smaller the value of data K, the further away from the intermediate value. Next, the data K is transferred to the serial-parallel exchanger (l5
), each set of data constituting the audio data becomes two parallel data Kl, K2 and is input to the comparator (23),
From the upper digit data (hereinafter referred to as "upper data") Kl to the lower digit data (hereinafter referred to as "lower data") K
A subtraction of 2 is performed. The output data m of this subtracter (23) is as shown in Table 5. Table 5 In other words, the MSB of the subtraction data m has information whether the subtraction result is positive or negative, and is ``O'' when K1≧K2 and ``1'' when Kl <K2. When the MSB, which is the first judgment data, is "Oj, it indicates that the lower data K2 is farther from the intermediate value than the upper data Kl, or is the same, r.1" indicates that the upper data Kl is further away from the intermediate value.Next, the absolute value 1ml of the subtracted value data m is taken in the absolute value circuit (24), and the absolute value 1ml is taken manually by the comparator (25). and a predetermined reference value r, and when 1ml≧r, r1 is output, and when ml<r, the second determination data n is output as “0”.

When this second judgment data n is “O”, IKI-K
If the difference between 21 and 21 is small, and both data are the same distance from the intermediate value, and it is not possible to determine which data was erroneously demodulated to the ternary level "1", and both data are erroneously demodulated to 1 This indicates that the signal has been demodulated to a ternary level "1". Also, the judgment data n is “1”.
”, one of Kl and K2 is far away from the intermediate value, and when combined with the first determination data MSB, the data that was erroneously demodulated to the ternary level “1” becomes the upper data. It is possible to determine which data is the lower-level data. Table 6 shows the combinations of the first and second judgment data and the judgment results. Table 6 The ternary/binary converter (19) converts the erroneously demodulated data into binary 3-bit data based on the combination of this determination result and the two parallel input data Kl and K2. If the second judgment data n is "O", no correction is performed to prevent errors of two or more bits from occurring due to incorrect correction. Next, Table 7 shows the conversion formula of the ternary/binary converter (l9) when data other than erasure level "11J" is demodulated. When erasure level "l1" is demodulated, upper data K1 and lower data One of K2 accidentally
There is a high probability that the higher-order data K1 is demodulated by mistake, such as when "21" is demodulated into "11" and when "01" is demodulated into "l1". .In addition, if the lower data K2 is demodulated by mistake,
This is a case where "12" is erroneously demodulated as "1l" and "10" is erroneously demodulated as "11". The original binary 2-baud data “2
In the case of FIG. 2(a), in which ``1'' is erroneously demodulated as rib 1bJ in the amplitude discriminator (4), the ternary level ``
Since the upper data K1 is larger, Kl < K2, and the MSB of the judgment output m of the subtracter (23) is "1". Furthermore, since l Kl −K2 l>r, the judgment output n of the comparator (25) becomes “1”. By combining the MSB and n of these two determination data m, it is determined that the value of the data before demodulation of the higher-order data h1 belongs to the ternary level "2" category, so ternary/binary ゜converter(
l9) is this first and '! M of judgment data m of J2
In response to SB,n, the upper data h1 is corrected to the ternary level ``2'' and the binary 3-bit data r0 1 0J of Table 7 corresponding to the ternary 2-baud data ``21'' is output. In addition, in the case of Fig. 2(b) in which r10'' is erroneously demodulated as rla la'', IKl is K1 to K2.
-K2 1<r, and the judgment data n becomes rO.
The ternary/binary converter (l9) determines that this judgment data n is "0".
'', it is not possible to determine which data was demodulated in error, so it is converted to binary 3-bit data rooOJ, which is predetermined for the erasure level ``11''.In this case, the erasure error is ``10''. Conversion data r0
Since it is 01J, there is a 1-bit error. Table 8 below shows the conversion format table 8 when erasure level "11" is demodulated. Note that in the above embodiment, the case where the ternary/binary conversion format is the same as Table 1 is shown. The conversion format is not limited to this one, but can be configured as shown in Table 9 below to convert two parallel data corresponding to erasure level "11" into
Using the three-level classification rtbJ, rla,
As shown in Table 10 below, Table 9 Table 1 O? Effects of the invention] As described above, the ternary/binary conversion device according to the present invention has the following effects:
If you input binary N-bit input data, the value of the input data is 3.
value level r2'', r intermediate or higher 1''. Converts to binary 2-bit data indicating which of the four categories "IJ, r below the intermediate value" it belongs to, and demodulates each into upper data and lower data that make up 3-value 2 baud data. first judgment data that detects the difference between values that are far from the intermediate value of the original input data values and expresses the sign of the difference value with a binary code, and the absolute value of the difference value. and second judgment data that expresses whether or not it is larger than a predetermined threshold using a binary code, and based on these judgment data, when the erasure level is demodulated, the upper data and the lower data are determined. , determine which one was demodulated incorrectly and correct it, and if the determination data of 's2 is not significant, a predetermined binary value of 3 is determined for the erasure level.
Since it is configured to convert into bit data, it is possible to obtain a ternary/binary conversion device that can suppress erasure errors.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram of an embodiment of the present invention, Fig. 2 is a diagram showing an example of data combination when the erasure level is demodulated, and Fig. 3 is a block diagram of a conventional ternary/binary conversion device. Circuit diagram, Fig. 4 shows the data string input to the beam sample section, Fig. 5 shows 10 of the input data to the amplitude discriminator section.
Base number, ternary level, and discriminant value p. FIG. 6 is a block circuit diagram of a configuration example of the exclusive OR circuit (21) of the embodiment of FIG. 1, and FIG. 7 is a diagram showing the relationship between
The division INa of the value of the serial data C demodulated into
FIG. 8, which is a diagram showing xbJ, is an input/output characteristic diagram of the exclusive OR circuit (21) of this embodiment. (2). (3)
, (16)...Comparator, (4)...Amplitude discriminator,
(5)...Shift register, (6)...Latch, (
8)...Switch, (lO)...Resample section, (
11). (is)...Serial-to-parallel converter, (l3)
... Ternary/binary converter, (l9)... Ternary/binary converter, (20) . (21)...exclusive OR circuit,
(23)...Subtractor, (24)...Absolute value circuit, (
25)...Comparator, (26)...Elimination level determination unit. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) The ternary code data is converted into binary N-bit data.The value of the input data is discriminated and the ternary level "2"
”, “2<1b<1”, “1<1a<0”, and “0”. a serial-to-parallel conversion means for converting and outputting two parallel data for each set of data comprising upper and lower data of 2 baud;
Detecting the difference in distance from the intermediate value corresponding to the ternary level "1" of each value before conversion of the parallel data, and outputting judgment data of a binary code indicating the sign or negative of the value of the difference. a second determining means that compares the magnitude of the absolute value of the difference value with a predetermined threshold value and outputs the result as binary code determination data; and the two parallel data. and a ternary/binary conversion device that converts the two parallel data into binary 3-bit data based on the first and second determination data.