JP2681399B2 - Three-value / two-value converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a ternary value used to convert ternary 2-baud data into binary 3-bit data in a MUSE audio demodulation circuit, for example. / Binary conversion device.

[Prior Art] Independent data (hereinafter, referred to as "independent data") transmitted by MUSE type voice or other voice channels of high-vision transmission type
"Voice data") as a method for multiplexing "voice / independent data multiplexing method" discussed in the document entitled "Development of MUSE method" in NHK Technical Research Vol. 39 No. 2 (pages 90 to 92). , And "Voice Baseband Multiplexing System" described in JP-A-62-172874.

In this system, the bit rate is low in the modulation circuit on the transmission side.
1.35 [M bit / s] binary NRZ coded voice / independent data
Time axis compression to 8.225 [M bit / s] data, then 2
The baud rate can be increased by converting the 3-value NRZ code to the 3-value NRZ code.
12.15 [M Baud / s] (Sampling frequency 12.15 [MH
z]) of the three-valued NRZ code, and then the three-valued
NRZ code data is converted to data with the same sampling frequency of 16.2 [MHz] as the MUSE format video signal, and is time-axis compression multiplexed during the vertical blanking period of the video signal and transmitted.
The demodulation circuit on the receiving side receives this data, resamples it with a digital filter, converts it to 12.15 [MHz] data, and then uses an amplitude discriminator to determine the baud rate.
Converted to 12.15 [M Baud / s] ternary NRZ code data, and then convert this ternary NRZ code data to bit rate 18.225.
This is a method of converting to [M bit / s] binary NRZ code data and then time-axis expanding to demodulate to 1.35 [M bit / s] binary NRZ code voice / independent data.

FIG. 3 shows an amplitude discrimination section, a resample section and a ternary value / 2 of a voice demodulation circuit disclosed in Japanese Patent Laid-Open No. 62-172874.
It is a block circuit diagram which shows the structure of a value conversion part. In the figure, (1) is the input terminal, 16.2 [MHz] binary 8 bits 3
Value NRZ coded voice / independent data a (hereinafter referred to as “data a”) is input. (2) is a first comparator, which is a value of the input data a and a first judgment value p set to a predetermined value.
(178 in this example) is compared, and a signal of "1" or "0" is output based on the comparison result. (3)
Is a second comparator, which compares the value of the input data a with the second determination value q (78 in this example), and based on the comparison result, the value of "1" or "0" is compared. Amplitude discrimination that outputs a signal and demodulates binary 8-bit data a by comparators (2) and (3) into binary 2-bit ternary NRZ code data b (hereinafter referred to as "data b") Configure the vessel (4).
(5) is a shift register, which receives data b.
It is driven by the clock of [MHz]. (6) is a latch,
The output signal of the shift register (5) is input, and 16.2 [MH
It is driven by the output clock of the quaternary counter (7) which receives the clock z] as an input. (8) is a switch, which receives the output signal of the latch (6) and is driven by the output clock of a ternary counter (9) which receives a clock of 12.15 [MHz], and shift registers (5) to ternary A counter (9) discards invalid data of data b and forms a resample unit (10) for converting it to 12.15 [MHz] binary 2-bit ternary NRZ code data d (hereinafter referred to as "data d"). . (11)
Is a serial-parallel converter, and outputs the data d output from the input switch (8) as 2 parallel data d1 and d2 for each set of data constituting the audio data. (12) is a three-value / two-value converter composed of, for example, a ROM, which converts the two parallel data d1 and d2 input from the serial converter (11) to 12.15.
[MHz] Converts to 3-bit binary NRZ coded voice / independent data e. The serial / parallel converter (11) and the three-value / two-value converter (12) constitute a three-value / two-value conversion unit (13). (14) is 3
The output terminal of the value / binary converter (12).

Next, the operation will be described. The data rate of the data a input to the input terminal (1) is, as shown in FIG.
At the clock rate of 16.2 [MHz], there is invalid data once every 4 clocks. The value of the input data a and the division of the ternary levels "2", "1", "0" and the first and second
The judgment values p and q of are in a relationship as shown in FIG. The input data a is compared with the judgment values p and q in the comparators (2) and (3), respectively, and the comparators (2) and (3) respectively output “1” when p ≦ a. Then, it is converted into 2-bit data of “11” indicating the ternary level “2”, and when p>a> q, “0” and “1” are output to indicate the ternary level “1”. It is converted to 2-bit data of "01", and when a≥q, "0" and "0" are output and converted to 2-bit data b of "00" indicating a ternary level "0". This data b is divided into four continuous data by a shift register (5) operating at a clock of 16.2 [MHz], invalid data is removed, and three data are input to the switch (6). It The latch (6) simultaneously latches three pieces of data into three parallel data and outputs it to the next switch (8). Switch (8) is 12.15 [MHz]
The 3 parallel data is 12.15 [MH
z] serial data. This data d becomes two parallel data d1 and d2 for each set of data constituting the audio data by the serial-parallel converter (11), and the three-value / two-value converter (1
In 2), for example, according to the three-value / two-value conversion format shown in Table 1, it is converted into the binary e-bit data e of 12.15 [MHz].

In the conversion format shown in Table 1, 3-level 2-baud data can represent 9 levels of information from "22" to "00", and 2-level 3-bit data can be "111".
Eight levels of information up to "000" can be represented. Therefore, when converting 3-level 2-baud data to 2-level 3-bit data, 3-level 2-baud 1 that is not used
There are two levels. This level is called "erasure level", and the conversion error to the binary data caused by demodulating the "erasure level" in the amplitude discriminator (4) is called "erasure error". In Table 1, the “disappearance level” is “11”.

If the "disappearance level" is detected by noise in the transmission system or jitter in the VTR, etc., no matter how the binary 3-bit data corresponding to the "disappearance level" is set, 1 bit or more is set. There is a high probability that a conversion error of will occur.

[Problems to be Solved by the Invention] Since the conventional three-value / two-value conversion device is configured as described above, when the "erasure level" is demodulated, a conversion error of one bit or more occurs, There is a problem that the audio cannot be reproduced faithfully when the error rate increases.

The present invention has been made to solve the above problems, and when the "erasure level" is demodulated, the original correct data can be estimated and the conversion error can be suppressed to a low value of 3 / The purpose is to obtain a binary converter.

[Means for Solving the Problem] A three-value / two-value conversion device according to the present invention discriminates the value of input data converted into a binary N-bit code, and has a three-value level of "2""1". Corresponding to a means for converting into a binary 2-bit code indicating which category of "0" belongs, a serial-parallel conversion means for outputting the converted code in two parallels, and each of the two parallel codes. The output of the other serial-parallel conversion means for outputting the input data in parallel in two and the output of the other serial-parallel conversion means are compared, and 2 is output according to the magnitude relationship between them.
The first determining means for outputting the determination data of the value code and the output of the other serial-parallel converting means are added, and it is determined whether the average value is larger or smaller than 1/2 of the maximum addition value. Second determination means for outputting determination data of a binary code corresponding to
The output of the serial / parallel conversion means is converted into a three-valued and two-baud code, and further converted into a two-valued and three-bit coded three-valued / 2
Value conversion means, and when the output of the serial-parallel conversion means is the disappearance level corresponding to the three-valued level "1""1", based on the outputs of the first and second determination means. It is characterized in that an error in the code of the three-valued and two-baud in the three-valued / two-valued conversion means is judged and corrected, and a binary three-bit code corresponding to the correction is output.

[Operation] When the erasure level is demodulated, the first and second deciding means of the present invention output a decision result capable of estimating the correct ternary 2-baud data of the erasure level. Ternary
Since the / binary conversion means converts the binary data into 3-bit data based on the result of this judgment, it is possible to reduce the occurrence of the erasure error.

[Embodiment of the Invention] An embodiment of the present invention will be described below.

FIG. 1 is a block circuit diagram of this embodiment, and the same reference numerals as those in FIG. 3 indicate the same or corresponding portions, and the explanation thereof will be omitted.

In the figure, (15) is a serial-parallel converter, which outputs the binary data of 8 bits serial data c output from the switch (8),
8 for each set of audio data
The bit parallel data f and g are output. (16)
Is a comparator which constitutes the first judging means, compares the values of the parallel data f and g, and when f ≧ g, “1”,
When f <g, the first determination data h of "0" is output. (17) is an adder which constitutes the second judging means,
The parallel data f and g are added, and the most significant bit (MSB) of the added value f + g is output as the second determination data MSB.
The serial-parallel converter (15) to the adder (17) constitute an erasure level determination section (18). (19) is a ternary / binary converter. When data d1 and d2 other than the erasure level "11" are input, the ternary / binary conversion format of Table 1 When the data is converted into data and the data d1 and d2 of the erasure level “11” are input, the erasure level determination unit (1
Depending on the combination of the first judgment data h and the second judgment data MSB output from 8)
According to the value conversion format, the data is converted into binary and 3-bit data e.

Next, the operation will be described. The 8-bit data a input to the input terminal (1) is four continuous data a0, a by the shift register (5) operating at 16.2 [MHz].
1, a2 and invalid data are simultaneously taken out, and three data a0, a1, a2 excluding invalid data are output to the latch (6). The latch (6) simultaneously latches the three data a0, a1 and a2 into three parallel data and outputs it to the switch (8). The switch (8) is switched at 12.15 [MHz],
1 of 3 parallel data a0, a1, a2 input from the latch (6)
2.15 [MHz] serial data c converted to comparator (2),
(3) and the serial / parallel converter (15). 8-bit serial data c of this sampling frequency 12.15 [MHz]
Is compared with the first judgment value p by the comparator (2) and with the second judgment value q by the comparator (3), and demodulated into binary 2-bit data d. This data d is input to the three-value / two-value converter (19) as two parallel data d1 and d2 for each set of data constituting the audio data in the serial-parallel converter (11). The three-value / two-value converter (19) uses the input data “d1, d2”.
If is not disappearance level “11”, follow Table 1 to 3
It is converted into bit binary data e and output.

On the other hand, the serial data c output from the switch (8)
Is input to the comparator (16) as 2 parallel data f, g for each set of data that constitutes the voice data in the serial-parallel converter (15), and the upper digit data ( Hereinafter, the size of the value of the lower digit (hereinafter referred to as “upper data”) f and the value of the lower digit data (hereinafter referred to as “lower data”) g are compared, and if f ≧ g, the value is “1”; The first determination output h is output.

Also, the adder (17) is configured to store the upper data f and the lower data g.
The MSB of the added value of and is output as the second determination data.
As shown in Table 2, the MSB of the added value f + g is 1/2 of the maximum addition value (511 in this example) (hereinafter "intermediate value")
It indicates whether it is above or below, and the added value f + g
It also has information about whether the average value obtained by dividing by 2 is equal to or greater than the intermediate value or less. That is, the MSB is Becomes

When the loss level “11” is demodulated, the high-order data f
If either one of the lower data g and the lower data g is erroneously demodulated to “1” and the upper data f is erroneously demodulated, “21” shown in FIG. , And “01” shown in FIG. 2B is demodulated to “11”. Further, when the lower data g is erroneously demodulated, "12" shown in FIG. 2 (c) becomes "11".
In addition, "10" shown in FIG. 2 (d) is erroneously demodulated to "11". In the case of FIG. 2 (a), since f> g, the judgment output of the comparator (16) is "1", and the MSB of the output of the adder (17) is So it is "1". The three-value / two-value converter (19) that has received the first and second determination data “1” and “1” is shown in Table 3
According to the conversion format of, the binary data 3 bit data "010" corresponding to the binary data 3 21 "21" is output.

Table 3 shows ternary 2-baud data and binary values for the combination of the first judgment output h and the second judgment output MSB of the erasure level judgment unit (18) when the erasure level "11" is demodulated. It is a table | surface which shows the conversion format of 3-bit data.

[Effects of the Invention] As described above, the three-value / two-value conversion device according to the present invention is
When the erasure level is demodulated, the erasure level determination unit makes a determination to estimate the correct data of the erasure level, and based on the result of the determination, the data is converted into binary and 3-bit data. There is an effect that a three-value / two-value conversion device that can be suppressed to a low value can be obtained.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of data combination when an erasure level is demodulated, and FIG. 3 is a block diagram of a conventional three-value / two-value conversion device. FIG. 4 is a circuit diagram, FIG. 4 is a diagram showing a data string input to the resample unit, and FIG. 5 is a diagram showing a relation between the decimal number of the input data and the ternary level and the discriminant values p and q in the amplitude discriminating unit. is there. (2), (3), (16) ... comparator, (4) ... amplitude discrimination section, (5) ... shift register, (6) ... latch,
(8) …… Switch, (10) …… Resample part, (1
1), (15) …… serial-parallel converter, (12), (19) …… 3
Value / two-value converter, (13) …… Tri-value / two-value converter, (17) ……
Adder, (18) ... Disappearance level determination unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiro Omura 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the broadcasting technology laboratory of the Japan Broadcasting Corporation (56) Reference JP-A-62-172874 (JP, A) JP JP-A-60-38955 (JP, A) JP-A-64-41347 (JP, A) JP-A-61-193542 (JP, A) JP-A-60-125042 (JP, A)

Claims (1)

(57) [Claims] 1. A value of input data that has been converted into a binary N-bit code is discriminated to determine a ternary level of "2", "1", "0".
Means for converting into a binary 2-bit code indicating which of the two belongs, serial-parallel conversion means for outputting the converted code in two parallel, and the input corresponding to each code in the two parallels. A first determination unit that compares the output of another serial-parallel conversion unit that outputs data in two parallels with the output of the other serial-parallel conversion unit and that outputs the determination data of the binary code corresponding to the magnitude relationship between them. And the outputs of the other serial-parallel conversion means are added, it is determined whether the average value is larger or smaller than 1/2 of the maximum addition value, and binary code determination data corresponding to the result is output. The above-mentioned serial / parallel conversion means is provided with a two-level judgment means and a three-value / two-value conversion means capable of converting the output of the serial-parallel conversion means into a three-value two-baud code and further converting it into a two-value three-bit code. The output of the conversion means is “1” or “1” of the above three-value level.
When the disappearance level corresponds to
On the basis of the output of the determination means of (1), the error of the code of the three-valued and two-baud in the three-valued / two-valued conversion means is determined and corrected, and the binary three-bit code corresponding to the correction is output. A three-value / two-value conversion device characterized by: