JP2681400B2 - Three-value / two-value converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a ternary value used to convert ternary 2-baud data into binary 3-bit data in a MUSE audio demodulation circuit, for example. / Binary conversion device.

[Prior Art] Independent data (hereinafter, referred to as "independent data") transmitted by MUSE type voice or other voice channels of high-vision transmission type
As a method of multiplexing "voice data", "voice / independent data multiplexing system" discussed in the document entitled "Development of MUSE system" in NHK Technical Research Vol. 39 No. 2 (pages 90 to 92). , And "Voice Baseband Multiplexing System" described in JP-A-62-172874.

In this system, the bit rate is low in the modulation circuit on the transmission side.
1.35 [M bit / s] binary NRZ coded voice / independent data
Time axis compression to 8.225 [M bit / s] data, then 2
The baud rate can be increased by converting the 3-value NRZ code to the 3-value NRZ code.
12.15 [M Baud / s] (Sampling frequency 12.15 [MH
z]) of the three-valued NRZ code, and then the three-valued
NRZ code data is converted to data with the same sampling frequency of 16.2 [MHz] as the MUSE format video signal, and is time-axis compression multiplexed during the vertical blanking period of the video signal and transmitted.
The demodulation circuit on the receiving side receives this data, resamples it with a digital filter, converts it to 12.15 [MHz] data, and then uses an amplitude discriminator to determine the baud rate.
Converted to 12.15 [M Baud / s] ternary NRZ code data, and then convert this ternary NRZ code data to bit rate 18.225.
This is a method of converting to [M bit / s] binary NRZ code data and then time-axis expanding to demodulate to 1.35 [M bit / s] binary NRZ code voice / independent data.

FIG. 6 shows an amplitude discrimination section, a resample section and a ternary value / 2 of a voice demodulation circuit disclosed in Japanese Patent Laid-Open No. 62-172874.
It is a block circuit diagram which shows the structure of a value conversion part. In the figure, (1) is the input terminal, 16.2 [MHz] binary 8 bits 3
Value NRZ coded voice / independent data a (hereinafter referred to as “data a”) is input. (2) is a first comparator, which is a value of the input data a and a first judgment value p set to a predetermined value.
(178 in this example) is compared, and a signal of "1" or "0" is output based on the comparison result. (3)
Is a second comparator, which compares the value of the input data a with the second determination value q (78 in this example), and based on the comparison result, the value of "1" or "0" is compared. Amplitude discrimination that outputs a signal and demodulates binary 8-bit data a by comparators (2) and (3) into binary 2-bit ternary NRZ code data b (hereinafter referred to as "data b") Configure the vessel (4).
(5) is a shift register, which receives data b.
It is driven by the clock of [MHz]. (6) is a latch,
The output signal of the shift register (5) is input, and 16.2 [MH
It is driven by the output clock of the quaternary counter (7) which receives the clock z] as an input. (8) is a switch, which receives the output signal of the latch (6) and is driven by the output clock of the ternary counter (9) which receives the clock of 12.15 [MHz], and shift registers (5) to ternary counter. In (9), the resample unit (10) for discarding the invalid data of the data b and converting it to the binary BIT ternary NRZ code data d of 12.15 [MHz] (hereinafter referred to as "data d") is configured. (11)
Is a serial-parallel converter, and outputs the data d output from the input switch (8) as 2 parallel data d1 and d2 for each set of data constituting the audio data. (12) is a three-value / two-value converter composed of, for example, a ROM, which converts the two parallel data d1 and d2 input from the serial-parallel converter (11) to 12.15.
[MHz] Converts to 3-bit binary NRZ coded voice / independent data e. The serial / parallel converter (11) and the three-value / two-value converter (12) constitute a three-value / two-value conversion unit (13). (14) is 3
The output terminal of the value / binary converter (12).

 Next, the operation will be described.

The data rate of the data a input to the input terminal (1) is, as shown in FIG. 7, a clock rate of 16.2 [MHz], and there is invalid data once every four clocks. The value of the input data a, the division of the ternary levels “2”, “1”, and “0” and the first and second determination values p and q have the relationship shown in FIG. The input data a is compared with the comparator (2).
And (3) are compared with the judgment values p and q, respectively, and the comparators (2) and (3) respectively output "1" when p≤a to indicate the ternary level "2". Converted to 2-bit data of "11", and when p>a> q,
"0" and "1" are output and "0" indicating the ternary level "1" is output.
Converted to 2-bit data of "1", output "0", "0" when a≤q, and output "0" indicating ternary level "0".
Convert to 2-bit data b of "0".

This data b is divided into four continuous data by a shift register (5) operating at a clock of 16.2 [MHz], invalid data is removed, and three data are input to the latch (6). It The latch (6) simultaneously latches three pieces of data into three parallel data and outputs it to the next switch (8). The switch (8) is switched by the clock of 12.15 [MHz] and 3 parallel data is 12.15 [MHz].
To serial data. This data d becomes two parallel data d1 and d2 for each set of data constituting the audio data by the serial-parallel converter (11), and the three-value / two-value converter (12).
Then, for example, according to the three-value / two-value conversion format shown in Table 1, it is converted into 12.15 [MHz] binary three-bit data e.

In the conversion format shown in Table 1, 3-level 2-baud data can represent 9 levels of information from "22" to "00", and 2-level 3-bit data can be "111".
Eight levels of information up to "000" can be represented. Therefore, when converting 3-level 2-baud data to 2-level 3-bit data, 3-level 2-baud 1 that is not used
There are two levels. This level is called "erasure level", and the conversion error to the binary data caused by demodulating the "erasure level" in the amplitude discriminator (4) is called "erasure error". In Table 1, the “disappearance level” is “11”.

If the "disappearance level" is detected by noise in the transmission system or jitter in the VTR, etc., no matter how the binary 3-bit data corresponding to the "disappearance level" is set, 1 bit or more is set. There is a high probability that a conversion error of will occur.

[Problems to be Solved by the Invention] Since the conventional three-value / two-value conversion device is configured as described above, when the "erasure level" is demodulated, a conversion error of one bit or more occurs, There is a problem that the audio cannot be reproduced faithfully when the error rate increases.

The present invention has been made to solve the above problems, and when the "erasure level" is demodulated, the original correct data can be estimated and the conversion error can be suppressed low. The purpose is to obtain a binary converter.

[Means for Solving the Problem] A three-value / two-value conversion device according to the present invention discriminates the value of input data converted into a binary N-bit code, and determines “2” or “intermediate value” of three-value level. 1 above "1 below intermediate value"
Corresponding to a means for converting into a binary 2-bit code indicating which category of "0" belongs, a serial-parallel conversion means for outputting the converted code in two parallels, and each of the two parallel codes. For each value of the input data, the distance from the intermediate value of the ternary level is obtained, these are converted into binary parallel codes, and binary code determination data corresponding to the magnitude relationship of each parallel code is output. The serial-parallel conversion means includes a determination means and a three-value / two-value conversion means capable of converting the output of the serial-parallel conversion means into a three-value two-baud code and further converting the output into a binary three-bit code. When the output of is a disappearance level corresponding to "1 above intermediate value" or "1 below intermediate value" of the above-mentioned three-valued level, in the above-mentioned three-value / two-value conversion means based on the output of the judgment means. Correct the error by judging the error of the 3-level 2-baud code. This is characterized in that a binary and 3-bit code corresponding to the correction is output while being corrected.

[Operation] The conversion means in the present invention has the sign of the most significant bit (MSB) of the binary N-bit input data and the value of this input data is ternary level "2", "1", "0". It is discriminated which one of the three divisions it belongs to and converted into binary 2-bit data in combination with a code formed by exclusive OR of the data represented by binary 2-bit. This converted data is
The value of the input data is ternary level "2", "2>1b>"
It indicates which of the four divided categories of “1”, “1>1a> 0”, and “0” belongs to. The serial-parallel conversion means outputs this converted data as 2 parallel data for each set of data that composes 3-level 2-baud data.
The determination means determines which of the values of each input data before conversion of the two parallel data is a value farther from the intermediate value corresponding to the ternary level “1”, and the result is determined. The determination data of the binary code shown is output. The three-value / two-value conversion means converts the data into three-value two-bit data according to a predetermined conversion format based on the combination of the judgment data and the two parallel data. As a result, even when the erasure level is demodulated, it is possible to estimate which of the upper data and the lower data is the demodulated data by mistake from the combination of the two parallel data and the determination data.
It can be demodulated into binary 3-bit data corresponding to correct 3-level 2-baud data.

[Embodiment of the Invention] An embodiment of the present invention will be described below.

FIG. 1 is a block circuit diagram of this embodiment, and the same reference numerals as those in FIG. 6 indicate the same or corresponding portions, and therefore the description thereof will be omitted.

In the figure, (20) is an exclusive OR circuit, to which the output data d of the amplitude discriminator (4) is input, and the serial-parallel converter (11).
The logic signal g is output to. On the other hand, this serial-parallel converter (1
1) is the serial data c output from the switch (8)
MSB of is input. (21) is an exclusive OR circuit, which is composed of seven exclusive OR elements as shown in FIG. 3. One input of each element is a series of 8 bits output from the switch (8). The MSB of data c is input and the other input is 2
The signals from SB to LSB are input and the 7-bit data K is output. (15) is a serial-parallel converter, which outputs a set of data that composes voice data as 7-bit parallel data K1 and K2, respectively. (16) is a comparator, which compares the parallel data K1 and K2 with each other, and outputs the judgment data 1 of "1" when K1≥K2 and "0" when K1 <K2. This exclusive OR circuit (21), serial-parallel converter (15)
Also, the comparator (16) constitutes an erasure level determination section (22). (19) is a three-value / two-value converter, which corresponds to the combination of the two parallel data h1 and h2 input from the serial-parallel converter (11) and the determination data l input from the erasure level determination unit (22). The data is converted into binary and 3-bit data according to the ternary / binary conversion format of Table 5 and Table 6 described later.

 Next, the operation will be described.

The 8-bit data a input to the input terminal (1) is
The continuous 4 data a0, a1, a2 and invalid data are simultaneously taken out by the shift register (5) operating at 16.2 [MHz], and three data a0, a1, a2 other than invalid data are taken out.
Is output to the latch (6). The latch (6) simultaneously latches the three data a0, a1 and a2 into three parallel data and outputs it to the switch (8). Switch (8) is 12.1
Switched at 5 [MHz] and input from the latch (6) 3
The parallel data a0, a1, a2 is converted into the serial data c of 12.15 [MHz] and the comparators (2), (3) and the exclusive OR circuit (21)
To the top bit (hereinafter referred to as "MS
"B") is output to the serial-parallel converter (11). The MSB of this serial data c is, as shown in Table 2 below, information on whether this serial data c is an intermediate value (127.5) or more, or less,
That is, when the MSB is "1", the value is equal to or greater than the intermediate value, and when the MSB is "0", the value is equal to or less than the intermediate value.

On the other hand, the binary 8-bit serial data c input to the amplitude discriminator (4) is compared with the decision level p by the comparator (2) and the decision level q by the comparator (3), and the binary 2 It is demodulated into bit ternary data d (hereinafter referred to as "data d"). This 2-bit data d is the exclusive OR circuit (20).
When the value Dn of the original serial data c of the data d is Dn ≧ P or Dn <q, “0” is output when P> Dn ≧ q, and the data g of “1” is output. The data h obtained by combining this data g with the MSB of the serial data c input from the switch (8) is the serial data c before being converted to the data d as shown in Table 3 and FIG. 4 below. Value Dn of the three-valued levels “2”, “1”, and “0” shown in FIG. It has information indicating which of “2”, “1b”, “1a”, and “0” the value belongs to.

In this table, the intermediate value is (127.5), which corresponds to the ternary level "1". These data MSB and g are converted into 2-parallel data h1 and h2 for each set of data constituting the audio data by the serial-parallel converter (11) to form a 3-value / 2-value converter (1
Entered in 9).

On the other hand, the 8-bit serial data c output to the exclusive OR circuit (21) is the MS of the input data C as shown in FIG.
Controlled by B, 7-bit data K shown in Table 4 below
Is converted to

FIG. 5 is an input / output characteristic diagram of the exclusive OR circuit (21).

The 7-bit data K output from the exclusive OR circuit (21) has information on how far the value of the input data C is from the intermediate value (127.5). That is, when the value of the data K is 127, the data is the closest to the intermediate value, and the smaller the value of the data K, the more distant from the intermediate value.

Next, the data K is input to the comparator (16) as two parallel data K1 and K2 for each set of data constituting the audio data in the serial-parallel converter (15). The comparator (16) compares the value of the upper digit data (hereinafter referred to as “upper data”) K1 and the lower digit data (hereinafter referred to as “lower data”) K2, and when K1 ≧ K2 When “1” K1 <K2, the judgment output 1 of “0” is output.

When the judgment data 1 is "1", it means that the lower data K2 is farther from the intermediate value or the same as the upper data K1, and when it is "0", the higher data K1. Indicates that it is farther from the intermediate value.

Next, Table 5 below shows the conversion format of the three-value / two-value converter (19) when data other than the erasure level "11" is demodulated.

If the erasure level "11" is demodulated, the high-order data K1
If either one of the lower data K2 and the lower data K2 is erroneously demodulated to “1” and the upper data K1 is erroneously demodulated, as shown in FIGS. 2 (a) and 2 (b). ,"twenty one"
Is demodulated to "11", and Fig. 2 (c),
This is a case where "01" is demodulated to "11" as shown in (d). If the lower data K2 is erroneously demodulated,
As shown in Figs. 2 (e) and (f), "12" is replaced with "11".
Also, as shown in FIGS. 2 (g) and 2 (h), "10" is erroneously demodulated as "11" and demodulated. In the case of FIG. 2 (a), the original binary 2-baud data "21" is erroneously demodulated as "1b1b" in the amplitude discriminator (4), and from the ternary level "1". Since the upper data K1 has a larger distance, K1 <K2, and the determination output 1 of the comparator (16) becomes “0”.

The three-value / two-value converter (19) receives the judgment output l and corrects the upper data h1 to the three-value level "2". The bit data “010” is output. Table 6 below shows the disappearance level "11".
6 is a table showing a conversion format in a three-value / two-value converter (19) when is demodulated.

[Effects of the Invention] As described above, the three-value / two-value conversion device according to the present invention is
If the input data of binary N bit is
It is converted to binary 2-bit data indicating which of the four levels of "2", "1 above intermediate value", "1 below intermediate value" and "0" of the ternary level, and ternary value Determine which of the values of the original input data demodulated into the upper data and the lower data that compose the 2-baud data is more distant from the intermediate value, and obtain the binary code determination data. , If the erasure level is demodulated based on this judgment data, of the upper data and the lower data,
Determine which is erroneously demodulated and correct it.
Since it is configured to convert to bit data, there is an effect that a three-value / two-value conversion device capable of suppressing the erasure error to be low can be obtained.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of data combination when an erasure level is demodulated, and FIG. 3 is an exclusive OR circuit of the embodiment of FIG. (twenty one)
A block circuit of one configuration example, FIG. 4 shows a ternary level "1".
FIG. 5 is a diagram showing divisions “1a” and “1b” of the values of the serial data c demodulated in FIG. 5, FIG. 5 is an input / output characteristic diagram of the exclusive OR circuit (21) of this embodiment, and FIG. FIG. 7 is a block circuit diagram of the value / two-value converter, FIG. 7 is a diagram showing a data string input to the resampling unit, and FIG. 8 is a diagram showing the input data in the amplitude discriminating unit.
It is a figure which shows the relationship between a base number, a ternary level, and discriminating values p and q. (2), (3), (16) ... comparator, (4) ... amplitude discrimination section, (5) ... shift register, (6) ... latch,
(8) …… Switch, (10) …… Resample part, (1
1), (15) …… Serial-parallel converter, (13) …… 3-value / 2-value converter, (19) …… 3-value / 2-value converter, (20), (21) ……
Exclusive-OR circuit, (22) ... Disappearance level determination unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiro Omura 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the broadcasting technology laboratory of the Japan Broadcasting Corporation (56) Reference JP-A-62-172874 (JP, A) JP JP-A-60-38955 (JP, A) JP-A-64-41347 (JP, A) JP-A-61-193542 (JP, A) JP-A-60-125042 (JP, A)

Claims (1)

(57) [Claims] 1. A value of input data that has been converted into a binary N-bit code is discriminated to determine which of three levels "2", "1 above intermediate value", "1 below intermediate value" and "0". Means for converting into a binary 2-bit code indicating whether it belongs to a section, serial-parallel conversion means for outputting the converted code in parallel to two, and each of the input data corresponding to each of the two parallel codes. With respect to the values, the distance from the intermediate value of the ternary level is obtained, the values are converted into binary parallel codes, and the binary code judgment data corresponding to the magnitude relationship of each parallel code is output, and the above-mentioned directing means. The output of the parallel conversion means is converted into a three-value two-baud code, and further, a three-value / two-value conversion means capable of converting it into a binary three-bit code is provided. "1 above intermediate value" or "1 below intermediate value" of level When the erasure level is equivalent, the error in the ternary / two-baud code in the ternary / two-value conversion means is determined and corrected based on the output of the deciding means, and the binary / three bits corresponding to the correction. A three-value / two-value conversion device characterized by outputting the code of.