JPH03171388A - Information card - Google Patents

Abstract

PURPOSE:To surely read information data at an information card by storing the information data constituted of plural unit block data. CONSTITUTION:At the information card 4, the information data S1 stored in an information memory 11 is constituted of plural unit block data including respectively card number data, block data, block number data, and error detection code data. Then, the information data S1 is stored as being blocked into plural unit block data. Thus, probability that each unit block data is interrupted at a null point is decreased, and besides, even if the unit block data is interrupted at the null point, the information data after the next unit block data having returned to be normal is transmitted correctly.

Description

[Detailed Description of the Invention] The present invention will be explained in the following order. A. Industrial field of application B. Overview of the invention C. Prior art (FIGS. 21 and 22) D. Problems to be solved by the invention E. Means for solving the problems (FIGS. 1 to 2) ) F action G embodiment (G1) Overall structure of information reading device (Figs. 1 to 5) (
G2) Pulling the PLL circuit section into a certain amount of information data signal (
(Figures 6 to 8) (G3) Structure of PLL circuit section (Figures 9 to 15) (G4) Blocking of information data (Figures 16 to 18)
(G5) Coordination of block information data (Figures 19 and 2)
(Figure 0) (G6) Other Embodiments H Effects of the Invention A Industrial Application Field The present invention relates to information cards 1-. , Special C allows information data to be read more reliably.

B Overview of the Invention The present invention (,j,, By storing information data composed of a plurality of unit blocks of data in an information card, the information data can be reliably read.

C. Conventional Technology Conventional 1r) As an information card reading device for reading information data from an information card consisting of a card, as shown in FIG. The response information signal W2 generated in the response request signal generation circuit 2 of the information reading device 1 is sent from the transmitting antenna 3 to the information card 4, and is returned from the information card 4. By receiving the product and answer signal processing circuit 6 through the receiving antenna 5, the information card d can be used as a punishment for leaving the gate, for example. It is being considered to construct an information card reading system that can check people who enter and leave the gate by stealth, and cargo that is attached using the information card 4 as a tag.

The information power and information that can be applied to such an information card reading system.
The card 4 includes a die ball antenna 4B attached to form a part of a wiring pattern on a substrate 4A, and an information signal generating circuit 4C having an integrated circuit (IC) structure that forms an information signal. By connecting the power supply battery 4D with the wiring pattern 4E and changing the impedance at the feed point of the die ball antenna 4B according to the information signal generated in the information signal generation circuit 4C, the information information reader 1 can be connected to the power supply battery 4D by the wiring pattern 4E. By changing the reflectance for the carrier waves emitted by the request signals Wl and L7, the reflected waves are returned as the response information signal W2.
It has been proposed (Japanese Patent Application No. 63-62925). , the information generating circuit 4C has an electrical circuit structure as shown in FIG. is read out by an address signal S3 of an address counter 13 which performs a counting operation in response to a clock signal S2 of a clock oscillation circuit 12, and is supplied to a variable impedance circuit 14 made of, for example, a field effect transistor. The variable impedance circuit 14 is connected between the pair of feed point terminals T1 and T2 of the die ball antenna 4B, and thus the field effect transistor is turned on or off when the information data S1 becomes logic "1" or logic rQJ. Accordingly, the impedance at the feed point of the die ball antenna 4B connected to the feed point terminals T1 and T2 is variably controlled, and thus the reflectance for the response request inertia W1 incident on the die ball antenna 4B is variably controlled. ing.

A hot source battery 4D is connected between the ground side feed point terminal 1゛l and the ii source terminal T3 of the information signal generation circuit 4C, thereby constantly variable control of the impedance at the feed point of the die ball antenna 4B based on the information data S1. It is done in such a way that it can be done continuously.

A unique ID code is assigned to the information card 4 in the information memory 11, so that the information reading device iti can read out the information data held by the information card 4 when the ID code is identified. Problems to be solved by the invention D By the way, the information card 4 to the receiving antenna 5 of
The signal level of the response information signal W2 that arrives at the time is actually very weak, and moreover, the data transmission rate and phase of the response information signal W2 vary greatly depending on the operating conditions of the information card 4.

Incidentally, the data transmission rate of the response information signal W2 is determined according to the oscillation frequency dispersion in the clock oscillation circuit 12 of the information signal generation circuit 4C, and the oscillation frequency varies from one information card 4 to another due to variations in IC manufacturing or from the 1i source. In addition to variations due to variations in voltage, if the ambient temperature of the information card 4 changes, it is unavoidable that the temperature will fluctuate greatly (for example, by about 3 to 10 times).

In particular, the clock oscillation circuit 12 that can be installed in the information card 4 tends to be simple and small in order to adapt to the miniaturization of the information card 4, and in practice, according to this tendency, it is not affected by the ambient temperature. If a simple CR oscillator structure is used, it is impossible to avoid significant fluctuations in the oscillation frequency.

In addition to this, external noise arrives at the receiving antenna 5 at a much higher signal level than the signal level of the response information signal W2. That is, as external noises, for example, the response request signal W1 sent from the transmitting antenna 3 directly arrives at the receiving antenna 5, and the response request signal Wl is reflected from a wall etc. around the information card 4 and arrives at the receiving antenna 5. response request signal W1 sent from another information reading device 1 when multiple information reading devices 1 are installed together.
There are some that occur as a beat between the response request signal W1 from the other information reading device 1 and its own response request signal W1, and the signal level of these noises is actually It is inevitable that the response request signal W2 will be significantly higher than the response request signal W2 obtained as a reflected wave from the information card 4.

In the conventional information card 4 under such severe noise conditions, when transmitting the information data stored in the information memory 11, a method is used in which the information data is transmitted at one time (for example, Patent application 1986-246205
issue). However, with this method, if a phenomenon occurs in which the carrier wave signal is actually interrupted while information data is being transmitted, the transmission of subsequent information data will continue until the end, and then the first data of the information data will be retransmitted. This has the disadvantage that valid information data cannot be sent again until the timing when the transmission starts. The present invention has been made in consideration of the above points, and even if a part of the information data stored in the information card becomes untransferable, the remaining data can be transmitted as valid information data. The purpose of this paper is to propose an information card that has the following features.

? Means for Solving the Problems In order to solve the problems, the present invention transmits the information data S1 stored in the information memory l1 to the outside by a carrier wave, and causes the information reading device 1 to receive the carrier wave, thereby transmitting the information. In the information card configured to read data S1, the information data S1 stored in the information memory 11 are card number data DNO, card number data DNO,
Block data DATA■~DATA■, block number data DINI~D■4 and error detection code data DC,
lc, ~D It is composed of a plurality of unit block data BLK1 to BLK4 including CIIC4, and each unit block data BLKI to BLK4 is sequentially transmitted one by one. When storing F action information data in the information memory 11, the entire
If the information data is stored as a set of information data, for example, if a so-called discontinuous phenomenon occurs repeatedly, such as when the carrier wave drops to a value of O or its vicinity at a null point, all the data will be stored during the timing at which the null point occurs. There is a risk that the information data may not be sent completely (because the amount of information data as a whole is large). In contrast, in the present invention, information data is stored in blocks in a plurality of unit block data BLKI to BLK4, so that each unit block data BLKI
~The probability that BLK4 is interrupted at the null point can be further reduced, and even if the unit block data BLKI~
Even if one of the BLK4 blocks is interrupted at a null point, the information data after the next unit block data that has returned to normal can be correctly transmitted.

In this way, the information data stored in the information card in advance can be read efficiently and reliably as a whole. Embodiment Embodiment Embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) In FIG. 1, which shows the overall structure of the information reading device or parts corresponding to those in FIG. A response information signal W2 returned based on the signal W1 is processed in a response signal processing circuit 6 having first and second series response signal acquisition circuits 21A and 21B.

In the case of this embodiment, the response request signal generation circuit 2 uses the voltage controlled oscillation route 23 based on the oscillation output of the crystal oscillation circuit 22.
, an amplifier circuit 24, a frequency divider circuit 25, and a phase comparator circuit 26. A phase-locked loop (p With amplification j~, the increased output S2 is sent out from the transmitting antenna 3 as a response request signal W1.

In the case of this embodiment, the information input unit 4 converts the transmission information data of the information memory 11 into a data encoder circuit, as shown in FIG. At step 16, predetermined management information is added to the signal, and the signal is biphasically modulated and supplied to the variable impedance circuit 14 as an information data signal S6.

As a result, the encode circuit 16 outputs a logic "1" by rising to a high signal 1 level during the period IT.
By falling to a low signal l/bell for a period 2T, logic "0" data is formed and sent as the information data signal S6.

When adding {1 to the management information, the data encode circuit 16 stops the address counting operation of the address counter 13 via the address/counter control circuit 17.

The response signal processing circuit 6 receives the response information signal W2 returned from the information card 4 at the receiving antenna 5, and converts the received signal Sll into first and second series response signals via the receiving amplifier circuits 3LA and 31B. Intake circuits 21A and 21B
Mixing circuits 33A and 33t3 are supplied.

The mixed Jql paths 33A and 33B each have a phase shift 1 obtained by shifting the phase of the enhanced output S2 of the response required jξ signal generation circuit 2 by a predetermined phase shift amount in the same paths 32A and 32B, respectively.・Output S13
A and S13B are obtained, mixed same path 33A and 33B
obtain mixed outputs S14A and S14B by multiplying the phase shift outputs S13A and S13B by the received enhancement signal S12, respectively.

Here, the phase shift circuit 32A has a phase shift 1 output S1
As 3A, the following formula, S 1 3 A= K+ASinωt ・
...- (1), the reference phase signal having the carrier angular frequency 0) of the response request signal W1 is sent out, whereas the phase shift circuit 32B is based on the following equation, S 1 3 B = K . Ilcosωt (2) As shown in (2), a phase shift output 313B with a phase iv<90° shift 1 is sent out with respect to the phase shift 1 output S 1 3A.

In contrast to this, the received amplified signal S12 is calculated by the following formula S 1 2=
K. sin(ω+α)t − (3), the phase deviation is equal to the phase shift angular frequency α corresponding to the distance G between the information reading device 1 and the information card 4 with respect to the carrier wave angular frequency O). It is possible to express it as a signal.

The mixing circuits 33A and 33B perform equations (1) and (3) respectively for the received amplified signal 312 expressed by equation (3).
2) Phase shift outputs S13A and S expressed by equations
It consists of a multiplier circuit that multiplies l3B, and thereby the following equation is obtained from the mixing circuits 33A and 33B: S14A - S13A - 312 "" K + A! fin/J) t. I<χ sin
(ω+α) t Z ・・・・・・ (4) SL4B =SL3B S1 2 冨KIICOSωt }(zsin (ω+α〉t Z ・・・・・・) (5) The signal strength of the phase shift amount α is and a signal having an angular frequency 2ω that is twice the carrier angular frequency ω. Mixed outputs S14A and SL4B are obtained. These mixed outputs S14A and S]4B are given to low-pass filters 34A and 34B to convert the carrier wave The signal power of the angular frequency 2ω is removed, and thus filter outputs S15A and S15B expressed by the following equations 2 are supplied to high-pass filters 36A and 36B through amplifier circuits 35A and 35B.

Filter output S expressed by equations (6) and (7)
As shown in FIG. 3, when the phase αt changes with the passage of time t, the signal levels of the filter output S15A and S15B are as follows: As shown in FIG.
2, 5π/2..., it becomes O (this signal level sets the point of rQJ as the null point (null pai
nt)), whereas the phase αt is α1-0, π,
It reaches its maximum value when it reaches 2π.

On the other hand, the filter output 315B is the filter output S
15A is the phase of the null point, that is, αt - π/2,
The signal level reaches its maximum value when it becomes 3π/2, 5π/2, etc., whereas the phase at which the filter output S15A reaches its maximum value, that is, α1-0, π, 2π, .
. . exhibits a change that becomes a null point.

In this way, since the filter outputs S15A and S15B exhibit complementary changes, the filter outputs S15A and S15B exhibit complementary changes.
If the filter output with the higher signal level is selected from among 15B, the response signal can be processed as a valid received signal in a state where the response request compensation code W2 does not reach the null point or a low signal level in the vicinity at any time. It can be incorporated into the circuit 6.

High bass filters 36A and 36B have filter output S1
Removes disturbance noise from DC to several (kHz) included in 5A and S15B. Incidentally, disturbance noise consisting of DC commands actually occurs when the response request signal Wl sent from the transmitting antenna 3 of the information reading device 1 is reflected by a stationary reflecting object (for example, a wall) and reaches the receiving antenna 5. arise. Further, disturbance noise of DC to several (k I{z) is generated when the information card 4 is moved. Thus, the filter outputs Sl of high-pass filters 36A and 36B
Disturbance noise generated in these low frequency ranges is removed from SL6A and SL6B, and the filter output is sent to a low-pass filter 38A via amplifier circuits 37A and 37B.
and 38B. The low-pass filters 38A and 38B are analog/
When performing analog/digital conversion processing at the sampling frequency f in the digital conversion circuits 40A and 40B, frequencies higher than the Nyquist frequency are removed to prevent aliasing noise. By removing a certain portion of the carrier frequency from FIG. 5(A)), it is possible to detect information data signal components S17A and S17B as shown in FIG. 4(B). The analog/digital conversion circuits 40A and 40B convert the information data signals S17A and S17B amplified by the amplifier circuits 39A and 39B into 8-bit digital data 518Δ and S18B, which are passed as shown in FIG. Band. 2T from the information data signals S17A and S17B by passing through the digital bandpass filter 41A exhibiting a frequency characteristic of 1.
Filter outputs S19A and S19B are obtained by extracting period data Dt and IT period data DIT, and these filter outputs Si9A and 319B are supplied to zero-cross detection circuits 42A and 42B.

Thus, the zero cross detection circuits 42A and 42B detect the information data signals S17A and S as shown in FIG. 4(C).
2T and IT period data rllllzt included in 17B
And when D+t crosses the zero point, "+1
” level or “-1” level of information data D
Information data signals S2OA and 320B made of ATA are sent out.

Here, ``analog/digital conversion circuits 40A and 40
The sampling time of B, the operating clock of the digital bandpass filters 41A and 41B, and the timing of the Z1 cross detection point of the zero cross detection circuits 42A and 42B are determined by the P'LL output obtained from the PT, ■, and circuit sections Fuku 3A and 43B. The pulses S21A and 321B control the PLL circuit sections 43A and 43B so that even if the frequency of the information data signals S17A and S17B varies according to the data transmission rate condition of the information card 4, the PLL circuit remains unchanged. The units 43A and 43B are configured to perform PLT operations that follow fluctuations in the frequency.

The PLL circuit sections 43A and 43B are the zerox a detection circuit 4.
A phase comparison signal 32 obtained from information data signals 2OA and 20B of 2A and 42B in phase comparison circuits 44A and 44B and numerically controlled oscillation circuits 45A and 45B.
2B and its phase error signals S23A and 3
23B is converted into feedback data S24A and S24B via digital signal processing circuits 46A and 46B, and the oscillation frequencies of numerically controlled oscillation circuits 45A and 45B are controlled so that phase error signals S23A and S23B become "0".

In this way, the numerically controlled oscillator circuits 45A and 45B convert the phases of the phase comparison signals S22A and S22B into the information data signal S.
The oscillation output is controlled to oscillate at a frequency that follows the PLL output pulses S2 1A and 321B, and is sent to the data decoding circuits 50A and 50B via the phase comparator circuits 44A and 44B. The data is supplied as data summation signals S25A and S25B.

The data decoding circuits 50A and 50B decode the data encoded in the information card 4, and after reading the header data attached to the transmitted data, demodulate the pie-phase modulated information data. Error detection code (in this case CRC: cyclic
The presence or absence of a transmission error is evaluated using a redundancy check code (using a redundancy check code).

Decode output S of data decode circuits 50A and 50B
3OA and S308 are supplied to the central processing unit i-(CPtJ) 5, which constitutes a part of the data processing unit 21C.
CPU 5 1 receives the supplied decode outputs S30A and S
30B of data is stored in RAM (random accesses).
While using the work memory 52 of ROM (read only memory) structure as needed,
w+emory) After data processing is performed based on the program stored in the program memory 53,
It is sent out as transmission data S31 via the data transfer circuit 54, and is sent out as display data 332 via the display input/output circuit 55.

In the configuration shown in FIG.
1, the weak response information signal W2
When the response signal is returned, it is transferred to the phase shift circuit 3 of the first series and second series response signal acquisition circuits 21A and 21B.
4A, mixing circuit 33A, and phase shift [il! 34B
, the mixed outputs S14A and S14B are converted into mixed outputs S14A and S14B whose phases are shifted by 90 degrees from each other in the mixing circuit 33B, and are processed thereafter. In this way, even if the distance between the information card 4 and the information reading device 1 is exactly at or near the null point, the first series response signal acquisition circuit can utilize the phase difference between the mixed outputs S14A and S14B. 21A or the second series response signal acquisition circuit 21B, it is possible to always acquire a received signal at a signal processing level sufficient for practical signal processing, and as a result, the response information signal W can be stably received.
2 can be received. Therefore, in this embodiment, firstly, an analog/digital conversion circuit 40A, a digital bandpass filter 41A, a zero cross detection circuit 42A, and a PLL
Circuit section 43A1 and analog/digital conversion circuit 4
0B, digital bandpass filter 41B2, zero cross detection circuit 42B, and PLL circuit section 43B structure allows the PLL circuit sections 43A and 43B to operate in a short time by a simple structure using the floating state of the oscillation frequency obtained during free running. During this period, the PLL circuit section 43A can be locked to the frequency of the information data signal. Secondly, in this embodiment, the PLL circuit sections 43A and 43B perform a high-speed locking operation, so a structure is used in which the PLL tracking operation is even faster.

Thirdly, in this embodiment, in consideration of the fact that the data transmission rate in the information card 4 fluctuates significantly, a structure is adopted in which transmission data is divided into blocks and transmitted in order to effectively avoid the influence. I have something. Fourthly, in this embodiment, the CPU 51 executes processing to ensure that the clock data can be combined.

These characteristic configurations will be explained in detail below. (G2) Introducing the PLL circuit to the information data signal signal As mentioned above, the information card 4 (Fig. 2) uses a CR oscillator configuration as the clock oscillation circuit 12, making the information card 4 compact as a whole. However, in practice, the oscillation frequency of the clock oscillation circuit 12 of the CR oscillator structure may fluctuate by up to 10 times due to changes in the surrounding temperature, and this is a problem that is difficult to understand when using information. IT period data I)+t and 2T period data [) contained in the information data signal portion S17A and S17B that are sent out from the card 4 and therefore the information data signals obtained from the low-pass filters 38A and 38B (FIG. 1)
This means that the frequency of No. 11 may fluctuate by about 10 times. In this way, when the information data signals S17A and S17B having one specific frequency included in the frequency range of 10 times the fluctuation width are obtained from the low-pass filters 38A and 38B, the information data signals S17A and S17B are S17
B is the digital conversion output 318 after being converted into 8-bit serial digital data at the sampling frequency determined by the PLL output pulses S2 1A and 321B in the analog/digital conversion circuits 40A and 40B.
A and 318B are the passbands J of digital bandpass filters 42A and 42B having the frequency characteristics shown in FIG.
The 1T period data DI? and 2T period data DZT are extracted.

The digital bandpass filters 42A and 42B are finite impulse response circuits (FIR,
finite impulse response
), the digital conversion outputs S18A and S18
1st to 8th stage delay circuits 61A to 61 connected in cascade with B
Supply to H.

The first to eighth stage delay circuits 61A to 61H are each constituted by a flip-flop circuit, and the PLL circuit section 43
The PLL output pulse S21A sent from A is used as a clock pulse to convert the digital conversion output S to one clock period at a time.
Each bit of 18A and 318B is shifted while being delayed. 1st stage and 8th stage delay circuits 61A and 61
The delayed outputs of H are added in an adder circuit 62A, weighted by a weighting signal WA in a multiplier circuit 63A, and then given to an adder circuit 64.
stage and the seventh stage delay circuit 61B and ? After the delayed outputs of 1G, 3rd and 6th stage delay circuits 61C and 6iF, and 4th and 5th stage delay circuits 610 and 6l are added in addition circuits 62B, 62C and 62D, respectively. Multiplying circuit 63I363C, G 3 D Nice mouse-picking signal W
I. , 'V'=/CW0 weighted by jIi
Lj is applied to the I calculation circuit 64.

If <j2, the output of the adder circuit 64 is:. is the 7th 1st
ml L. −． ．． As shown, the filter output S19 has a passband J that can be selected with high selectivity for IT and 2T period data D and Dyy.
A and S19B can be obtained.6 In the configuration of FIG.
The passband is located at the frequency position determined by the frequency of 1B. J
By setting δ (FIG. 7), the passband J is therefore IT and the 2'r period data D. 1], 7, the data DI? and D, T between the IT and 2'i''QJI are extracted and the outputs of the filter are set to si9A and S19B. Consultation 42A
and 42B (first section i), thereby maintaining the locked state of P Li and the circuit sections 43A and 43B.

However, in reality, the data transmission rate of the information car F4 depends on the fluctuation of the oscillation frequency of the clock oscillation circuit 12 (Fig. 2).
Therefore, when the response information code W2 is returned from the new information card 4, the passband J is not necessarily j as shown by the solid line in FIG. , T and 2T period data DI! and Dlr frequency.8 If this continues, the PLL circuit section 43A will be able to output the IT and 2T period data DI of the information card 4 currently communicating. The numerically controlled pear oscillation circuits 45A and 45B are allowed to self-oscillate while remaining in the unlocked state, although they may be in the locked state at D and T.

However, the second self-transmitting oscillation state C 7, is actually low bass filter 38A and 3 fl B! :: If the information signals S 1 7 A and S 1 7 B cannot be removed completely (:'.' noise components are present, then this is the digital bandpass filter 41A and 4
1 Ba) AejMMiJ4 transmission C+frJ class detection one route. i2A and 0” 4 2 B Follow-C: P L
P L K, lii@S 4 3 A and (J43
B is acting as if it is trying to add a pseudo phase signal to the noise component, but is this noise component? 'L steady M reception 3 is not possible, so browning P L L circuit section 43A and No. 438 41T and 2T period data D,,
2-pass over the entire range where rubi T) zt' varies? A floating state that makes I'JLJ dizzy (Gonaru,
As a result, when the PLLIiJ path sections 43A and 43l3 are in the free-running oscillation state, the PLL output pulses 21A and 2
As the frequency of 1B fluctuates, the actual -1 pass band J is changed between the currently communicating information power of IT of 4 and 21 of the regular data DI?, as shown by the broken line in FIG.
This results in a scan operation that takes the stiffness into the PLL circuit sections 43A and 43B through the frequency position it of D6 and D6, and thus the IPLL circuit sections 43A and 43B
1T and 2T period data D + y and DIT are pulled into and served by 1 cook + t.
It is maintained as long as the 1I information signal W2 continues to arrive, and as a result, the I and 2T period data Dot of the information card 4 are maintained.
Even if the frequency positions of D and A vary widely, this can be reliably determined by the D and C code Enro 50A.
and 50B to the CPU 51.

Thus, according to Mizoei in Figure 6, the log/digital conversion tunnel 40. A and 40B are Y? An 8-stage delay circuit 6 is used to convert the information data signals Sl7A and 317B into 8-bit serial data.
By providing C to provide 1A to 61H, Fig. 8 (
As shown in A), the filter output S19A warps S19B
{8 B, level is change of bit data f. When this transition occurs, a red, ringing light is generated.
When constructing an i゛pass filter, if we increase the number of stages of the predicate circuit that involves the 0 interposition confusion, the number of stages becomes equal to the current average, l-, and the number of stages? , it is unavoidable that the ringing waveform XI as shown in FIG. 8(B) occurs during the sampling time of two burns, but if the configuration is as shown in FIG. 6, it is possible to prevent the ringing waveform X1 from occurring. It can be done. (G3) Structure of the PLL circuit The PLL circuit sections 43A and 43B (Fig. 1) output the zero cross detection signal S2 of the zero cross detection circuits 42A and 42B.
Based on 0A and S20B, it is configured to perform a lock operation at high speed with respect to the frequency of the information data signal with large frequency variations.

As shown in FIG. 9, zero-cross detection circuits 42A and 42B receive filter outputs S19A and S19B through first and second stage delay circuits 71A and 71B which perform delay operations using PLL output pulses S2 1A and 321B. It has a structure in which the filter outputs S19A and SL9B are input to the comparator circuit 72 as the first comparison input CM1 with a delay of two clock cycles, and the filter outputs S19A and SL9B are directly input to the comparator circuit 72 as the second comparison input SM2.

The comparison circuit 72 has the following equation: CMI>O and CM2>+X→+1 (8) ”, positive value “+
1'' information data signals S2OA and 320B, and the first comparison input CMI is negative and When the second comparison input CM2 is lower than the negative reference value "1X", the numerical value "-1"
” information data signals S20A and 820B are sent out.

In addition, the comparison circuit 72 has first and second comparison inputs C having input conditions other than the input conditions of equations (8) and (9).
When MI and CM2 arrive, they are ignored and the previous values continue to be sent as information data signals S2OA and 320B. The output of the information data signals S2OA and 320B under the conditions of equations (8) and (9) is the first
As shown in FIG. 0 (B), filter outputs S19A and S19 given to zero cross detection circuits 42A and 42B
If B contains a sufficiently large third-order harmonic component, there is a risk that the filter outputs S19A and S19B will be affected by it and cross the zero point. By providing a dead zone in the range of signal levels "r-X" to "+X" in the comparator circuit 72, the incorrect zero cross is not detected. Incidentally, as shown in FIG. 10(A), in an ideal case where a third harmonic is not included, the second comparison input CM2 representing the current signal level of the filter outputs S19A and S19B For filter output S1 two sample periods before
1st comparison input CM representing signal levels of 9A and S19B
I is that if the filter outputs S19A and S19B correctly cross the zero crossing point from a negative signal level to a positive signal level, or from a positive signal level to a negative signal level,
A signal is generated at the timing when the second comparison input CM2 exceeds the positive reference value "+X" or the negative reference value r-X" by obtaining a state that satisfies the conditions of equation (8) or equation (9), respectively. Information data signals S20A and 320B that transition to level "+1" or "-1" can be obtained.

On the other hand, when the first and second comparison inputs CMI and CM2 cross the zero cross point due to the influence of the third harmonic precept, as in the case of FIG. 10(B), the equation (8) Or, because the condition of equation (9) cannot be satisfied, the information data signal S at the timing of the second comparison input CM2.
It is possible to prevent the signal levels of 20A and 320B from changing. Thus, as described above with reference to FIG.
and 42B, as shown in Figure 5,
3rd harmonic power D! There is a risk that x may not be removed sufficiently for practical use, and when the third harmonic D, Although there is a risk of detection,
This fear can be effectively avoided by using the detection speeds 42A and 42B.

Gonoyo Ul: 'LL and Zel': ll Cross Detection Circuit 4
Information data signals 320A and 320B (FIG. 11(A)) obtained from 2A and 42B are . , phase comparison circuit 4
It is given as a counter control signal to the counter circuit 75 (FIG. 9) of 4A and 44B.

Count circuit 75 receives information data signals S2OA and 32
Detection pulse S41 based on 0BID rising and falling
(Fig. 1l(B)) is generated j-, and this detection pulse S41
The predetermined period T. During this period, the counter operation signal S42 (FIG. 11(C)) rising to the logic 'L11 novel is generated, and its rise causes the phase comparison signals S22A and S
22B as numerical system 611 type oscillator circuit 45A and 45B
The number of pulses of the pulse train (FIG. 11(D)) given from TIl is counted during the period TIl.

Here, the count circuit 75 performs phase comparison {K % S 2
The pulses of 2A and S22B are counted up to 8 times at maximum, and when 8 or more pulses arrive, the process returns to counting and counts l=t, [.

(Kabifun 1 - circuit 75 is counter l - operation signal S
42 (Fig. 1l(C)) falls to the logic "0" level and stops counting, the counter l-value becomes "0".
~． ．． The counter 1 signal S43 having the value "r7" is applied to the current value conversion circuit 76.

When the current value conversion circuit 76 receives the numerical data "0" to "7" as the count signal S43, it converts it into the following formula S4 4= ((34 3-4) + 0.5)
...(10) The current value conversion signal 344 is calculated by the conversion formula expressed by
Convert to

In this way, the count signal S43 becomes the numerical value "0", "l", "
2", "3", "4", "5", "6", "7", this is r-7J, r-5", "-3", "11"
, "+1", "+3", "+5j", and "+7".

This current value conversion signal S44 converts the conversion value table TABLE shown in FIG. 12 into a phase error conversion circuit 77.
is input as current value information.

The phase error/conversion circuit 77 converts numerical data "-7j to "+
7” as the change range now {l! The converted signal S44 is converted into numerical data r-15''~r+l according to the way it changes.
5 J into phase error signals S23A and S23B having a change radius of 5 J, and thereby the change range of the data obtained by the count same-path 750 count operation result with a narrow count range (i.e. "0" to "7"). , a significantly wider variation range (i.e. r-15J~
Phase error signals S23A and S2 with "+15,i)
In the eight phase comparator circuits 44A and 44B configured to select the number of conversions to 3B, the thirteenth
If the values of the phase error signals S23A and S23B were "+1" in the previous phase comparison operation as shown in FIG. In the current phase error detection operation, it is given to the phase error conversion circuit 77 as the previous value signal S45.

At this time, the phase error conversion circuit 77 specifies the "+1" column as the previous value in the conversion value table TABLE of FIG.
-3", "-1", "+1", "+3", "+5", "
+7'', the phase error signal S23A corresponds to this.
and the value of 323B is "+9", "-5", "-3", "
1", "+1", "+3", "+5", and "+7".

Therefore, the phase comparison operating range at this time is
5 count signal S43 is "1", "2"...
When the value becomes "7", the current value conversion circuit 76 outputs the current value conversion signal S44 as "-5", "-3", . . . "+7".
”, the phase error conversion circuit 7
7 is the numerical value "
-5'', ``-3J...'' can send a value of ``+7''.

In addition, when the count amount of the count circuit 75 exceeds the maximum count value "7" and returns to the minimum count value "O", the current value conversion circuit 76 converts the count signal 343 into a numerical value "-7". By applying this to the phase error conversion circuit 77 as the current value conversion signal S44, the phase error conversion circuit 77 sends out the numerical value "+9" as phase error signals S23A and S23B.

Thus, the phase comparator circuits 44A and 44B generate a phase error signal S in the range of phase error amount "-5" to "+9" corresponding to the count operation range "0" to "7" of the count circuit 75.
23A and 323B will be sent.

By the way, as a result of such a phase comparison operation, as shown in FIG. 13(B) as phase error signals S23A and 323B, when the numerical value "+9" is held in the previous value holding circuit 78, the next phase is As shown in the previous value "+9" column of the conversion value table TABLE in FIG.
23A and S23B move from "+3" to '+15J centering on the previous value "+9".

In this example, the phase error signals S23A and 323
B is limited to r+15J as its upper limit, and thus, even if the values of the phase error signals S23A and 323B increase thereafter, they are saturated at the upper limit "+15".

On the other hand, as a result of the phase comparison operation in the range of FIG. 13(A), when the numerical value "-5" is held as shown in FIG. 13(C) on the 7th day of the previous value holding circuit, the phase Comparing circuits 44A and 44B respond to phase error signals S23A and 323B when count circuit 75 sends out count signal S43 with count values "0" to "7".
The phase comparison operation is performed in the phase comparison operation range of the numerical value r-134 to "+1".

Furthermore, as a result, the previous value is as shown in Figure 13 (D).
If the numerical value is '-134, then in the subsequent phase comparison operation, the count circuit 75 calculates the count value rQJ~'
When the count signal S43 of 7J is sent out, the phase error signals 323A and 523B correspond to the value r-15.
Move the phase comparison operation range to the range from J to "-7".

In this way, in the phase comparator circuits 44A and 44B, even if the phase comparison result of the same count value is obtained as the count signal S43 of the count circuit 75, the subsequent phase comparison operation will be performed using the same phase as the previous phase operation. By being able to move to the phase comparison operating range centered on the previous value sent out as the error signals S23A and 323B, it is possible to substantially expand the phase comparison range further, and as a result, the phase error signal S23A that can be obtained
In order to avoid discontinuity in the amount of change in and 323B,
A linear change can be produced.

Such a linear change causes the phase error signal S23
Digital signal processing circuit 46A using A and S23B
and numerically controlled oscillator circuits 45A and 45 via 46B.
When B is numerically controlled, unstable operation can be prevented, and thus stable PLL pull-in operation can be realized.

Phase error signals S23A and 323B of comparator circuits 44A and 44B are output to digital signal processing circuits 46A and 46B.
After being given a predetermined weight in the primary weighting circuit 8, the signals are applied to the primary addition circuit 82 and also to the secondary addition circuit 83. Addition output S2 of secondary addition circuit 83
5 is delayed by one sampling period in the secondary delay circuit 84 and then fed back to the secondary addition circuit 83,
As a result, the secondary addition circuit 83 sequentially outputs the phase comparison circuit 44A.
It sends out an addition output S45 representing the total integrated value of the phase error signals S23A and 323B given from the phase error signals S23A and 44B.

The calculation output 345 obtained from the secondary delay circuit 84 is supplied to the primary adder circuit 82 via the secondary adder circuit 85 (7), and thus the current phase comparison operation is executed from the primary adder circuit 82. An added output is obtained by adding the phase error scene of the current phase comparison operation to the total phase error amount of the six phase comparison operations before the phase comparison operation. BL;″.Supplied.

The numerically controlled oscillator circuits 45A and 45B supply feedback data 24A and 24B to the numerically controlled circuit 856, as shown in FIG.
・Generates the numerical control signal S50.

Numerical control signal S50 supplies a 2-bit selection signal ISsO8 to sector 1/actor 86, and also supplies a 5-bit exponent signal 350B to power coefficient circuit 87.

The selector 86 receives the mask clock CLK at the manual end (96-127), and also receives the 172-frequency divided clock CLK obtained by dividing the master clock CLK by 1/2 in the 172-frequency divider circuit 886. r m
(64 to 95) to the manual terminal, and further receives this 172-divided clock CLK. The 174 frequency divided clock CLK. ．． (32～
63) This 174 frequency divided clock C is received at the input terminal.
A 178 frequency divided clock CLK1 obtained by frequency dividing LK4N in a 172 frequency dividing circuit 90 is received at the input end (0 to 31).

The master clock CL thus input to the selector 86
K, 1/2 frequency division clock CI, K, . , 1/4 frequency division clock CLK-a and 1/8 frequency division clock CLK
I, l are selected by selection signal S50A and provided to power coefficient circuit 87 as selection output S51.

The exponentiation circuit 87 calculates 4it! of the 32nd root of 2 as shown in the following equation. x by numerical control circuit 8
The number n to be input from the number signal 350B to be given from 5 (n=o~31) is expressed by the following formula 32 1A
(32 1B)=x" -- (12)? As shown in FIG. S22A and S2
2B, and PLL output pulses S21A and 321
Send as B.

In the structure of FIG. 14, feedback data S24
A and S24B are configured to take values in the range of numbers "O" to "127j," whereas the numerical control circuit 85 sets these values to four ranges, that is, numbers r■, to "127j."
31", "32" to "63", '64J - '95J
, "96" to rl27, +, and sends out phase comparison signals S22A and S22B which are pulse train signals with a frequency f that changes exponentially for each range.

That is, first, when the feedback decoder 24A and 24B are in the first range, that is, the numerical value r~131'', the numerical control circuit 85 sets the selector circuit 86 to the state of selecting the (0=31) input terminal by the selection signal S50A. control,
From this number, the 178 frequency divided clock CLKsm is supplied to the selection output S51 and the exponentiation coefficient circuit 87.

In addition, the numerical control circuit 85 sends a numerical signal 350B that should represent the numerical value n to the exponentiation coefficient circuit 87 in response to the contents of the feedback data S24A and S24B being any of the numerical values "0" to "3l". By giving 178 frequency divided clock CLK. Numerically controlled oscillation is performed by generating a pulse train signal with frequency r, which is expressed by the following formula for frequency f0 of l, f = xIl - fo (13) and using this as phase comparison signals S22A and S22B. Phase comparator circuit 44A from circuits 45A and 45B
and 44B to the count circuit 75 (FIG. 9).

Thus, as shown in FIG. 15, the numerically controlled oscillator circuits 45A and 45■3 have the frequency f of the pulse train signal of the phase comparison signals S22A and S22B in the first range of N=rO to "31". 1f0 to 2f. up to 1
The octave change can be divided into 32 steps (approximately 1.03 times as many steps) and can be changed exponentially. Another numerical control episode! 85 is feedback data S24A
And when the value of S24B becomes a numerical value "32" to "63",
The clock CLK. divided by 174 is selected by the selection signal S50A.
．． is selected and sent to the selection output S51, and the numerical value rQJ to "31" is supplied to the exponent coefficient circuit 87 as the exponent signal 350B.

In this way, the numerically controlled oscillator circuits 45A and 45B have the value N of the feedback data S24A and S24B set to the 15th
As shown in the figure, when it comes to the range of "32" to "63",
By changing the frequency 2f0 of the 1/4 frequency divided clock CLKam in 32 steps represented by the exponent signal S50B, the frequency is increased by one octave, that is, 4f. It is possible to send phase comparison signals S22A and 322B consisting of a pulse train having a frequency of .

Similarly, feedback data S24A and S2
When 4B reaches the third range of the numerical value N-r63J to "95" in FIG. 15, or the fourth range of the numerical value "95" to rl27J, the numerical control circuit 85 The cycle clock CLK or the master clock CLK is selected by the selector 86 and supplied to the power coefficient circuit 87 as a selection output S51, and the number "0" to "31" is set as a power number to the power coefficient circuit 87 as a power number signal 350B. give. As a result, ]/2 frequency division clock C
LKIN or master clock CLK frequency 4f. ,
Or a phase comparator circuit S22A consisting of a pulse train signal that changes exponentially from 8fo to a frequency 8f0 or 16f0 that is one octave higher by 32 steps each.
and 322B are sent out as outputs of numerically controlled oscillation circuits 45A and 45B.

According to the structure of FIG. 14, feedback data S24
By making it possible to generate a pulse train signal with a frequency that changes exponentially when data with a numerical value N that changes linearly as A and S24B arrives,
Even if the frequencies of the information data signals S2OA and 320B applied to the phase comparison circuits 44A and 44B vary greatly, the phase comparison signal S2 can be easily tracked over the entire frequency range of the variation.
2A and S22B can be generated.

Incidentally, when the phase error signals S23A and 323B increase due to a large fluctuation in the frequency of the received information data, the phase comparison signals S22A and S22 increase accordingly.
When B increases exponentially and as a result a fluctuation occurs that causes the phase lock state to be deviated from, the pull-in operation to the phase lock state becomes much stronger and the pull-in speed becomes even higher. (G4) Blocking of information data The information data stored in the information memory 11 of the information card 4 (FIG. 2) is a relatively small predetermined block. It is stored in blocks of unit block data of each amount.
When sending the information data S1 from the information memory 11 to the variable impedance circuit 14, each unit block data is repeatedly read out in a predetermined order.

In this embodiment, the information data in the information memory 11 is stored in four unit blocks BLKI to B, as shown in FIG.
Blocked into LK4, each unit block data is 26
It is designed to have a byte of information.

Unit block data BLKI, BLK2, BLK3 and BLK4 are block data DATA■ for 16 bytes,
D A T A xt, D A T A ** and D
ATA■, and 2-byte block number data Dm. 4+, DuHt% D++Ns and D■
, and 2 bytes of error detection code data D c*c+
, DCl1el, D CICffi, and D elcd are sequentially added, and the block data DATA■, DA
At the beginning of TA■, DATA0, and DATA■, the common car number data DNo of Gbyi・minute is added, which does not represent the card number assigned to the current card.

Thus, each unit block data B i, K 1-B
Each of the LKs 4 is configured to have information such that it can independently transmit information data.

Each unit block data B L K1~ of the information memory 1l
When sending out BLK4 from the information card 4 (Fig. 2), one information memory memory is used as the unit block 1 as shown in Fig. 17.
Kotoku data BI, K 1, BL K 2, B
LK3 and BLK4 are read out in that order and supplied to the data encoding circuit 16. Each unit block data is added with header data H including a security code in the data encoding circuit 16, and then subjected to phase modulation. variable impedance circuit 1,
H, this is sent.

Here, the data encoding circuit 1G inputs each unit block data B L, K1, BLK2, BLK3, and BLK4.
17, the address counter 13's counter 1 operation is temporarily stopped and data H is added via the add I/counter control circuit 17. It is done like this.

As a result, information power 4 is unit block data BLK1, BLK2 to which data H has been added, respectively.
, B i-K 3 and BLK 4 are arranged in that order, and a frame data string FRM for one frame is repeatedly sent out from the continuous die-ball antenna 4B.

According to the structures shown in FIGS. 16 and 17, information data to be transmitted is divided into unit blocks BLK1 to B IK4 each having a relatively small amount of data, and each unit block is By making it possible to transmit transmission information data independently for each data, response information signal W
4 by the information reading device 1, the reading speed and reading accuracy of the information data can be further improved.

Incidentally, when receiving the response information signal W2 in the response signal processing circuit 64, if the signal l/bell of the response information signal W2 is weak, and if the information card d moves, the response information signal W2 71-nome data string F for 17 frames due to reasons such as the possibility of not being able to receive stable
If part of the RM cannot be received or an error occurs in the received information data, 1 RM for 1 person will be
The unit block data BLKI-BLK4 that has been received up to that point in the norm data string FRM cannot be used as meaningful information, so it is discarded, and then the response information signal W2 is sent again after waiting for the arrival of a normal response information signal W2. However, reception can be started from the timing of the first unit block data that can be successfully re-received.

For example, as shown in FIG. 18(A), one frame of frame data string FRM. is made up of first to fourth unit block data BLKI to BLK4. ,FRM,. ．． , F.R.M.
While continuously transmitting FRM.2,..., the m-th frame data string FRM. When the response signal processing circuit 6 cannot receive the second unit block data normally, as shown in FIG. If the number is completed, four unit block data from the third unit block data are transferred to the m-th frame data string FR.
M. It would be a good idea to incorporate it as

On the other hand, as shown in FIG. 18(C), when information data is to be transmitted for each frame data string for one frame, the m-th frame data string FRM. (Fig. 18 (A)), when a state occurs in which normal reception cannot be performed, the next frame data string, that is, rn+
1i-th frame data string FRM. ．． ．． If you do not wait for the arrival of the signal, normal reception will not be possible.

Therefore, according to the configurations shown in FIGS. 16 and 17, the response information signal W2 sent from the information card 4 can be received for each unit block of data, so that information can be read efficiently.

Especially when a microwave with a frequency of about 2.45 (GHz) is applied as a carrier wave, as in the case of this embodiment,
As described above with reference to FIG. 3, it is unavoidable that a so-called null point occurs in which the received signal becomes 0 based on the phase amount α corresponding to the distance between the information card 4 and the information reading device 1. For example, if the information card 4 is moving at a constant speed, each time the information card 4 passes a null point, there is a risk that reception will not be possible. By being able to import the data immediately when normal reception is possible, the information reading operation of the information reading device 1 can be made more efficient and the reading accuracy can be improved. (G5) Block information data processing The response signal processing circuit 6 of the information reading device 1 converts the information data transmitted in blocks into the data decoding circuits 50A and 50B, as described above with reference to FIGS. 16 and 17. When decoded in CPU 5 1
Then, the block data is taken into the data memory MEM (FIG. 19) provided in the work memory 52 through the block data combination processing procedure shown in FIG.

In this case, the data memory MEM has information data memory sections M1, M2, . Old...Mj is 4 unit block data BLKI 1 to BLKI4, BLK2 1 to BLK read as one frame data string FRM
24...BLKj 1 to BLKj4 as data write flags Fil to F14, F21 to F24, respectively.
...Stored in the memory areas labeled Fjl to Fj4, respectively. Unit block data BLKII~BLK
14, BLK2 1~BLK24...BLKj
l~BLKj4 each have the read information card 4.
Card number data BNI, BN2...BNj
and timer data TMi, TM2...TMj are stored, thereby data write flags F11-F14, F21-F24...Fjl-
Together with Fj4, unit block data BLKI 1 to BLK
14, BLK2 1~BLK24...BLKj
1 to BLKj4 are written to format the management data for transmission.

In the block data structure processing procedure (Figure 20), C
After starting the processing procedure at step SPI, PU51 starts the processing procedure from the data memory ME at step SP2.
Management data of M, that is, timer data TMI, TM2
...TMj, data writing flub Fil~F14
, F21-F24...... By initializing FJ1-Fj4, logic "O" data is written.

Thereafter, in step SP3, the CPU 51 determines whether the data gathering permission signal CS is logic "1" or not.
When a negative result is obtained (this means that the data matching permission signal CS is in the state of "cs=rQ" and data matching is prohibited), the CPU 51 returns to step SP2 described above and executes the data matching process. The precept permission signal CS is logical.
1” (this means that the prohibition on data compositing processing has been lifted). In the case of this embodiment, the CPU 5 1 is given a data consolidation permission signal CS from the outside, and its logic level is switched as necessary, so that when CS becomes "0", a newly received unit block is received. data to data memory ME
By writing to M, it is possible to prohibit the merging and also to discard all the data previously written to the data memory MEM.

When a positive result is obtained in step SP3, the CPU 51 moves to step SP4 and determines whether or not the unit block data has been manually input.

If there is an information card 4 currently communicating here, the CPU
51, a block data string FRM as shown in FIG. 17 is sequentially input as a decode output S30A or S30B from a data decoding circuit 50A or 50B.

Therefore, the CPU 5 1 uses each unit block data BLK1~
The determination in step SP4 is executed based on the header data H attached to BLK4.

If a positive result is obtained here, the CPU 5 1 reads each unit block data BLKI to BL in step SP5.
K4 error detection code data D CICI~Dclc4 (
It is determined whether or not there are any errors in the data based on FIG. 16).

If a positive result is obtained here, it will be confirmed that each unit block data H3 1, K1 to BLK4 has been received without error, and the CPU 5 1 will then proceed to step S.
In order to execute the processing from P6 onwards, the uplink unit block data BLK1 to BLK41 are used to perform block data merging processing based on this. On the other hand, when a determination result is obtained in step SP5, the process returns to step SP3 described above without performing the data aggregation process.

C P U 5 1 t. ;J: Card number data DNo from the unit block data currently fetched in step SP6 and card number data BN written in the memory sections M1 to Mj of the data memory MEM.
1 to BNj and selects the memory section that has one loss, and also sets the timer data TMI to T of the selected memory section.
Confirm that Mj is positive.

If a negative result is obtained here, this means that the past predetermined retention time (0.5 (Sec. in this example) ) means that no data has been received during this period, and at this time, the CPU 51 moves to the STEG SP7 and stores the memory of TMj=O (j=1 to j) in the memory section M1=MJ. Determine whether or not there is a department.

The judgment in step SP7 is based on the memory parts M1 to lI4.
．． It means that when a positive result is obtained, CPtJ5I moves to step spsc and stores the corresponding free memory area. With the timer data TMj (j=1 to j) and 17, retention time data "50" is written, and thereby the writing of the received unit block data is stopped.

On the other hand, in step SP7, a negative result, l, (
If obtained, this means that there is no free memory area in the memory parts M1 to Mj, and at this time the CPU
Is 51 the received unit block? Discard the data and return to step SP3 above.

Further, if a positive result is obtained in step SP6, this means that the unit block data BLKI to BL
This means that there is a memory part Mj (J-1 to j) in which 4 is written, and ΔCPIJ5 1 is a steg S.
P87. Next, check the timer data of the memory module.
By writing retention time data "50" to j (j=l-j), the memory area is set in a reserved state for writing the unit block data BLKI to BLK4 that are received intermittently.

When this reserved state is reached, CPU 5 1 is at step SP.
9, the selected memory section Mj (j-1 to j)
, the currently received unit block data BLKj
Block number data D■+ included in (j-1 to 4)
(i=i~4), the data write flag Fjl (j=1~4) corresponding to the value i of the block number data
It is determined whether or not j, i=i~4) is rQ.

If a positive result is obtained here, this means that the block data BLKj i is stored in the memory area of the block number i.
This means that (j = 1 to j, i-i to 4) is not written, and in this case, the CPU 5l moves to step SPIO and stores the currently received unit block in the block data memory area 7 of the block number i. Write the day and evening,
And the data write flag Fji is set to "1". In this way, the CPU 5 i transfers the currently received unit block data B LKi (i-1 to 4) to the sent information card 4.
It is possible to write to a selected memory area.

On the other hand, if a negative result is obtained in step SP9, this means that the same unit block data of the same information card has already been written in the selected memory area. returns to step SP3 described in E without writing new data.

Subsequently, in step SPII, the CPU 51 determines whether the data write flags Fjl to Fj4 (j=1 to j) of the selected memory section Mj (j-1 to j) have all reached the logic "1" level. Make a judgment. If a negative result is obtained here, this means that all unit block data BLKI, BLK2, BL from the information card 4 currently communicating
This means that K3 and BLK4 have not been taken into the data memory MEM, and at this time the CPU 51 returns to the above-mentioned step SP3 and executes the process of receiving the unit block data that has not yet been received and writing it into the data memory MEM. Prepare to be able to do so. On the other hand, if a positive result is obtained in step SPII, this means that all unit block data BLK1, BLK2, BLK3, and BLK4 from the currently communicating information card 4 can be imported into the data memo IJMEM. This means that the combination of block data has ended.

At this time, the CPU 51 moves to step SP12 and transmits the combined frame data to the data transmission circuit 54, and then returns to the above-mentioned step SP3, thereby waiting for the arrival of new unit block data.

In the configurations shown in FIGS. 19 and 20, each time new block data is input, the CPU 51 confirms this in step SP4, and after confirming that there is no data error in step SP5, the CPU 51 updates the received unit block. Based on the card number and block number of the data, if there is data with the same card number as the received card number in the data memory MEM, the corresponding memory area is selected (steps SP6, SP8). And the selected memory section Mj
Check the contents of the data write flag Fji of the same block number as the block number of the unit block data received in step SP1, and if no data has been written, write the currently received unit block data (steps SP9, SP1
0), on the other hand, if data has already been written, the newly received data is discarded.

Also, the card number D8 of the received unit block day. When data with the same card number as is not written in the data memory MEM, the empty memory section Mj (
j = 1 to j) and writes the received unit block data to the corresponding memory section, whereas if there is no free memory area, the currently received block data is discarded without being written to the data memory MEM. do.

Regarding the card number data DNO of the received unit block data, when all the data for one frame, that is, the four block data are written into the data memory MEM, this is confirmed by the data write flag Fji (step SP11), Finishes combining the received unit block data. According to the above structure, when information data formed into a plurality of blocks of data is sequentially transmitted from a plurality of information cards 4, the received information data can be reliably reproduced by combining them. be able to. (G6) Other examples? 1) In the embodiments shown in FIGS. 16 and 17, card number data DNO, block data DATA■ to D
ATA■, block number data DIl■ to D■4, and error detection code data Del1. We have described the case where the unit block data BLKI to BLK4 consisting of ~D elc4 are each attached with header data H having security data and transmitted as one frame of frame data FRM. Instead of or in addition to entering the card number data DNO, security data may be entered and transmitted.

(2) In the above-mentioned embodiment, the case where the present invention is applied to an information card has been described, but the present invention is not limited to this.In short, the present invention is applicable to the case where information data is read from an information source that repeatedly sends out the information data. It can be widely applied. (3) In the case of the embodiment shown in FIG. 14, the master clock CL
Although K is frequency-divided in three stages by the 1/2 frequency divider circuits 88, 89, and 9o, the frequency division ratio is not limited to this and may be changed as necessary.

Further, the values of the exponentiation numbers O to 31 and X of the exponentiation coefficient circuit 87 can be changed as necessary.

(4) In the case of the embodiment shown in FIG. 14, the phase comparison signals S22A and S are
Although the conversion operation to 22B was executed by hardware means, it may also be executed by software means.

■Effects of the Invention According to the present invention, the information data to be transmitted is divided into a plurality of unit block data and stored, and the unit block data are sequentially stored one by one. By transmitting this data, even if a phenomenon such as carrier wave interruption occurs, unit block data transmitted at other timings can be used as meaningful information, compared to the case where information data is transmitted as a whole at once. Now you can read information data more efficiently and reliably! An information card that obtains X can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an information reading device according to the present invention, FIG. 2 is a block diagram showing the structure of an information card, and FIG. 3 is a low-pass filter 34A and 34B of FIG. 1.
FIG. 4 is a signal waveform diagram showing the information data demodulation operation of the response signal processing circuit 6 of FIG.
A characteristic curve diagram showing the frequency characteristics of the digital bandpass filters 41A and 41B shown in FIG. 1, FIG.
1B is a connection diagram showing the configuration of 1B, FIG. 7 is a characteristic curve diagram to explain its scanning operation, FIG. 8 is a signal waveform diagram to explain its ringing waveform prevention effect, and FIG.
FIG. 10 is a signal waveform diagram for explaining the operation of the zero-cross detection circuits 42A and 42B in FIG. 9;
11 is a signal waveform diagram for explaining the phase detection operation in the count circuit 75 of FIG. 9; FIG. 12 is a chart showing a conversion value table of the phase error conversion circuit of FIG. 9;
Fig. 3 is a schematic diagram for explaining the movement of the phase comparison operating range, Fig. 14 is a block diagram showing the detailed structure of the numerically controlled oscillator circuit of Fig. 9, and Fig. 15 shows its numerical frequency. Characteristic curve diagrams showing conversion characteristics, Figures 16 and 17 are schematic diagrams to explain the blocking of information data, Figure 18 is a diagram to explain the effect of blocking, and Figure 19 is a diagram of the data. FIG. 20 is a flowchart showing the block data combination processing procedure; FIG. 21 is a block diagram showing the information card reading system; FIG. 22 is a block diagram showing the structure of a conventional information card. It is. DESCRIPTION OF SYMBOLS 1... Information reading device, 2... Answer request signal generation circuit, 4... Information card, 6...
・・Response signal processing circuit, 21A, 21B・・・1st series, 2nd series response signal acquisition circuit, 2IC・・・・
・Data processing section, 32A, 32B...Phase shift circuit, 33A, 33B...Mixing circuit, 40A
, 4OB...Analog/digital conversion circuit,
41A, 41B...Digital bandpass filter, 42A, 42B...Zero cross detection circuit, 43A, 43B...PLL circuit section, 44A,
44B... Phase comparator circuit, 45A, 45B...
...Numerically controlled oscillator circuit, 46A, 46B...
...Digital signal processing circuit, 51...CPU
, 52...Work memory.

Claims (1)

[Scope of Claims] An information card configured to transmit information data stored in an information memory to the outside via a carrier wave, and read the information data by receiving the carrier wave with an information reading device, The information data stored in the information memory is each composed of a plurality of unit block data including card number data, block data, block number data, and error detection code data, and each unit block data is sequentially sent out one by one. An information card featuring: