JPH03169692A - Electronic component and attaching method for memory card which uses said component - Google Patents

Abstract

PURPOSE: To obtain a method for accurately positioning a conductive bump in a hole of a card by covering at least part of the card surrounding one end of a hole and the hole before mounting an electronic component in the hole, and then bringing the bump into contact with a conductive layer during a mounting step. CONSTITUTION: In the method for mounting an LSI chip on a card 5 and connecting it thereto, an overall card 5 having a hole 15 is covered with a layer 16 of a conductive material. Then, the chip is disposed in the hole 15, and conductive bumps 2, 3, 4 are brought into contact with the layer 16 covering the hole 15. Then, the chip 1 is pressed to the layer 16 to effectively electrically bring the bumps 2, 3, 4 into contact with the layer 16, and the chip 1 or the layer 16 or the both are heated so as to solder the contact. The bumps 2, 3, 4 create protrusions 17, 18, 19 on an upper surface of the layer 16 by the operation. Then, the chip 1 is filled with an embedding material and embedded in the hole 15. Thereafter, the layer 16 is etched to obtain a predetermined circuit pattern on the upper surface of the card. The protrusions 17, 18, 19 of the layer 16 are set to a visible state at the positions of the bumps 2, 3, 4 of the chip 1, and hence etching masks can be easily arranged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for mounting and interconnecting electronic components in a card, which are provided with at least one conductive bump constituting a terminal. The present invention relates to a method for mounting the electronic component in a hole in the card and interconnecting the conductive bump and the conductive portion of the card.

[Prior Art] Such a method can be applied to the production of credit cards and has already been described in the literature (2nd I
E E E International Ele
ctronicsManufacturing Tec
hnology Symposium. September 15, 1986-{7th, San Francisco, pp. 30-33)
. More common methods such as printed wire connections (PWC) and wire bonding and tape automated connections (TAB) are also described in this document.

Wire bonding provides high connection flexibility, but requires two connection operations. That is, first one end of the wire is connected to a conductive bump, and then the other end of the wire is connected to a conductive portion of the card. These lines and connections create undesirable conductive resistance.

Furthermore, a relatively flat connection was realized, and the International Standards Organization (I)
It is not easy to obtain plastic memory cards of the 1-credit type, ie, very low in height, according to the SO standard.

Tape Automated Bonding (TAB) allows for interconnects that are flat and have low conductive resistance.

However, it has the disadvantage that a relatively large area is required on the card in the vicinity of the hole to make this connection.

The printed wiring connection (PWC) method involves mounting electronic components, particularly large-scale integrated circuit (LSI) chips, into holes in series, embedding the chips in the holes, and applying a conductive polymer paste onto the card through a mask. Interconnects are formed by screen printing patterns. This method has the advantage that the formed interconnects have a low height and low conductive resistance, but the disadvantage is that the position of the chip in the hole, and more specifically the position of each of its conductive bumps, is not accurate. There are problems in accurately positioning masks for screen printing because of the unknown

[First Problem to be Solved by the Invention] An object of the present invention is to accurately position conductive bumps in the holes so that the mask for screen printing mentioned above can be accurately positioned. The aim is to provide a method that can be used.

[Means for Solving the First Problem] According to the invention, it is an object of the present invention that, before installing an electronic component into the hole, one end of the hole and at least a part of the card surrounding the hole are This is achieved by being covered with a conductive layer, after which the conductive bumps are brought into contact with said layer during the attachment process.

Another feature of the method of the invention is that after being contacted with the conductive layer, the conductive bumps are soldered to the conductive layer by heating the conductive layer, the electronic component, or both.

Yet another feature of the method of the invention is that the electronic component and the conductive layer are pressed together during the soldering process.

In this way, convex bumps or protrusions are generated on the external surface of the conductive layer at positions corresponding to the conductive bumps of the electronic component, so that the position of this bump can be known precisely and therefore for subsequent screen printing operations. can be easily done.

Yet another feature of the method of the invention is that a portion of the conductive layer is removed during the connection step.

In a preferred embodiment, these portions are removed from the conductive layer by etching techniques similar to those used to form printed circuit boards.

The resulting connections do not increase the thickness of the card and
The conductive resistance caused by the connections is very small.

SECOND PROBLEM TO BE SOLVED BY THE INVENTION The present invention also relates to a process for forming conductive bumps on terminal pads of integrated circuit electronic components covered by a passivation layer.

In currently available electronic components such as LSI chips, the terminal pads are arranged in recesses in the passivation layer, so that they can be connected to the card by the methods described above or by printed wiring connections (PWC).

Another object of the present invention is to provide a processing method for shaping conductive bumps protruding from a passivation layer, thereby enabling the method of the invention as described above to be used for interconnection of electronic components and cards. That's true.

[Second Means for Solving the Problem] According to the present invention, the object is to cover the passivation layer with a conductive protective layer, and cover the conductive protective layer with a mask having holes at positions corresponding to the terminal pads. depositing metal in the hole, removing the mask, and etching the conductive protective layer to remove a portion of the conductive protective layer overlying the panvation layer. This is achieved by a method including.

In this way, conductive bumps are formed at the terminal pads of the electronic component and protrude from the passivation layer.

The above-mentioned and other objects and features of the invention will be apparent to those skilled in the art from the following description of the embodiments, taken in conjunction with the accompanying drawings.

[Examples] The method described below is applicable to credit, debit, or charge cards, which are commonly referred to as memory cards when they are capable of storing variable data, and are referred to as intelligent (smart) cards when they contain a microprocessor. can be used to form various types of integrated circuit (IC) cards.

In the case of the last-mentioned intelligent card (not shown), a battery connected to the terminals of the card's printed circuit, a random access memory (RAM), a read-only memory (R
OM) and/or other large-scale integrated circuits (LSI)
) houses numerous electronic components such as chips.

First, a method for forming the conductive bumps 2, 3.4 on the chip l will be described below. In this connection, in some cases these bumps may be attached to the card 5 by soldering, for example.
It must be noted that thermal conductivity is necessary to ensure that the

FIG. 1 shows an LSI chip 1 having terminal pads 8, 7.8 located in the middle of a passivation layer 9 covering the top surface of the chip i.

The passivation layer 9 is, for example, a silicon nitride layer,
Its purpose is to protect the chip against collisions and other damage.

In a first step, shown in FIG. 2, a terminal layer IO is deposited on the passivation layer 9. This layer IO is composed of titanium, tungsten and gold. Methods for forming such a terminal layer lO on the passivation layer 9 are described in the literature (for example, 'Int.
National Conf'erence on
Metal! urg1cal Coatings,
195-205). This terminal layer 10 has a thickness of about 2000
Has the thickness of a person.

FIG. 3 shows the second step, in which the photolithographic mask 1
The terminal layer IO is coated with l. This photolithographic mask 11 has holes 12, 13., corresponding to the positions of the terminal pads 6, 7.8, respectively. 14 to reach the terminal layer 10.

In the third step, holes 12, 13. are formed as shown in FIG.
A metal material is sputtered during step 14. The material is for example gold or copper. This makes the conductive bumps 2, 3
．． 4 are formed at the positions of terminal pads 8 and 7.8 of chip l, respectively. These conductive bumps 2, 3.4 are approximately 2
It has a height of 5 to 30 microns.

In the fourth step, as shown in FIG. 5, the photolithographic mask 11 is first removed from the chip 1, and the chip 1 is etched to remove the portion of the terminal layer 10 that covers the passivation layer 9. .

Since the thickness of the terminal layer 10 is much lower than the height of the conductive bumps 2, 3.4, the conductive bumps 2, 3.4 are only slightly affected by this metal etching.

A method for attaching the thus obtained LSI chip to the card 5 and connecting it thereto will be described below.

First, in the first step shown in FIG. 6, one or more holes i5 are formed in the card 5. This hole 15 has the same shape as the LSI chip l to be installed therein, for example, rectangular, and is slightly larger.

In a second step, the entire card 5 with the holes l5 is covered with a layer 6 of conductive material, which material is a metal, such as copper or a metal alloy such as bronze.

Then, in a third step shown in FIG. 7, the chip 1 is placed in the hole l5 and its conductive bumps 2, 3.4 are in contact with the conductive layer i6 covering the hole l5. Therefore, the chip 1 is first mounted on a support which transports it into the hole l5, or in a preferred embodiment (not shown) the card 5 is inverted and the chip 1 is mounted on a support for placing it into the hole l5. treated by suction means.

In a fourth step (not shown), the electrical contact between the conductive bumps 2, 3.4 and the conductive layer 16 is ensured by pressing the chip l against the conductive layer l6, and the contacts are soldered. The chip 1 or the conductive layer 16, or both, are heated to perform the following steps.

In a preferred embodiment (not shown), a thermode is placed on the chip I for simultaneous pressurization and heating. This action causes the conductive bumps 2,
3.4 are protrusions 17.3 and 3.4 on the upper surface of the conductive layer i6, respectively. 1
8. Generate 19.

Prior to installing the chip l into the hole l5, a layer of material such as tin (not shown) is applied to the conductive bump 2 on the conductive layer l6.
．． 3.4 may be coated on the underside of the conductive layer 16 covering this hole to facilitate soldering.

In a fifth step, the chip l is embedded in the hole l5 by filling with an embedding material such as epoxy. The embedding material has a viscosity that allows it to fill the gap between the chip 1 and the conductive layer 16. In this way, when a portion of the conductive layer 16 is removed by etching as described below, the upper surface of the chip 1 is protected by the buried material. The expansion coefficient of the embedding material is selected such that the card 5 is not mechanically influenced by the heat dissipation of the operating chip l. The underside of the card 5 is then stacked into the flat structure shown in FIG.

FIG. 9 shows the sixth and final step of etching the conductive layer 16 to obtain the desired circuit pattern on the top surface of the card. Projections 17, 18 on the upper surface of the conductive layer te. 19 makes it possible to visualize the positions of the conductive bumps 2.3.4 of the chip l, thus facilitating alignment of the etching mask. Portions 20 and 2l can thus be removed from conductive layer l6 with high accuracy.

By using this method, parts 20 and 2l
The width of the passages in the conductive layer {6 that remain after removal of the conductive layer {6) and the width of the connections connecting the chip l and the card 5 are selected according to the value of the current flowing therethrough or the type of connection path required;
For example, the ground path is wide, and the signal path is relatively narrow.

The cards thus obtained are then protected and
or coated with a layer of reinforcing material.

By using this method the chip 1 of the conductive layer l6
Since their position with respect to the top surface of the chip 1 is fixed, the terminal pads 6, 7.8 of the chip 1 do not need to be arranged at its periphery as in the case of wire bonding. If in this case the terminal pads are not arranged at the periphery, the connecting lines extend over the chip l and are displaced, for example by vibrations, thereby creating a short circuit or at least a variable capacitance with the chip.

Another application of this method is the formation of heat dissipation elements for chips l. Since the part of the surface of the chip l with the highest power consumption can be predetermined, the terminal pads 8,
A terminal pad of the same type as 7.8 is formed in the vicinity of this part and is connected to the part of the conductive layer 1B via a thermally conductive bump of the same type as the conductive bumps 2, 3.4. This portion of conductive layer 1B is selected to be large enough to act as a heat dissipation element.

Although this invention has been described above in relation to a specific device,
It should be recognized that this description is for illustrative purposes only and is not intended to limit the scope of the invention as set forth in the appended claims.

[Brief explanation of the drawing]

1 to 5 show successive steps of the method according to the invention for forming conductive bumps 2, 3.4 on electronic components using the method of the invention, and FIGS. FIG. 9 shows the subsequent steps of the method according to the invention. 1... Chip, 2 3 4... Conductive bump, 5.
...Card, 9...Passivation layer, 10...
Terminal layer, 11... Photophosphorographic mask, 16...
・Conductive layer.

Claims (12)

[Claims] (1) mounting an electronic component comprising at least one conductive bump constituting a terminal into a hole in a card, and interconnecting the conductive bump and a conductive portion of the card; In the mounting method, prior to mounting the electronic component into the hole of the card, one end of the hole and at least a portion of the card around the hole are covered with a layer of conductive material, and then the conductive material is coated in the mounting step. A method for attaching an electronic component to a card, characterized in that a conductive bump is brought into contact with a layer of conductive material. 2. The method of claim 1, wherein a portion of the layer of conductive material is removed in the step of interconnecting. 3. The method of claim 2, wherein a portion of the layer of conductive material is removed by etching. (4) The conductive bumps are soldered to the conductive material layer by heating the conductive material layer in the interconnecting step after contacting with the conductive material layer. The method described in Scope 1. (5) The conductive bumps are soldered to the conductive material layer by heating the electronic component in the interconnecting step after contacting with the conductive material layer. The method described in Section 1. 6. A method according to claim 4 or 5, characterized in that the electronic component and the layer of conductive material are pressed together during the soldering operation. 7. A method as claimed in claim 4 or claim 5, characterized in that an intermediate metal is provided between the conductive bump and the layer of conductive material to facilitate the soldering operation. (8) A portion of the conductive material layer is removed after the soldering operation,
The method according to any one of paragraphs 4 and 5. 9. The method of claim 1, wherein the conductive bump and the conductive material layer are both thermally conductive and electrically conductive. (10) The method according to claim 1, wherein the conductive material layer is a metal sheet. (11) A method of forming a conductive bump on a terminal pad of an integrated circuit electronic component covered with a passivation layer, comprising: covering the passivation layer with a conductive protective layer, and positioning the bump corresponding to the terminal pad. covering the conductive protective layer with a mask having holes in the holes, depositing metal in the holes, removing the mask, and removing a portion of the conductive protective layer covering the passivation layer. A method for forming a conductive bump, comprising the step of: etching the conductive protective layer. (12) The method according to any one of claims 1 to 10, wherein the conductive bump is formed on the electronic component by the method described in claim 11.