CA2003229C - Method for mounting an electronic component and memory card using same - Google Patents

Abstract

J. BOUCQUET 01 ABSTRACT
METHOD FOR MOUNTING AN ELECTRONIC COMPONENT
AND MEMORY CARD USING SAME.
A method for mounting a LSI chip (1) with conductive bumps (2, 3, 4) as terminals into a hole (15) of a card (5) and for interconnecting them. The card and therefore one end of the hole is first covered by a layer (16) of a conductive material. Then the conductive bumps of the chip Placed in the hole are soldered to the layer whilst being pressed against this layer. Thus protrusions (17, 18, 19) are created on the external surface of the layer. These protrusions are used to facilitate the alignment of the mask used during the subsequent etching operation of the layer.
The invention also concerns a process for creating the conductive bumps (2, 3, 4) on the terminal pads (6, 7, 8) of the LSI chip (1).

Description

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- l - J. BOUCQUET 01 METHOD FOR MOUNTING AN ELECTRONIC COMPONENT
( AND MEMORY CARD USING SAME.
The present invention relates to a method for mounting an electronic comPOnent into a card and for interconnecting them, said electronic component being provided with at least one conductive bump constituting a terminal thereof, said method including the stePs of mounting said component into a hole of said card and of interconnecting said conductive bump and a conductive `~ ~
10 portion of said card. ;~ i;
~-; Such a method can be applied to the manufacture of "credit" cards and is already known from the article ~A NEW ;~
LSI INTERCONNECTION METHOD FOR IC CARD" by M. Ohuchi et al, published at the occasion of the "2nd IEEE International 15 Electronics Manufacturing Technology Symposium", September ;
15-17, 1986 - San Francisco, pages 30 to 33.
Interconnection methods such as the Printed Wiring Connection ~PWC), as well as more conventional methods such :
as the wire bonding method and TaPe Automated Bonding (TAB) ~ 9 20 method are described in this article.
The wire bonding method provides an high bonding ~P~ flexibility but requires two wire bonding operations : a ; first one to connect one end of a wire with the conductive bump and a second one to connect the other end of the wire -25 with the conductive portion of the card. This wire as well as the bonds themselves constitute unwanted conduction - resistances. Moreover, it is not easy to realize a ~ ;

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relatively flat interconnection and to obtain plastic memory cards ~ ;;
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of the "credit" type realized according to the International - ;~
Standards Organization (ISO) recommendations, i.e. having a small ~ -~
height.
The Tape Automated Bonding (TAB) method allows the ~ . ~
realization of an interconnection which is flatter and has a lower , ....,~
conduction resistance. However it has the drawback of requiring a relatively large area on the card near the hole to realize this - ~;
interconnection. .
The Printed Wiring Connection (PWC) method con~ists in successively mounting the electronic component, more particularly ~ -~
a Large Scale Integrated (LSI) chip, into the hole, embedding this .. . . .- , .
chip in the hole, and realizing the interconnections by screen printing a pattern of conductive polymeric paste on the card ~ j -through a mask. This method has several advantages since the interconnectlon realized has a small height and a low conduction ~- re~istance, but a drawback thereof i8 that the position of the , chlp in the hole and more particularly of each conductive bump thereof is not accurately known so that correctly positioning the mask for screen printing is a problem. ~ ~;
An ob~ect of the present invention i3 to provide a ~ method which has the last mentioned advantages and moreover 'J accurately positions the conductive bump in the hole.
According to the invention, this object is achieved by a method including the steps of creating at least one hole into said card, covering one end of said hole and at least that part of said : , .
card surrounding said hole by a layer of a conductive material, - ~
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2 0 0 3 ~ ~q 72430-104 inserting sald component into said hole of said card, pressing ~ ~-said electronic component and a portion of an adjacent one side of said conductive layer against each other and interconnecting said bump and said layer so that the said conductive bump forms a protrusion that ls visible from the other side of æald layer, using sald protruslon to allgn an etchlng mask relative to said -conductive bump, and using said etching mask in a subsequent etching operation to remove portions of said conductive layer ~ `
while leavlng said bump electrlcally interconnected to said layer.
Another characteristic feature of the present method is ;~`
that after having been brought into contact with said conductive layer, said conductive bump is soldered to said conductive layer `
by heating either said conductive layer, said electronic ~; component, or both and this solderlng may take place while the ;"~
electronic component and the conductlve layer are being pressed against each other.
By using the new method the realized interconnection does not increa~e the thickness of the card and the conduction ;;
resistance lntroduced by the contact iB very small.
The above mentloned and other ob~ects and features of the invention will become more apparent and the invention itself -` i wllllbe best understood by referrlng to the following description ;
of an e~bodiment taken in con~unctlon with the accompanying drawings wherein-Figs. 1 to 5 illustrate the successive steps of a process for creating conductive bumps 2, 3, 4 on an electronic component 1 used in a method according to the invention; and Figs. 6 to 9 illustrate the successive steps of the method according to the invention. ~ ~
The process and the method deiscribed hereinafter may be ~ ~;
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used to realize an Integrated Circuit tIC) card of the credlt, debit or charge type generally called memory card when able to store varlable data or intelllgent (smart) card when including a ;
microprocessor. In thls last case (not shown) it also houses a number of electronic components such as a battery, a Random Access Memory (RAM), a Read-Only Memory (ROM) and/or other Large Scale Integrated (LSI) chips connected to terminals of a circuit printed on the card.
Eirst, the process for creating electrically conductive bumps 2, 3, 4 on a chip 1 1B described hereafter. In this connection it may be noted tha~ in some ' '; ' ' '' '' , : -:
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~ 5 - J. BOUCQUET 01 -circumstances these bumps only need to be heat conductive to ensure, for instance, a better fastening of the chip 1 to a card 5 by soldering.
Fig. 1 shows an LSI chip 1 having terminal pads 6, 7, 8 located in recesses or holes of a passivation layer 9 covering the upper surface of the chip 1. The passivation ~-layer 9 is for instance a laYer of silicon nitride and its goal is to protect the chip 1 against corrosion and other possible damages.
In a first process step illustrated by Fig. 2, a ;` - -~
( trimetal layer 10 is deposited over the passivation layer ; -;~9. This layer 10 is constituted by titanium, tungsten and gold. The process to apply such a trimetal laYer 10 on a ~ ~Y.
passivation layer 9 is for instance described in the article "STUDIES OF THE Ti-W/Au METALLIZATION ON ALUMINUM"
by R. NOWICKI et al, published at the occasion of the International Conference on Metallurgical Coatings~, San Francisco, California, U.S.A., April 3-7, 1978, pages 195 to 205. This trimetal layer 10 has a thickness of about ; 20 2,000 Angstrom. ,~
Fig. 3 illustrates a second step of the present process which consists in covering the trimetal layer 10 ( with a photolithographic mask 11. This photolithographic ',~
mask 11 is such that the trimetal layer 10 is accessible through holes 12, 13, 14 corresponding to the locations of the terminal pads 6, 7, 8 respectively.~ `
; A third process step, illustrated by Fig. 4, ~ consists i;n sputtering in the holes 12, 13, 14 melta~ c ~''""'~'~!~;
i,~; material which is for instance gold or copper.
Electrically conductive bumps 2, 3, 4 are created in this manner at the locations of the terminal pads 6, 7, 8 of the chip 1 respectively. These conductive bumps 2, 3, 4 have ``~
a height of about 25 to 30 microns."'.`,'`'~'~`'','.!~
` In a fourth process step illustrated by Fig. 5, `~ 35 first the photolithographic mask 11 is removed from thé

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- 6 - J. BOUCQUET 01 chip 1 and the latter is etched to remove the portions of ;~
the trimetal layer 10 covering the passivation layer 9. ~ ~
Because the thickness of the trimetal layer 10 is much ~ ~-smaller than the height of the conductive bumps 2, 3, 4, :~
the latter are only sligthly affected by this metal etching process. ;-~
The method for mounting the LSI chip 1 thus obtained into a card 5 and for interconnecting them is described hereafter.
A first method step related to Fig. 6, consists in making one or more holes 15 in the card 5. The hole 15 is slightly larger than and has the same shape, e.g.
rectangular, as the LSI chip 1 to be mounted therein.
During a second method steP, the whole card 5 including the hole 15 is covered with a layer 16 of an electrically conductive material which is generally a metal ;~
such as copper or a metallic alloy such as brass.
Then, in a third method step illustrated by Fig. 7, the chip 1 is mounted inside the hole 15 so that the , 20 conductive bumps 2, 3, 4 thereof make contact with the ~;
conductive layer 16 covering the hole 15. The chip 1 is ~:~ therefore first mounted on a support which brings it into the hole 15 or, in a preferred embodiment (not shown), the ( card 5 is reversed and the chip 1 is handled by suction means which positions it into the hole 15.
?r , ~ In a fourth method steP (not shown), an intimate electrical contact is ensured between the conductive bumps 2, 3, 4 and the conductive layer 16 by exerting pressure on the chip 1 towards the conductive layer 16 while heating `.!'' '~
either the chip 1, the conductive layer 16, or both so as to perform a contact soldering. In the preferred embodiment (not shown), a "thermode" is placed on the chip 1 to simultaneous}y create pressure and heating. By this operation the conductive bumps 2, 3, 4 create protrusions 35 17, 18, 19 on the upper surface of the conductive layer 16 ~;;

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respectively. ;~
Prior to mounting the chip 1 in the hole 15, a layer of material (not shown) such as tin may be coated on the lower side of the portion of conductive layer 16 which;~
covers this hole 15 in order to facilitate the soldering of the conductive bumps 2, 3, 4 to this layer 16.
In a fifth method step, the chiP 1 is embedded in ~`
the hole 15 by filling it (not shown) with an embedding material such as epoxy. The embedding material has a ~i--10 viscosity which allows it to fill the interstices between `~- -(~the chip 1 and the layer 16. In this way, the upper side of the chip 1 is protected by the embedding material when portions of the layer 16 are removed by the etching step described below. It is to be noted that the coefficient of ~s~
15 expansion of the embedding material is chosen so that the i;~
card 5 is not mechanically affected by the heat dissipation ,~
of the operating chip 1. The bottom side of the card 5 isi~
then laminated to obtain the planar structure shown in Fig.
8.
Fig. 9 relates to a sixth and last method step which consists in etching the conductive layer 16 to obtain a ;~
required circuit pattern on the uPper surface of the smart card. The protrusions 17, 18, 19 on the upper surface of the conductive layer 16 thereby facilitate the alignment of the etching mask as they allow a visual localization of the conductive bumps 2, 3, 4 of the chip 1. Portions 20 and 21 can thus be removed from the electrically conductive layer 16 with an high accuracy. , By using the present method, the width of the paths ~;~30 of the conductive layer 16 remaining after the portions 20, 21 have been removed and interconnecting the chip 1 and the card 5 is chosen in function of the value of the current which has to flow therethrough or of the type of connection path required, e.g. a wide ground connection path as 35 compared to a smaller signal connection path. ~ '~
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- 8 ~ J. BOUCQUET 01 The smart card thus obtained may afterwards be coated with a layer of protective and/or strengthening material.
Because the position of the conductive layer 16 is fixed with respect to the upper surface of the chip 1, by using the present method the terminal pads 6, 7, 8 of the chip 1 need no longer be exclusively located at the periphery thereof as it is the case for instance when the wire bonding method is used. If in this case a terminal pad is not located at the periphery, the interconnecting (; wires then extend over the chiP 1 and may be displaced, e.g. by vibrations, therebY causing short-circuits or at ~ ;
least constituting variable capacitances with this chip.
Another application of the present method is to create a heat dissipation element for the chip 1. Since the portion of the surface of the chip 1 which has the highest power dissipation can be determined, terminal pads of the same type as 6, 7, 8 maY be created near this ~;~ portion and connected to a portiun of the layer 16 via heat conductive bumps of the same tyPe as 2, 3, ~. This portion of the layer 16 may be chosen sufficiently large to operate as a heating dissipation element.
While the principles of the invention have been ,, . . .
described above in connection with specific apparatus, it ~ ~ ;
is to be clearly understood that this descriPtion is made only by way of example and not as a limitation on the scoPe -of the invention. ~
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Claims (7)

1. Method for mounting an electronic component into a card and for interconnecting the component to the card, said electronic component being provided with at least one conductive bump constituting a terminal thereof, said method including the steps of creating at least one hole into said card, covering one end of said hole and at least that part of said card surrounding said hole by a layer of a conductive material, inserting said component into said hole of said card, pressing said electronic component and a portion of an adjacent one side of said conductive layer against each other and interconnecting said bump and said layer so that the said conductive bump forms a protrusion that is visible from the other side of said layer, using said protrusion to align an etching mask relative to said conductive bump, and using said etching mask in a subsequent etching operation to remove portions of said conductive layer while leaving said bump electrically interconnected to said layer.

2. Method according to claim 1, further comprising the step of soldering said conductive bump to said conductive layer by heating said conductive layer.

3. Method according to claim 1, further comprising the step of soldering said conductive bump to said conductive layer by heating said electronic component.

4. Method according to claim 1, further comprising the step of soldering said conductive bump to said conductive layer while pressing said electronic component and said conductive layer against each other.

5. A method according to claim 1, further comprising the steps of providing an intermediate metal between said conductive bump and said conductive layer, and soldering both said conductive bump and said conductive layer to said intermediate metal.

6. Method according to claim 1, wherein both said conductive bump and said conductive layer are heat conductive as well as electrically conductive.

7. Method according to claim 1, characterized in that said conductive layer is a metallic sheet.