NZ239815A - Conductive protrusions on integrated electronic components as terminals - Google Patents

Description

<div id="description" class="application article clearfix"> <p lang="en" class="printTableText">l V, '' • " ' - <br><br> S. 0.2 (5) "&lt; *\ ** - <br><br> ^ Application No. 230738 H Q g f*} Application Date 21 September 1989 * <br><br> NEW ZEALAND PATENTS ACT 1953 <br><br> .tuC provisions cf Regu- <br><br> COMPLETE SPECIFICATION <br><br> laiion 23 (1) the <br><br> Specification has been ante-dated Jo 19 i.t <br><br> 'MEMORY CARD' <br><br> N.Z. PATfifITOFFICE <br><br> Initials <br><br> 16 SEP 1991 <br><br> "ECEIV "» <br><br> WE, ALCATEL AUSTRALIA LIMITED, A Company of the State of New South Wales, of 280 Botany Road, Alexandria, New South Wales, 2015, Australia, hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: <br><br> 1 <br><br> 2398 1 <br><br> This invention relates to an integrated electronic component having conductive protrusions thereon, and to a method of forming the protrusions. <br><br> The invention will be described in the context of mounting an electronic component into a card and for interconnecting the card and component, said electronic component being provided with at least one conductive bump constituting a terminal thereof. A method of mounting said component into a hole of said card and of interconnecting said conductive bump and a conductivc portion of said card will also be described. <br><br> Such a method can be applied to the manufacture of "credit" cards and is already known from the article "A NEW LSI INTERCONNECTION METHOD FOR IC CARD" by M. Ohuchi ct al, published on the occasion of the "2nd IEEE International Electronics Manufacturing Technology Symposium", September 15-17, 1986 - San Francisco, pages 30 to 33. Interconnection methods such as the Printed Wiring Connection (PWC), as well as more conventional methods such as the wire bonding method and Tape Automated Bonding (TAB) method arc described in this article. <br><br> The wire bonding method provides a high bonding flexibility but requires two wire bonding operations : a first one to conncct one end of a wire with the conductive bump and a second one to conncct the other end of the wire with the conductive portion of the card. This wire as well as the bonds themselves constitute unwanted conduction resistances. Moreover, it is not easy to realise a relatively flat interconnection and to obtain plastic memory cards of the "credit" type realised according to the International Standards Organisation (ISO) recommendations, i.e. having a small height. <br><br> The Tape Automated Bonding (TAB) method allows the realisation of an interconnection which is flatter and has a lower conduction resistance. However it has the <br><br> 2398 1 <br><br> drawback of requiring a relatively large area on the card near the hole to realise this interconnection. <br><br> The Printed Wiring Connection (PWC) method consists in successively mounting the electronic component, more particularly a Large Scale Integrated (LSI) chip, into the hole, embedding this chip in the hole, and realising the interconnections by screen printing a pattern of conductivc polymcric paste on the card through a mask. This method has several advantages since the interconnection realised has a small height and a low conduction resistance, but a drawback thereof is that the position of the chip in the hole and more particularly of cach conductive bump thereof is not accurately known so that correctly positioning the mask for screen printing is a problem. <br><br> It is desirable to produce a chip the position of which can be accurately determined when in the recess in the card. Accordingly, a chip is provided with protrusions at its terminals, formed as disclosed herein. <br><br> Accurate location is achieved by covering one end of the hole and at least that part of said card surrounding the hole by a layer of a conductivc material prior to mounting said component into said hole, after which said conductivc bump is brought into contact with said layer during said mounting step. <br><br> Preferably, after having been brought into contact with said conductive layer, said conductive bump is soldered to said conductivc layer by heating either said conductive layer, said electronic component, or both. <br><br> Preferably said electronic component and said conductive layer are pressed against each other during said soldering operation. <br><br> In this way a convex bump or protrusion is crcatcd on the external surface of the conductive layer at a position corresponding to that of the conductive bump of the electronic component so that the position of this bump is accurately known thus facilitating a subsequent screen printing operation. <br><br> 398 1 5 <br><br> Preferably, during said interconnection step portions are removed from said conductive layer. <br><br> In a preferred embodiment these portions arc removed from said conductivc layer by an etching technique similar to the one used to realise printed circuit boards. <br><br> As a result, the realised interconnection docs not increase the thickness of the card and the conduction resistance introduced by the contact is very small. <br><br> The present invention relates to a process for creating a conductivc bump on a terminal pad of an integrated electronic component coated with a passivation layer. <br><br> In the presently available electronic components such as LSI chips the terminal pads are located in rcccsscs of the passivation layer so that their interconnection with an above mentioned card by the above method or by the printed wiring conncction (PWC) is impossible. <br><br> Another object of the present invention is to provide a process for creating a conductivc bump protruding from the passivation layer so that the above method according to the invention may be used for interconnecting the electronic component and a card. <br><br> According to the present invention this other object is achieved by including in said process the steps of covering said passivation layer with a conductivc protection layer, of covering said protection layer with a mask having a hole at a location corresponding to said terminal pad. of depositing a metal into said hole, of removing said mask, and of etching said protection layer so as to remove the portions thereof covering said passivation layer. <br><br> In this way, a conductivc bump is crcated at the location of the terminal pad of the electronic component and protrudes from the passivation layer. <br><br> The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the <br><br> following description of an embodiment taken in conjunction with the accompanying drawings wherein: <br><br> Figs. 1 to 5 illustrate the succcssivc steps of a proccss according to the invention for creating conductive bumps 2, 3, 4 on an electronic component 1 used in a method according to the invention; and <br><br> Figs. 6 to 9 illustrate the succcssivc steps of this method. <br><br> The process and the method described hereinafter may be used to realise an Integrated Circuit (IC) card of the credit, debit or charge type generally callcd memory card when able to store variable data or intelligent (smart) card when including a microprocessor. In this last case (not shown) it also houses a number of electronic components such as a battery, a Random Access Memory (RAM), a Read-Only Memory (ROM) and/or other Large Scale Integrated (LSI) chips connected to terminals of a circuit printed on the card. <br><br> First, the proccss for creating electrically conductive bumps 2, 3, 4 on a chip 1 is described hereafter. In this connection it may be noted that in some circumstances these bumps only need to be heat conductivc to ensure, for instance, a better fastening of the chip I to a card 5 by soldering. <br><br> Fig. 1 shows an LSI chip 1 having terminal pads 6. 7, 8 located in recesses or holes of a passivation layer 9 covering the upper surface of the chip 1. The passivation layer 9 is for instance a layer of silicon notridc and its goal is to protect the chip 1 against corrosion and other possible damages. <br><br> In a first process step ilustratcd by Fig. 2. a trimctal layer 10 is deposited over the passivation layer 9. This layer 10 is constituted by titanium, tungsten and gold. The process to apply such a trimctal layer 10 on a passivation layer 9 is for instance described in the articlc "STUDIES OF THE Ti-W/Au METALLIZATION ON ALUMINUM" by R. NOWICKI ct al, published on the occasion of the "Interna <br><br> tional Conference on Metallurgical Coatings", San Francisco, California, U.S.A., April 3-7, 1978, pages 195 to 205. This trimctal layer 10 has a thickness of about 2,000 Angstrom. <br><br> Fig. 3 illustrates a second step of the present proccss which consists in covering the trimental layer 10 with a photolithographic mask 11. This photolithographic mask 11 is such that the trimctal layer 10 is accessible through holes 12, 13, 14 corresponding to the locations of the terminal pads 6, 7, 8 respectively. <br><br> A third proccsss step, illustrated by Fig. 4, consists in sputtering in the holes 12, 13, 14 metallic material which is for instance gold or copper. Electrically conductivc bumps 2, 3, 4 are created in this manner at the locations of the terminal pads 6, 7, 8 of the chip I respectively. These conductivc bumps 2, 3, 4 have a height of about 25 to 30 microns. <br><br> In a fourth proccss step illustrated by Fig. 5, first the photolithographic mask 11 is removed from the chip I and the latter is etched to remove the portions of the trimetal layer 10 covering the passivation layer 9. Because the thickness of the trimctal layer 10 is much smaller than the height of the conductive bumps 2, 3, 4, the latter are only slightly affected by this metal etching process. <br><br> The method for mounting the LSI chip I thus obtained into a card 5 and for interconnecting them is described hereafter. <br><br> A first method step related to Fig. 6. consists in making one or more holes 15 in the card 5. The hole 15 is slightly larger than and has the same shape, e.g. rectangular, as the LSI chip 1 to be mounted therein. <br><br> During a second method step, the whole card 5 including the hole 15 is covered with a layer 16 of an electrically conductivc material which is generally a metal such as copper or a metallic alloy such as brass. <br><br> '$8 1 <br><br> Then, in a third method step illustrated by Fig. 7, the chip 1 is mounted inside the hole 15 so that the conductivc bumps 2, 3, 4 thereof make contact with the conductive layer 16 covering the hole 15. The chip I is therefore first mounted on a support which brings it into the hole 15 or, in a preferred embodiment (not shown), the card 5 is reversed and the chip 1 is handled by suction means which positions it into the hole 15. <br><br> In a fourth method step (not shown), an intimate electrical contact is ensured between the conductivc bumps 2, 3. 4 and the conductivc layer 16 by exerting pressure on the chip 1 towards the conductivc layer 16 while heating either the chip I, the conductive layer 16, or both so as to perform a contact soldering. In the preferred embodiment (not shown), a "thcrmodc" is placed on the chip 1 to simultaneously create pressure and heating. By this operation the conductivc bumps 2, 3, 4 create protrusions 17, 18, 19 on the upper surface of the conductivc layer 16 respectively. <br><br> Prior to mounting the chip 1 in the hole 15, a layer of material (not shown) such as tin may be coated on the lower side of the portion of conductive layer 16 which covers this hole 15 in order to facilitate the soldering of the conductive bumps 2, 3, 4 to this layer 16, <br><br> In a fifth method step, the chip 1 is embedded in the hole 15 by filling it (not shown) with an embedding material such as epoxy. The embedding material has a viscosity which allows it to fill the intcrsticcs between the chip I and the layer 16. In this way, the upper side of the chip I is protcctcd by the embedding material when portions of the layer 16 arc removed by the etching step described below. It is to be noted that the coefficient of expansion of the embedding material is chosen so that the card 5 is not mechanically affected by the heat dissipation of the operating chip I. The bottom side of the card 5 is then laminated to obtain the planar structure shown in Fig. 8. <br><br> "? * © 8 1 <br><br> Fig. 9 relates to a sixth and last method step which consists in etching the conductive layer 16 to obtain a required circuit pattern on the upper surface of the smart card. The protrusions 17, 18, 19 on the upper surface of the conductive layer 16 thereby facilitate the alignment of the etching mask, as they allow a visual localisation of the conductivc bumps 2, 3. 4 of the chip 1. Portions 20 and 21 can thus be removed from the electrically conductivc layer 16 with a high accuracy. <br><br> By using the present method, the width of the paths of the conductivc layer 16 remaining after the portions 20, 21 have been removed and interconnecting the chip 1 and the card 5 is chosen in function of the value of the current which has to flow therethrough or of the type of connection path required, e.g. a wide ground connection path as compared to a smaller signal connection path. <br><br> The smart card thus obtained may afterwards be coated with a layer of protective and/or strengthening material. <br><br> Because the position of the conductivc layer 16 is fixed with respect to the upper surface of the chip 1, by using the present method the terminal pads 6, 7, 8 of the chip 1 need no longer be exclusively located at the periphery thereof as it is the case for instance when the wire bonding method is used. If in this ease a terminal pad is not located at the periphery, the interconnecting wires then extend over the chip 1 and may be displaced, e.g. by vibrations, thereby causing short-circuits or at least constituting variable capacitances with this chip. <br><br> Another application of the present method is to create a heat dissipation element for the chip 1. Since the portion of the surface of the chip 1 which has the highest power dissipation can be determined, terminal pads of the same type as 6, 7, 8 may be created near this portion and connected to a portion of the layer 16 via heat conductive bumps of the same type as 2, 3, 4. This portion of the layer 16 may be chosen sufficiently large to operate as a heating dissipation element. <br><br> ^98 1 5 <br><br> While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention. <br><br> O <br><br> 10 <br><br> 15 <br><br> 20 <br><br> 25 <br><br> 9 <br><br></p> </div>

Claims (12)

<div id="claims" class="application article clearfix printTableText"> <p lang="en"> What we claim is:<br><br>

1. A method of producing one or more conductive protrusions cach on a corresponding terminal pad of an integrated electronic component coated with a passivation layer, the method including the steps of:<br><br> covering the passivation layer and cach terminal pad with a protective layer of conductive material;<br><br> coating the protective layer with a mask having holes corresponding to the location of each terminal pad;<br><br> depositing metal into cach hole; removing the mask; and etching the protective layer to remove the portions thereof covering the passivation layer.<br><br>

2. A method of producing one or more conductivc protrusions substantially as herein described with reference to the accompanying drawings.<br><br>

3. A method of mounting an electronic component in a recess in a card wherein the card has one or more protrusions formed by the method of claim 1 or claim 2, wherein the recess is closed at one end by a conductive layer, the method including the steps of:<br><br> pressing the or each protrusion and the conductive layer together to form visible deformations on the side of the conductivc layer opposite to the component, the position of the deformations corresponding to the position of the protrusions;<br><br> heating either conductivc layer or the component or both to cause the conductive layer to adhere to the or cach protrusion;<br><br> using the visible deformations as reference points, removing portions of the conductive layer to establish conductivc paths from the or cach protrusion to corresponding portions of the contact zone.<br><br> 10<br><br>

4. A method as claimed in claim 3, wherein the conductive layer includes a deposit of a solderable material in the region in which the or each protrusion contacts the conductive layer.<br><br>

5. A method as claimcd in claim 3 or claim 4, wherein the portions of the conductive layer are removed by etching.<br><br>

6. A method as claimcd in claim 5, wherein the visible deformations are used to align one or more etching masks.<br><br>

7. A method as claimcd in any one of claims 3 to 6, wherein the conductive protrusion and the conductive layer arc heat conductivc as well as electrically conductive.<br><br>

8. A method as claimcd in claim 7, wherein the conductive layer is used to help disperse heat generated when the component is in use.<br><br>

9. A method as claimcd in claim 3 to 8, wherein the conductivc layer is a metallic sheet.<br><br>

10. A method of mounting an electronic component in a card as herein described with reference to the accompanying drawings, wherein the component has protrusions formed on it by the method of claim I or claim 2.<br><br>

11. An integrated electronic component having protrusions formed by the method of claim 1 or claim 2.<br><br>

12. A card containing an integrated clcctronic component mounted by the method of any one of claims 3 to 10. r- —_<br><br> N.z. PATENT OFFICE<br><br> 16 SEP 1991<br><br> ALCATEL AUSTRALIA LIMITED<br><br> PECEIV- &gt;<br><br> F -<br><br> Authorized Agent P5/l/l703<br><br> 11<br><br> </p> </div>