JPH03169044A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a silicon substrate from being short-circuited to an interconnection or the like which is formed during a transfer to a next process even when a second-layer insulator used to fill up a groove region surrounded by a first-layer insulator is overteched by a method wherein the first-layer insulator formed on an inner wall of a groove made in an element isolation region of a semiconductor substrate forms a sidewall. CONSTITUTION:Grooves 2 are made in an element isolation region of a P-type silicon substrate 1; inner walls of the grooves 2 are oxidized; after that, an oxide film 7 and a phosphate glass (BPSG) film 8 containing boron are formed one after another; the BPSG film 8 is made to reflow by a heat treatment; the grooves 2 are filled up completely. The BPSG film 8 and the oxide film 7 are etched back one after another by a dry etching operation by using CHF3 gas; an active region of the substrate 1 is exposed. At this etching-back operation, an etch rate of the oxide film 7 is smaller than an etch rate of the BPSG film 8; the oxide film is left as sidewalls 9 in the groove parts in the silicon substrate after the etchingback operation. Thereby, it is possible to prevent that a gate electrode interconnection formed in the next or later process is short-circuited to the substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device isolation method for semiconductor integrated circuits, and more particularly to a trench isolation method as an alternative to the conventional selective oxidation method (LOGOS).

[Conventional technology]

Conventional trench isolation, as shown in FIG. i'l7
b) After forming a thin thermal oxide film 3 on the inner wall of r/42, an insulating film 4 is buried by chemical vapor deposition (CVD) or a coating method; It consists of a step of exposing the active region on the surface of the semiconductor substrate by etching back using a technique such as active ion etching. In order to improve the controllability of the etchback, as shown in FIG. 3, a method may be used in which the polycrystalline silicon layer 5 formed on the semiconductor substrate 1 is used as an etching stopper and is removed after the etchback. (For example, O. Kudo et al., IEDMtec
hnical digest. pp. 67-70, 1984
Year: K. Sekiya et al., Symp VLSI Te
ch. Dig. (pp. 87-88, 1986) [Problems to be Solved by the Invention] In this conventional trench 7 isolation, it is difficult to detect the end point during etchback of the insulator in which the trench is buried, so the insulator may be over-etched. However, there was a problem in that the wiring formed in the next process and the substrate were short-circuited. Furthermore, when performing etchback with good control using a stopper, additional steps are required to shape or remove the stopper layer.
There were problems in that the process became more complicated and the manufacturing cost increased.

[Means to solve the problem]

In the device isolation of the present invention, a trench formed in the device isolation region of a semiconductor substrate is formed into a first layer of insulator inscribed in the trench and a second layer that buries the trench region surrounded by the first layer of insulator. It is characterized by being embedded with an insulator. Here, the element isolation according to the present invention involves 1) forming a groove in the element isolation region of a semiconductor substrate, 2) filling the groove with a first insulator and a second layer of insulator, and 3) forming the groove. It is formed by etching back the buried insulator by a desired amount, but the second layer of insulator is etched back so that the etching rate of the second layer of insulator is higher than the etching rate of the first layer of insulator. By selecting the type of insulator, the first layer of insulator can be used as a sidewall of the inner wall of the groove.

[Effect]

In the device isolation of the invention, the first layer of insulating material formed on the inner wall of a groove formed in the device isolation region of the semiconductor substrate forms sidewalls, so that the device is surrounded by the first layer of insulating material. Even if the second layer of insulating material covering the groove region is overetched, there is an effect of preventing short circuits between the silicon substrate and wiring formed in subsequent steps.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a process flow of trench isolation used in a MOS transistor according to an embodiment of the present invention. First, a) a trench 2 is formed in the element isolation region of the P-type silicon substrate 1; Then b) After oxidizing the inner wall of the trench, an oxide film 7 and a BPSG film 8 are sequentially formed by CVD, and the BPSG film 8 is reflowed by heat treatment at 900° C. to completely fill the trench 2. Next, c) the BPSG film 8 and the oxide film 7 are sequentially etched back by dry etching using C H F 3 gas to expose the active region of the silicon substrate l. In the above etchback, the etching rate of the oxide film 7 is lower than the etching rate of the BPSG film 8, so that sidewalls 9 remain in the silicon substrate trench after the etchback. As shown in FIG. 4, this Zide wall 9 has the effect of preventing a short circuit between the gate electrode wiring 10 and the P-type silicon substrate 1, which will occur after the attachment process.

FIG. 5 is a process flow sectional view of another embodiment of the present invention. This example is applied to a non-volatile memory having a floating gate electrode, and the process flow is described to create a megabit class EFROM cell in which a floating gate, a control gate, and an element isolation region are formed in a self-aligned manner. Explain.

First, a) a P-type silicon substrate 1 with element isolation in the peripheral circuit section using a selective oxide film (LOCOS oxide film) 20;
A first gate oxide film 21 and a first polycrystalline silicon film 22 are formed on the top.
, a second gate oxide film 23, and a second polycrystalline silicon film 24 are sequentially formed. Then, b) the multilayer film 24, 23, 2
2.21 and the silicon substrate 1 are successively etched by anisotropic dry etching to form grooves 2 in the element isolation regions of the cell array section. The dimensions of such etching are
For example, when manufacturing a 16 Mbit EPROM, a trench with an element isolation width of 0.7 μm and a depth of 1.5 μm is formed.

Subsequently, oxide films 7 and 0.0.0 μm in thickness are formed by low pressure CVD. 5 ~ 0. A BPSG film 8 having a thickness of 8 pm is formed, and the BPSG film 8 is refined by heat treatment at 900° C., and the trench 2 is filled. Next, C) the BPSG film 8
Then, the oxide film 7 is etched back by dry etching to expose the surface of the second polycrystalline silicon film 240. Finally, d) the silicide film 25 is formed by sputtering, and word lines that will become control gate electrodes are patterned. When sorting the sorting line, the second layer of the lower layer
The polycrystalline silicon film 24, first polycrystalline silicon film 22, etc. are sequentially etched to form word lines, control gate electrodes, and floating gate electrodes in a self-aligned manner. The shaped cell array is shown in FIG. According to this method, the etching rate of the oxide film 7 during etch-back is lower than the etching rate of the EPSG film 8, so even if the BPSG film is over-etched, the sidewalls 9 of the oxide film 7 are not formed on the inner walls of the BPSG film. be shaped. This side wall 9 is
Word line 26 and floating gate electrode 27 to be formed in the next process
This avoids short circuits.

In the conventional method in which the trench filling step shown in FIG. 5(b) is performed using only a BPSG single layer film, the yield of memory cell transistors is 70%. On the other hand, when the embedding is performed using the two-layer film of the oxide film and the BPSG film as shown in this embodiment, the yield is dramatically improved to 95% or more.

〔Effect of the invention〕

As explained above, in the present invention, the insulating material buried in the trench in trench element isolation is two-layered, and the sidewall is formed of the insulating material layer in contact with the inner wall of the trench, so that the electrodes, wiring, etc. formed in the later process This has the effect of avoiding short circuit with the inner wall of the groove and improving product yield.

4

[Brief explanation of the drawing]

Figures 1 (a') to (c) are cross-sectional views of the process flow of an embodiment of the present invention, Figures 2 (a) to (c), and Figure 3 (a).
- (d) are cross-sectional views of conventional process flow, Fig. 4 is a schematic diagram of a transistor formed using the trench isolation method shown in Fig. 1, and Fig. 5 (a) - (d) are cross-sectional views of conventional process flow. FIG. 6 is a cross-sectional view of the process flow of the embodiment. FIG. 6 is a sketch of an EPROM cell array formed according to the process flow shown in FIG. l... Semiconductor substrate (P-type silicon substrate), 2.
...Groove, 3...Thermal oxide film, 4...
・Insulator, 5... Polycrystalline silicon, 6...
...Thermal oxide film, 7...CVD oxide film, 8...
...BPSG film, 9...Side wall, 1
0...Gate electrode wiring, 11...N+
Diffusion layer (source), l2...N+ diffusion layer (drain), 20...LOCOS, 21...
・First gate oxide film, 22...First polycrystalline silicon film, 23...Second gate oxide film, 24...
...Second polycrystalline silicon film, 25...Silicide film (word line), 26...Word line, 2
7...Floating gate electrode, 28...Control gate electrode, 29...Bit line.

Claims (1)

[Claims] (1) In a semiconductor integrated circuit having element isolation in which an insulator is embedded in a groove selectively formed on the surface of a semiconductor substrate, the insulator is composed of two layers of insulators made of different materials; (2) The semiconductor integrated circuit is characterized in that the insulator in contact with the inner wall of the groove among the insulators in the layer forms the sidewall. (2) The two insulator layers are silicon oxide films (SiO
_2) and boron-containing phosphorous glass (BPSG), the semiconductor integrated circuit according to claim 1.