JPH11354737A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit the retreat of a silicon oxide film on a silicon substrate. SOLUTION: The manufacture of the semiconductor device has a process in which a silicon oxide film 12, a silicon nitride film 13 and a TEOS film 14 are formed onto a silicon substrate 11, a process in which the silicon oxide film 12, the silicon nitride film 13 and the TEOS film 14 are etched in a specified shape, a process in which the silicon substrate 11 is etched while using the TEOS film 14 as a mask and trenches 15 are shaped, a process in which a reaction product in the trenches 15 is removed by using a wet etching method, and a process in which the silicon film 12 selectively growing only on silicon is formed to sections, from which the surfaces of the silicon substrates 11 are exposed, in the trenches 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a trench capacitor.

[0002]

2. Description of the Related Art A DRAM is composed of a capacitor for storing charges serving as storage information and a MOSFET serving as a switch for controlling the transfer of charges. Along with the high integration of DRAM devices, miniaturization of memory cells is required, but this also reduces the capacitor area. Therefore, it is important to secure the capacitance of the capacitor in this narrow area. Therefore, a trench type cell using a trench capacitor is known as one in which the capacitor area is increased by making the capacitor structure three-dimensional.

Here, a conventional method for forming a trench for a trench capacitor will be described with reference to the drawings (FIGS. 1 and 2).

First, as shown in FIG. 1, a silicon oxide film 2 is formed on an upper surface of a silicon substrate 1 by using a thermal oxidation method. Then, a silicon nitride film 3 is formed on the upper surface of the silicon oxide film 2 by using the CVD method. Further, a TEOS film 4 is formed on the upper surface of the silicon nitride film 3 by using the CVD method. Next, a resist (not shown) is formed on the upper surface of the TEOS film 4 using a spin coating method, and the resist is patterned into a predetermined shape by a photolithography method. Using this resist as a mask, TE is formed using an anisotropic etching method, for example, RIE method.
The OS film 4, the silicon nitride film 3, and the silicon oxide film 2 are removed. Here, the silicon oxide film 2 is used as an adhesive layer for bonding the silicon substrate 1 and the silicon nitride film 3.

[0005] Next, as shown in FIG.
Is used as a mask, the silicon substrate 1 is removed using an anisotropic etching method, for example, an RIE method, and a trench 5 is formed. Thereafter, the TEOS film 4 is removed using a hydrofluoric acid-based wet etching method.

[0006]

When the trench 5 is formed by the conventional technique as described above, the silicon oxide film 2 is etched even during wet etching for removing a reaction product, and is slightly recessed. (See FIG. 2).

Further, during the wet etching for removing the TEOS film 4, the silicon oxide film 2 is etched and receded from the side surface of the trench (see FIG. 2).

After that, hydrofluoric acid-based wet etching is repeatedly performed to remove the natural oxide film formed on the surface of the trench 5, but also in this case, the retreat of the silicon oxide film 2 proceeds. Will be.

For this reason, there is a disadvantage that the adhesive force between the silicon substrate 1 and the silicon nitride film 3 is weakened, and the silicon nitride film 3 is peeled off. In addition, the silicon oxide film 2 may recede and may be completely removed.

The present invention has been made in view of the above problems, and has as its object to suppress the retreat of the silicon oxide film 2 on the silicon substrate 1.

[0011]

According to the present invention, a step of forming a silicon oxide film on an upper surface of a silicon substrate, a step of forming a silicon nitride film on an upper surface of the silicon oxide film,
Forming a TEOS film on the upper surface of the silicon nitride film, etching a portion of the silicon oxide film, the silicon nitride film, and the TEOS film to expose a portion of the surface of the silicon substrate; Forming a trench by etching the silicon substrate using a TEOS film as a mask; removing a reaction product in the trench by using a wet etching method; and forming only a silicon on the surface of the trench. Forming a selectively grown silicon film.

According to the present invention, by employing the above-described structure, it is possible to suppress the receding of the silicon oxide film on the silicon substrate when the wet etching process is performed in a subsequent step.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS.
This will be described with reference to 6).

First, as shown in FIG. 3, a silicon oxide film 12 is formed to a thickness of about 8 nm on the upper surface of a silicon substrate 11 by using a thermal oxidation method. And the silicon oxide film 1
A silicon nitride film 13 is formed to a thickness of about 220 nm on the upper surface of the substrate 2 by using the CVD method. Further, the upper surface of the silicon nitride film 13 is formed on the upper surface of the silicon nitride film 13 by using a CVD method.
EOS film 14 (tetra-ethl-ortho-sillicate) with a thickness of 7
It is formed to a thickness of about 00 nm. Next, using the spin coating method,
A resist (not shown) is applied to the upper surface of the TEOS film 14.
This resist is patterned into a predetermined shape by using photolithography. Using this patterned resist as a mask, anisotropic etching, for example, RIE
The EOS film 14, the silicon nitride film 13, and the silicon oxide film 12 are removed, and a part of the upper surface of the silicon substrate 11 is exposed. Next, the resist (not shown) is removed by ashing.

Next, as shown in FIG.
4 is used as a mask to etch the silicon substrate 11 using an anisotropic etching method, for example, an RIE method.
5 is formed. Then, a reaction product generated in the trench 15 is removed by a hydrofluoric acid-based wet etching method. At this time, the silicon oxide film 12 facing the trench 15 is also etched, and the exposed side surface is slightly receded.

Next, as shown in FIG.
Using a method, a silicon film 16 is formed only on the surface of the silicon substrate 11 at the portion where the surface of the silicon substrate 11 is exposed. The selective CVD method used here utilizes a time difference between a time until the silicon film 16 starts to be formed on the silicon substrate 11 and a time when the silicon film 16 starts to be formed on another film. At this time, it is best to fill the portion (see FIG. 4) of the silicon oxide film 12 that has receded by hydrofluoric acid-based wet etching.
However, it does not have to be completely buried.

Next, as shown in FIG. 6, a TEOS film 14 is formed by a hydrofluoric acid-based wet etching method under conditions that allow the silicon nitride film 13 and the silicon substrate 11 to have selectivity.
Is removed. Here, when the TEOS film 4 is removed by the conventional technique, the silicon oxide film 2 is largely retreated, the adhesive strength between the silicon substrate 1 and the silicon nitride film 3 is weakened, and the silicon nitride film 3 is peeled off. was there. In addition, the silicon oxide film 2 may recede and may be completely removed (see FIG. 2). In contrast,
According to this embodiment, when removing the reaction product in trench 15, silicon oxide film 12 is slightly retracted. However, since the silicon oxide film 12 is covered with the silicon film 16 (silicon substrate 11), the silicon oxide film 12 does not recede in the step of removing the TEOS film 14 (see FIG. 6). In the subsequent steps, the trench 1
The wet etching process is repeated several times in order to remove a natural oxide film (not shown) formed in 5. Also in this case, since the silicon oxide film 12 is covered with the silicon film 16 (silicon substrate 11), it does not recede.
Therefore, the retreat of the silicon oxide film 12 on the silicon substrate 11 can be suppressed as compared with the related art.

Next, as shown in FIG. 7, a film containing impurities, for example, an AsSG (Arsenic Silicate Glass) film 1
7 is formed on the entire surface by CVD, and a resist 33 is formed on the entire surface by spin coating so that the trench 15 is completely filled. Then, a part of the AsSG film 17 is exposed by exposing and developing the resist 33.
How much is exposed depends on where the buried plate is to be formed. Further, the exposed AsSG film 17 is removed using, for example, a hydrofluoric acid-based wet etching method. Here, the film containing the impurity is not limited to the AsSG film 17 but may be any film containing the impurity and having a high etching selectivity with respect to the silicon substrate 11.

Next, as shown in FIG.
The resist 33 in the inside is removed by ashing, and for example, a TEOS film 19 is formed on the entire surface by using the CVD method.

Next, as shown in FIG. 9, As contained in the AsSG film 17 is diffused to the side surfaces of the trench 15 by a thermal diffusion method. Thereby, the burying plate 19 is formed. Here, when the TEOS film 18 diffuses As, the As
This is for preventing the side surface 5 from entering the silicon substrate 11 from a portion where the AsSG film 17 is not formed. Further, the AsSG film 17 and the TEOS film 1 formed in the trench 15 by wet etching.
8 is removed. When As is diffused by the thermal diffusion method, an exposed portion of the silicon substrate 11 in the trench 15 is oxidized. Thereafter, the oxidized portion is removed, so that the side surface of the trench 15 is slightly retreated.

Next, as shown in FIG. 10, a dielectric film 20 made of, for example, an NO film (a laminated film composed of a silicon nitride film and a silicon oxide film) is formed to a thickness of 8 nm by the CVD method.
Formed to the extent. Next, a conductive film 21 made of, for example, a doped polycrystalline silicon film is
Is formed so as to be filled. Thereby, a capacitor is formed. Here, in the conventional technique (see FIG. 2), an oxide film (not shown) is formed on the side surface of the trench 5 by oxidation when As is diffused into the silicon substrate 1 by a thermal diffusion method. By removing the oxide film (not shown), the side surfaces of the trench 5 recede. Therefore, when a conductive film (not shown) is formed in the trench 5 by using the CVD method thereafter, there is a disadvantage that a cavity is formed in the center of the trench 5. On the other hand, according to this embodiment, since the silicon film 16 is formed in the exposed portion of the silicon substrate 11 (see FIG. 5), the diameter of the trench 15 is smaller than the diameter of the silicon nitride film 13. Is also getting smaller. Therefore, even if the side surface of the trench 15 is slightly retreated, the side surface of the trench 15 does not retreat from the side surface of the silicon nitride film 13. Therefore, CVD
Even when the conductive film 21 is formed in the trench 15 by using the method, it is possible to prevent a cavity from being formed in the center of the trench 15.

Next, as shown in FIG. 11, the upper surface of the silicon nitride film 13 is flattened by using a CMP method (Chemical Mechanical Polish). Then, using the silicon nitride film 13 as a mask, an anisotropic etching method such as RIE
The conductive film 21 is etched to a predetermined depth using a method. Thereby, a part of the dielectric film 20 is exposed. After that, the exposed dielectric film 20 is removed using, for example, a phosphoric acid-based wet etching method or the like.

Next, as shown in FIG. 12, an insulating film 22 made of, for example, a TEOS film is formed on the entire surface by using the CVD method. This insulating film is for preventing the occurrence of a parasitic transistor, and needs to have a sufficient film thickness. Then, using an anisotropic etching method, for example, an RIE method,
The insulating film 22 is left only on the side surfaces of the trench 15.

Next, as shown in FIG. 13, a conductive film 23 made of, for example, a doped polycrystalline silicon film is formed by CVD so that the trench 15 is filled. Here, similarly to the step of forming the conductive film 21 (see FIG. 10), since the silicon film 16 is formed on the exposed portion of the silicon substrate 11 (see FIG. 5), the diameter of the trench 15 is reduced. It is smaller than the diameter of the silicon nitride film 13. Therefore, even if the side surface of the trench 15 is slightly receded, the diameter of the silicon nitride film 13 does not become larger than the diameter of the trench 15. Therefore, even when the conductive film 23 is formed in the trench 15 by using the CVD method, it is possible to prevent a cavity from being formed in the center of the trench 15.

Next, as shown in FIG. 14, the upper surface of the silicon nitride film 13 is flattened by a flattening process such as a CMP method. Then, the conductive film 23 is etched to a predetermined depth in the trench 15 by a downflow etching method. Furthermore, using a wet etching method,
The insulating film 22 is etched to a predetermined depth in the trench 15.

Next, as shown in FIG. 15, a conductive film (not shown) is formed in the trench 15, and the upper surface of the silicon substrate 11 is etched into a predetermined shape. Then, a TEOS film 24 is formed on a predetermined portion of the silicon substrate 11.
Next, after removing the silicon nitride film 13 and the silicon oxide film 12, a gate oxide film 35 is formed by using a thermal oxidation method. Further, a polysilicon film 2 having a thickness of about 100 nm
5. A tungsten silicide film 2 having a thickness of about 55 nm
6. A silicon nitride film 27 having a thickness of about 150 nm is formed in a predetermined shape. The polysilicon film 25, the tungsten silicide film 26, and the silicon nitride film 2
7 becomes a gate electrode. Further, a diffusion layer 28 is formed by injecting and activating an impurity on a portion of the upper surface of the silicon substrate 11 where the polysilicon film 25 is not formed. Further, an insulating film, for example, a silicon nitride film 34 is formed to a thickness of about 30 nm on the entire surface by using the CVD method.

Next, as shown in FIG. 16, a BPSG (Bo
ron-doped Phospho-Silicate Glass) film 29 and BPS
TEOS film 3 having a thickness of about 300 nm from the upper surface of G film 29
0 is formed and etched into a predetermined shape. Further, a polysilicon film 31 serving as a contact and a tungsten film 32 serving as a wiring are formed in a predetermined shape. As described above, the semiconductor device DRAM is manufactured by electrically connecting the diffusion layer 28 and the conductive film 21 and forming the information transfer transistor on the silicon substrate 11. Here, the configuration of the DRAM shown in FIG. 16 will be described. The capacitor is formed by sandwiching the dielectric film 20 between the buried plate 19 and the conductive film 21. The conductive film 21 is electrically connected to or insulated from the polysilicon film 31 by the gate electrode 36 of the transistor via the conductive film 23 and the diffusion layer 28. This polysilicon film 31 is electrically connected to a tungsten film 32 which is a wiring.

As described above, according to this embodiment,
Recession of the silicon oxide film 12 on the silicon substrate 11 can be suppressed. Also, when the conductive film 21 is formed in the trench 15 by using the CVD method (see FIGS. 10 and 13), it is possible to prevent a cavity from being formed in the center of the trench 15.

[0029]

As described above in detail, according to the present invention, it is possible to suppress the receding of the silicon oxide film on the silicon substrate.

[Brief description of the drawings]

FIG. 1 is a process sectional view relating to a conventional trench forming method.

FIG. 2 is a process sectional view relating to a conventional method for forming a trench.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 6 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 7 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 8 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 9 is a cross-sectional view of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 11 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 12 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 13 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 14 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 15 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention;

FIG. 16 is a sectional view showing a manufacturing step of the semiconductor device according to the embodiment of the present invention;

[Explanation of symbols]

 1 .... silicon substrate . . . 2. Silicon oxide film . . . 3. Silicon nitride film . . . 4. TEOS film . . . Trench 11. . . . Silicon substrate 12. . . . Silicon oxide film 13. . . . Silicon nitride film 14. . . . TEOS film 15. . . . Trench 16. . . . Silicon film 17. . . . AsSG film 18. . . . TEOS film 19. . . . Embedded plate 20. . . . Dielectric film 21. . . . Conductive film 22. . . . Insulating film 23. . . . Conductive film 24. . . . TEOS film 25. . . . Polysilicon film 26. . . . Tungsten silicide film 27. . . . Silicon nitride film 28. . . . Diffusion layer 29. . . . BPSG film 30. . . . TEOS film 31. . . . Polysilicon film 32. . . . Tungsten film 33. . . . Resist 34. . . . Silicon nitride film 35. . . . Gate oxide film 36. . . . Gate electrode

Claims (4)

[Claims] A step of forming a first oxide film on an upper surface of the semiconductor substrate; a step of forming a first insulating film on the upper surface of the first oxide film; Forming a second oxide film, and exposing a portion of the upper surface of the semiconductor substrate by etching a portion of the first oxide film, the first insulating film, and a portion of the second oxide film. Forming a trench by etching the semiconductor substrate using the second oxide film as a mask; and removing a reaction product in the trench by using a wet etching method. A step of forming a semiconductor film at least in a portion where the first oxide film has receded by the reaction product removing step; a step of diffusing impurities into the substrate from a predetermined side surface of the trench; The method of manufacturing a semiconductor device including a step of forming a dielectric film on the side surface to a depth of, and forming a conductive film on the trench. 2. The semiconductor device according to claim 1, wherein said semiconductor substrate is made of silicon, and said semiconductor film is made of silicon.
2. The method for manufacturing a semiconductor device according to 1. 3. A step of forming a first oxide film on an upper surface of a semiconductor substrate, a step of forming a first insulating film on an upper surface of the first oxide film, and a step of forming a first insulating film on the upper surface of the first insulating film. Forming a second oxide film, and exposing a portion of the upper surface of the semiconductor substrate by etching a portion of the first oxide film, the first insulating film, and a portion of the second oxide film. Forming a trench by etching the semiconductor substrate using the second oxide film as a mask; and removing a reaction product in the trench by using a wet etching method. A step of forming a semiconductor film at least in a portion where the first oxide film recedes by the reaction product removing step; a step of removing the second oxide film; and a step of removing impurities from a predetermined side surface of the trench into the substrate. Diffused Forming a dielectric film on at least a side surface of the trench; forming a first conductive film up to a first depth of the trench; and reducing the dielectric film to approximately the first depth. Removing, forming a second insulating film on a portion of the side surface of the trench where the dielectric film is not formed, and removing at least the substrate from an upper surface of the first conductive film in the trench. Forming a second conductive film up to the upper surface; electrically connecting a predetermined diffusion layer to the second conductive film; forming an information transfer transistor on the one-conductivity-type semiconductor substrate A method for manufacturing a semiconductor device comprising: 4. The method according to claim 3, wherein the semiconductor substrate is made of silicon, and the semiconductor film is made of silicon.