JPH03167980A - Synchronizing correction circuit - Google Patents

Abstract

PURPOSE:To relieve the fluctuation of a screen generated during the period reduction by providing a vertical synchronizing signal insertion device to a period reduction circuit and inserting the vertical synchronizing signal to a preceding position below the quantity reducing the period than the position of the vertical synchronizing signal of an original video signal. CONSTITUTION:The vertical synchronization period of a reference signal when a video signal from a memory 3 is read is reduced by a command of a microcomputer 8. The reduction command form the microcomputer 8 is fed to a vertical synchronizing signal insertion device 10 together with a reference signal when the video signal is read from the memory 3 generated from a reference signal generating circuit 9. A new vertical synchronizing signal is inserted to a preceding position than the original vertical synchronizing signal by the quantity below the reduction quantity at the period reduction with a command of the microcomputer 8 by a vertical synchronizing signal insertion device 10 to the video signal read from the memory 3 from the memory controller 4. Thus, the most stable pattern without fluctuation is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is directed to a VCR (Video Cassette).
e Recorder) and video discs, etc.
The present invention relates to a synchronization correction circuit that synchronizes images when a video signal is stored in a memory, read out and outputted, and is switched between a still image and a moving image.

(Conventional technology) Recent years. Many VCRs and video discs now have a special playback method that allows them to output still images using memory. FIG. 3 is a schematic diagram of an example of a device that outputs still images and moving images by switching between them.

In the figure, the video signal applied from the input terminal is A/D
It is converted into a digital signal by the converter 2 and written into the memory 3 by the memory control device 4. Here, it is assumed that the memory 3 is a field memory in which data is written for each field of the video signal. memory 3
The video signal data written to the memory controller 4 is read out when necessary. D/A converter 5
A controller (hereinafter referred to as a microcomputer) controls a system such as a player by converting it back to an analog signal and inputting it to one input of the signal changeover switch 6, and applying the video signal from the input terminal 1 directly to the other input. 8, the switching of the signal changeover switch 6 is selected, and a video signal of a reproduced image or a still image is output from the output terminal 7. On the other hand, the memory control device 4 has a reference signal generation circuit 9.
from the reference signal (hereinafter referred to as
A reference signal for reading (hereinafter referred to as a read start signal) is formed.
Writes and reads video signals to and from memory 3. Figure 4 is a waveform diagram showing an example of a video signal. For example, if there is a video signal (approximately 1 field) as shown in FIG. 2(a), a write start signal (FIG. 2(b)) is sent from the reference signal generation circuit 9. Since this write start signal is formed from the vertical synchronization signal of the video signal, it is a signal that lags behind the vertical synchronization signal of the video signal. A synchronization signal is written at the end. On the other hand, reading is performed using a signal having an accurate vertical synchronization signal period as shown in FIG. 3(c), and a video signal (FIG. 3(d)) is periodically outputted from the memory 3 in accordance with the read start signal. In this case, since it is a field memory, it is generally controlled by the memory control device 4 so that the horizontal and vertical synchronization signals of the video signal to be read out are continuous. As mentioned above, the video signal is output as a still image for each field from the memory 3, but when switching to a direct playback image from the input terminal 1, the playback image is vertical synchronization of memory output and memory output is required. Conventionally, the period of the read start signal, which is the reference for reading from the memory 3, is reduced by a certain amount for each field, and the period of vertical synchronization of the video signal read from the memory 3 is shortened. Image switching is performed by shortening the memory output video signal until the vertical synchronization signals of the reproduced image and still image match each other. This method is especially useful for CL of video discs.
V (Constant Linear Velocity)
y: constant linear velocity) This is an effective method for special reproduction of discs. (Problem to be solved by the invention) However, in the conventional synchronization correction method as described above,
If you shorten the period of the vertical synchronization signal of the video signal read from memory, the time difference between the vertical synchronization signal of the video signal and the video signal appearing on the TV will be shortened, so the video signal portion will be pulled up on the TV screen. This has the disadvantage that the screen shakes and the timing of synchronization can be clearly seen, and in particular, it makes subtitles and fixed lines in the video look unsightly. Furthermore, depending on the amount of shortening of the vertical synchronization signal period mentioned above, the original vertical synchronization signal written at the end of the memory may not be read out in its complete form, resulting in a narrower width. The disadvantage is that vertical synchronization is disturbed.

An object of the present invention is to provide a synchronization correction circuit that reduces the shaking of a television screen caused by the conventional synchronization as described above and eliminates vertical synchronization disturbance. (Means for Solving the Problems) The present invention has the above-mentioned objects, a memory, a memory control device for writing to and reading from the memory, and a reference signal generation circuit for reading a video signal from the memory and generating a reference signal with a variable period. and a vertical synchronization signal insertion device for inserting a vertical synchronization signal into the taste image signal read out from the memory, and the vertical synchronization period of the video signal read out from the memory is the horizontal synchronization period m (m is any positive value). When the video signal is shortened by a number of times, the vertical synchronization signal position of the shortened video signal is moved to a position that is n times the horizontal synchronization signal period (where n (m, n is a positive number) times). , by inserting a vertical synchronization signal. (Function) According to the present invention, the video signal read from the memory,
When performing vertical synchronization with an external playback video signal, it is possible to reduce the shortening of the time from the vertical synchronization signal of the video signal with a shortened vertical synchronization cycle to the video signal appearing on the TV screen, so that the screen This has the effect of reducing shaking. (Example) Hereinafter, the present invention will be explained in detail using the drawings.

The second engineering drawing is a block diagram showing the configuration of an embodiment of the present invention.
The video signal applied to the input terminal 1 is converted into a digital signal by the A/D converter 2, and the memory control device 4 controls writing to or reading from the memory 3, and the read video signal is converted into a vertical synchronization signal. After passing through the insertion device 10, the signal is returned to an analog signal by the D/A converter 5. The output of this D/A converter 5 is used as one input of the signal changeover switch 6, and the video signal is directly applied from the input terminal 1 to the other input, and the reproduced image and the still image read out from the memory are connected. It is switched and output. The memory control device 4 is also supplied with a reference signal for writing a video signal from the reference signal generation circuit 9 and a reference signal for reading a video signal from the memory 3, and performs data writing or reading operations from the memory 3. I do.

The reference signal generation circuit 9 described above shortens the vertical synchronization period of the reference signal when reading the video signal from the memory 3 in response to a command from the microcomputer 8 that controls this system. The shortening command from the microcomputer 8 is applied to the vertical synchronization signal insertion device 10 together with the reference signal generated by the reference signal generation circuit 9 when reading the video signal from the memory 3.

The present invention has the above-described configuration. First, a video signal applied from the input terminal 1 is converted into a digital signal by the A/D converter 2, and a vertical synchronization signal is converted by the memory control device 4 as in the conventional example. Finally, the video signal part is written to memory 3. The read timing is
The vertical synchronization signal period is determined by the read start signal of the vertical synchronization signal period generated by the reference signal generation circuit 9, and is read out for each field data. Usually, the vertical synchronization signal period and There is a regular time difference between the vertical synchronization signal and the signal containing the image part. However, when switching between the reproduced image signal and the memory signal, it is necessary to synchronize, so the microcomputer 8 causes the reference signal generation circuit 9 to shorten the period of the readout start signal.
A command to shorten the vertical synchronization period of the video signal is sent, but if this continues, the readout will be as shown in Figure 2(c), and as the start signal is shortened, the reading will be as shown at point A in Figure 2(d). The time between the synchronization part and the image part of the output video signal is shortened by the shortened amount, and the image becomes unstable. 10, a new vertical synchronizing signal is inserted at a position before the original vertical synchronizing signal by an amount equal to or less than the shortening amount at the time of cycle shortening, according to a command from the microcomputer 8. In other words, if the amount of shortening is mH, which is m times the horizontal synchronizing signal period (hereinafter referred to as H), the shortening amount is less than mH, which is less than the shortening amount of the readout signal, taking into consideration the transient response of the vertical scanning circuit of the television. Insert vertical synchronization signal by shortening amount. Its insertion position is especially 2Q
For the amount of H shortening, inserting a new vertical synchronization signal before half the QH provides the most stable screen with no shaking.

As can be seen from the detailed explanation of the present invention using the examples above, the newly inserted vertical synchronization signal improves the time difference with the signal of the image part compared to the original relationship, and also The response can be made smoother, thereby reducing the shaking when the cycle is shortened on the TV screen, allowing smooth switching between playback images and still images, and eliminating disturbances in synchronization.

Note that when a new vertical sync signal is inserted, there will be two vertical sync signals, but this is not a problem since TVs generally do not respond to later vertical sync signals. ! 110 allows the subsequent vertical synchronization signal to be deleted.

Further, although the vertical synchronization signal insertion device 10 is provided before the D/A converter 5, it may be provided after the D/A converter 5, and similarly, the signal changeover switch 6 is provided before the D/A converter 5. The same effect can be obtained even if the reproduced image is a digital signal. Furthermore, if the vertical synchronization signal insertion device 10 operates at the same time as period shortening, it will not affect normal operation in any way, and in addition, the vertical synchronization signal insertion device 10 inserted by the device of the present invention will not affect the normal operation. The signal can be easily formed from a signal generated before the start pulse read out from the reference signal generation circuit 9. Note that depending on the amount of shortening, the original vertical synchronization signal may be missing or its width may be reduced, but if the vertical synchronization signal insertion device 10 is configured to correct the vertical synchronization signal even in such a case, the synchronization signal can be corrected. Good images can be obtained without any disturbance. As described above, the present invention provides a vertical synchronization signal insertion device to insert a new vertical synchronization signal into the video signal read from the memory before the position of the original vertical synchronization signal by an amount less than the amount of shortening. By inserting it, synchronization with the playback image will be improved and shaking on the screen will be reduced. (Effects of the Invention) As is clear from the above explanation, the present invention shortens the period of the vertical synchronizing signal of the video signal read from the memory, and when performing synchronization with a reproduced picture having a different phase, the period shortening circuit is used vertically. By providing a synchronization signal insertion device and inserting a vertical period signal before the position of the vertical synchronization signal of the original video signal by a value less than or equal to the amount by which the period is shortened, This has the effect of reducing screen shake.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a signal waveform diagram explaining the operation of FIG. 1, and FIG. 3 is a block diagram showing the configuration of a conventional synchronization correction circuit. Figure 4 is a waveform diagram explaining Figure 3. 3...Memory, 4...Memory control device, 9...Reference signal generation circuit. 10...
Vertical synchronization signal insertion device.

Claims (1)

[Claims] A memory for storing a video signal, a memory control device for writing to and reading from the memory, a reference signal generating circuit capable of changing a reference signal period for reading the video signal from the memory, and a reference signal generating circuit for reading the video signal from the memory, and a vertical synchronization signal insertion device for inserting a new vertical synchronization signal, the period of the reference signal generated by the reference signal generation circuit is shortened by m times (m is a positive number) the period of the horizontal synchronization signal. , when the vertical synchronization period of the video signal read from the memory is shortened by m times the horizontal synchronization period, from the position of the vertical synchronization signal of the shortened video signal, n of the horizontal synchronization signal (where n is A synchronization correction circuit characterized in that the vertical synchronization signal insertion device inserts a new vertical synchronization signal at a position which is a positive number and is advanced by a period of n<m.