JPH03165182A - Signal processing circuit for solid-state image pickup element - Google Patents

Abstract

PURPOSE:To attain high quality horizontal contour emphasis processing without cross color disturbance by synthesizing plural outputs obtained via 1st and 2nd delay circuits having at least one digital delay means whose delay time is nearly equal to one horizontal scanning period by means of 1st and 2nd synthesis means. CONSTITUTION:A 1st synthesis means 23 synthesizes plural outputs from a 1st delay circuit 21 having at least a digital delay means whose delay time is nearly equal to one horizontal scanning period as to a green picture pickup signal in each digital output signal of an analog digital conversion means to limit a vertical direction band. Moreover, a 2nd synthesis means 24 synthesizes plural outputs from a 2nd delay circuit 22 as to a red picture pickup signal, a blue picture pickup signal or a synthesis signal of both the color signals similarly to limit the vertical band. Then an adder means 25 adds outputs of the 1st and 2nd synthesis circuits equally and uses the result as a horizontal detail signal, which is outputted via a digital filter means 26. Thus, the image enhancement processing is implemented in an excellent way without cross color disturbance.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Application Field The present invention digitizes an imaging output signal from a solid-state image sensor for generating video signals, and forms detail signals for image enhancement processing by digital signal processing. Regarding the signal processing circuit of the solid-state imaging device, in particular, the solid-state image sensor for green image sensing, the solid-state image sensor for red image sensing, and the solid-state image sensor for blue image sensing are spatially separated by 1/2 of the repetition pitch of each pixel. The present invention relates to a signal processing circuit of a solid-state imaging device that employs a so-called spatial pixel shifting method in which the pixels are arranged in a shifted manner in the imaging section.

B. Summary of the Invention The present invention is a so-called system in which a solid-state image sensor for capturing a green image, a solid-state image sensor for capturing a red image, and a solid-state image sensor for capturing a blue image are spatially shifted by I/2 of the repeat pinch of each pixel. A signal processing circuit for a solid-state imaging device that digitizes the imaging output signal from each solid-state image sensor from an imaging unit that employs a spatial pixel shifting method and forms a detail signal for image enhancement processing through digital signal processing. In the above, the delay time is 1 for the digital output signal obtained by digitizing each imaging output signal read out from each solid-state image sensor.
A first delay circuit having at least one digital delay means approximately equal to the horizontal scanning period provides the above-mentioned delay time to the green image pickup signal of the F digital output signals, and synthesizes the signal in the first synthesis circuit. , a second delay circuit which limits the vertical band of the recorded color image signal and has at least one digital delay means whose delay time is approximately equal to one horizontal scanning period allows one of the digital output signals to be The red image imaging signal, the blue image imaging signal, or the composite signal of both signals is given the delay time and synthesized by the second combining means, thereby producing the red image imaging signal, the blue image imaging signal, or the composite signal of both signals. By limiting the vertical band of the signal, adding the outputs of the first and second combining means in equal amounts using the adding means, and outputting the result as a horizontal detail signal through the digital filter means, the possibility of cross color interference is eliminated. In this embodiment, it is possible to obtain a horizontal detail signal that has a small amount of noise and can perform good image enhancement processing on image signals of each color.

C Conventional technology Charge coupled device (CCD)
In a solid-state imaging device that uses a solid-state image sensor having a discrete pixel structure formed by a device, etc. as an imaging section, the solid-state image sensor itself is a sampling system, so the diagonal lines in Fig. 12 are used. As shown, an aliasing component from the spatial sampling frequency [S is mixed into the imaging output signal from the solid-state imager.

Conventionally, by providing a birefringent optical low-pass filter in the single-image optical system and suppressing the high frequency side of the baseband component of the imaging signal, it has been possible to satisfy the Nyquist condition of the sampling system using the solid-state image sensor described in (g). In this way, generation of aliasing components to the baseband of the imaging output signal is prevented.

In addition, in a color television camera device, the green image 1
A two-dimensional solid-state imaging device that images a three-primary color image using a solid-state image sensor provided with a solid-state image sensor for one image and a color coding filter for red pixels and blue pixels;
2. Description of the Related Art Multi-plate solid-state imaging devices such as a three-plate type that capture images of three primary colors using individual solid-state image sensors have been put into practical use.

Furthermore, as a method for improving the resolution in the -F multi-plate solid-state imaging device, for a solid-state image sensor for green image imaging,
A so-called spatial pixel shift 1.7 method is known in which the solid-state image sensors for red and blue images are shifted by /2. By employing this spatial pixel shifting method, an analog output multi-plate solid-state imaging device can achieve high resolution that exceeds the limit of the number of pixels of a solid-state image sensor.

In addition, standardization of the so-called Di/D2 format is underway for professional digital video tape recorders used at broadcasting stations, etc., and color television cameras are the digital interface for digital video-related equipment that conforms to these standards. It is also required for equipment. In the standard for the digital interface for the digital video-related equipment, the sampling rate is set to about the sampling rate f of the current solid-state image sensor.

Furthermore, in general, in order to improve image quality in television camera devices, etc., gamma correction processing is performed on the imaging output signal obtained by the imaging unit, or a detail signal is formed from the imaging output signal and added to the original signal. I am trying to perform image enhancement processing for compositing.

D Problems to be Solved by the Invention By the way, as mentioned above, for a solid-state image sensor for capturing green images, 1/2 of the spatial sampling period of picture elements is
In a solid-state imaging device equipped with an imaging unit that employs the so-called spatial pixel shifting method, in which solid-state image sensors for red and blue images are arranged spatially shifted, digital signals are used for imaging output signals. When a detail signal is formed through processing and the image enhancement processing is performed, aliasing components included in the detail signal cause deterioration of image quality. In addition, cross-color interference occurs when the horizontal detail signal formed from the imaging output signal mixes into the color subcarrier frequency domain, and the mixed component of the horizontal detail signal into the color subcarrier frequency domain degrades image quality. cause it to happen.

Therefore, in view of the above-mentioned problems, the present invention provides a solid-state image sensor for capturing a green image, a solid-state image sensor for capturing a red image, and a solid-state image sensor for capturing a blue image spatially by 1/2 of the repetition pitch of each pixel. An object of the present invention is to enable image enhancement processing using a horizontal detail signal to be performed satisfactorily without cross-color interference in a solid-state imaging device that employs a so-called spatial pixel shifting method in which pixel elements are arranged at different angles. The present invention aims to provide a signal processing circuit for a solid-state imaging device that eliminates aliasing components included in detail signals and prevents occurrence of cross color interference due to mixing of horizontal detail signals into the color subcarrier frequency range. be.

Eil! Means for Solving the Problem In order to achieve the above-mentioned object, the present invention provides a solid-state image sensor for capturing a green image, a solid-state image sensor for capturing a red image, and a solid-state image sensor for capturing a blue image. analog-to-digital conversion means for digitizing each imaging output signal read from each of the solid-state image sensors of the imaging unit arranged spatially shifted by 1/2;
a first delay circuit having at least one digital delay means whose delay time is approximately equal to one horizontal scanning period, and to which a green image continuous image signal is supplied from among the digital output signals of the analog-to-digital conversion means; It has at least one digital delay means whose delay time is approximately equal to one horizontal scanning period, and among the digital output signals of the analog-to-digital conversion means described in F, a red image imaging signal, a blue image imaging signal, or a composite signal of both signals. a second delay circuit to which a second delay circuit is supplied; and a first synthesizing means for synthesizing a plurality of outputs from the first delay circuit to limit a vertical band of the human input signal to the first delay circuit; , a second synthesizing means for synthesizing a plurality of outputs from the second delay circuit and limiting a vertical band of an input signal to the second delay circuit; and the first and second synthesizing means. , and digital filter means to which the output of the addition means is supplied, and a horizontal detail signal is obtained from the output of the digital filter means. be.

F action In the signal processing circuit of the solid-state imaging device according to the present invention, the solid-state image sensor for green image sensing, the solid-state image sensor for red image sensing, and the solid-state image sensor for blue image sensing are spaced apart by 1/2 of the repetition pitch of each pixel. Each image pickup output signal read from each of the solid-state image sensors of the image pickup section arranged at different positions is digitized by an analog-to-digital conversion means.

The first synthesizing means includes at least one digital delaying means whose a delay time is approximately equal to one horizontal scanning period for the green image imaging signal among the digital output signals of the analog-to-digital converting means described above. The vertical band is limited by combining multiple outputs from the delay circuits.

Further, the second synthesizing means is configured to perform, among the digital output signals of the analog-to-digital converting means, a red image imaging signal, a blue imaging output signal, or a composite signal of both signals.
The vertical band is limited by combining a plurality of outputs from a second delay circuit having a small number of digital delay means whose delay time is approximately equal to one horizontal scanning period.

Then, the adding means adds the outputs of the first and second combining circuits by equal amounts, and outputs the added output signal as a horizontal detail signal via the digital filter means.

G. Embodiment Hereinafter, one embodiment of a signal processing circuit for a solid-state imaging device according to the present invention will be described in detail with reference to the drawings.

Figure 1 shows that the imaging light incident from the image lens (1) via the optical low-pass filter (2) is separated into the three primary color light components of R, C, and H by the color separation prism (3). This figure shows a color television camera device configured by applying the present invention to a three-chip solid-state imaging device that captures three primary color images of a subject using three CCD image sensors (4R), (4G), and (4B). There is.

In this embodiment, the three CCD image sensors (4R), (4G), and (4B) constituting the imaging unit of the color television camera device employ a spatial pixel shifting method to As shown in the figure, a CCD image sensor (4G) for capturing a green image, a CCD image sensor (4R) for capturing a red image, and a CCD image sensor (4B) for capturing a blue image at a spatial sampling period of pixels. They are arranged shifted by 1/2 of τ.

And the above three CCD image sensors (4R),
(4G) and (4B) are driven by a CCD drive circuit (not shown), and the imaging charge of each picture element is read out by a readout clock having a sampling frequency fs of 4 times the color subcarrier frequency rsc, that is, 4"8.

The three CCD image sensors (4R), (4G), and (4B) that employ the above spatial pixel shifting method are used to detect the three primary color images of the subject image.
D image sensor (4G) and each CCD image sensor (4R) for capturing the red image and drawing the blue image,
(4B) spatial sampling is performed at a position shifted by τ1/2. As a result, the above CCD image sensor (4R
), (4G), and (4B), the spectral components of each image pickup output signal S1m+S GelS read out from (4B) are the green image pickup output signal from the CCD image sensor (4G), as shown in FIG. 5GII
The above sampling frequency [S component and each of the above CCD4'
Red image output signal S1. by image sensor (4R), (4B). and the respective sampling frequencies (S component) of the blue imaging output signal Sum are in opposite phase to each other.

Then, each CCD image sensor (4R
), (4G), and (4B), each imaging output signal S11l)ISGth, S1m is,
Buffer Anne 7' (SR), (5c) respectively
, analog/digital (＾/D) via (5B)
Supplied to converters (6R), (6G), and (6B).

Each of these A/D converters (6R), <6G>, (
611), each of the above-mentioned imaging output signals S; + S G11
+S 11) Clock rate equal to the sampling rate of each CCD image sensor (4R)
, (4G), (4B) read clock same as 4f! The clock frequency of c [the clock of S is given by a timing generator (not shown). And each of the above A/D converters (6R).

(6G) and (6B) are each of the above imaging output signals S 1
1 m + S G m l5I1. The above 4f5. The above image pickup output signals S and Y are digitized as they are at a clock rate of fs.

S(, *, each color data of the spectrum and the same output dregs vector shown in Fig. 3 of S1m D R$ + D 6 *,
Form D B*.

The above A/D converters (6R), (6G), (6B
), each color data D@m, D Gll,
D@* is supplied to the signal processing section (7).

As shown in Part 4, the signal processing unit (7) is configured to process the red data D@* obtained by the A/D converter (6R) and the red data D@* obtained by the A/D converter (6R). 6G)
a detail signal generator (11) to which the green data DG11 obtained by is supplied, and the A/D converter (6R)
, (6G), and (6B) are supplied to the interpolation processing unit (13R) through the delay circuits (12R), (12G), and (1211). , (13G) ,
(13B) and these interpolation processing units (131+), (
13G), the interpolated three primary color data D ll*11+ D G1+'jv D @o from (13B) and the detail signal D from the detail signal generator (11).
1°, is supplied to the adder (14R), (14[;
), (14B) and these adders (14R),
Gamma correction processing circuit (15R), (15G), to which the addition output of (14G), (14B) is supplied.
(15B).

In this signal processing section (7), the interpolation processing section (13
R), (13G), (13B) are the above A/D
The three primary color data D at the clock rate fs of 4fse supplied from the converters (6R), (6G), and (6B)
By applying interpolation processing to 111+D o,D@*, the clock rate rs is twice as high as 8'', c
Three primary color data D3. with a clock rate of 2 fs. Yu+D
G**+ D s** is formed. The interpolation processing units (L3R), (13G), and (13B) process the three primary color data D at the clock rate of 2fs. .

D Gii*, Dl*11 are added to the above adder (14+1)
, (14G), (14B). These adders (14R), (14G), (73B) are the interpolation processing units (13R), (13G), (13
Three primary color data D IIIm1 D G**l from B)
Dl. 4. The detail signal from the detail signal generating section (11) is generated. By adding yu, the above 3
Primary color data D@6m, DQ*□D1. , performs image enhancement processing on. This image has been enhanced 3
Primary color data D II*□D,. ID1mm is the gamma correction processing circuit (15R).

(Supply) to (15G) and (15B).

Then, the gamma correction processing circuit (15R), (
15G).

(15B) is the adder (14R), (14G)
, image enhancement processed by (14B) 3
Primary color data D□,.

Gamma correction processing is performed on Dayu, , Dl, , and each color data D that has undergone gamma correction processing. Yu+D G*11+D
Output IIIm.

Further, in this embodiment, the detail signal generating section (11) generates green data D obtained by the A/D converter (6G), as a concrete example of its configuration is shown in FIG. The first delay with input data G! (2
1), and a second delay circuit (22) which uses red data D+1m obtained by the A/D converter (6R) as input data R1, 4.

The first delay circuit (21) includes two IH delay circuits (21a) and (21b) that provide an input signal with a delay time equal to one horizontal scanning period IH using digital delay means such as a D-type flip-flop. are connected in series. This first delay circuit (21) is connected to the A/D converter (6G)
Regarding the green input data GIN supplied from ) is supplied to the interpolation processing section (14G).

Similarly, the second delay circuit (22) uses digital delay means such as a D-type flip-flop to add a delay time equal to one horizontal scanning period IH to the input signal.
It is formed by connecting delay circuits (22a) and (22b) in series. Regarding the red input data RI supplied from the A/D converter (6G), this second delay circuit (22)
The OH delay output R1, the IH delay output R1゜, and the 2H delay output R2゜ are given to the second comb filter (24), and the IH delay output is sent to the delay circuit (13R).
The data is supplied to the interpolation processing unit (1411) via the interpolation processing unit (1411).

The first comb filter (23) processes the green input data Gl+1 supplied from the A/D converter (6G) to the first delay circuit (21).
21) The above three types of delayed outputs from G I NI G
+ Based on HDL+Gt, oL, ω 1 GH= −(2+(ω-1+ω)・GIH),・,■G
V= (2(ω−'10ω) ・G+sl ・”
(DC=ω・GIN...) The filter outputs GH, GV, and DC are given to the mixer circuit (25).

Further, the second comb filter (24) includes the A/D
Regarding the red input data RIM supplied from the converter (6R) to the second delay circuit (22), the delay output RIN+R of the type 31i from the second delay circuit 8 (22)
Based on IHIILI RznoL, RH= □
(2+(ω-1+ω)・R)...■or RH-ω-1・RIM...■or RV=O...■or DR=O...■ Filter output RH , RV, and DR are the mixer circuit (
25).

The mixer circuit (25) receives filter outputs Gll and GVDG from the first comb filter (23).
and the filter outputs RH, RV, and DR from the second comb filter (24), IEH' = GH+
R1-1... [phase] IEI = GV + α-RV (α-0,%, '/!2.1) ...■LEV=
GH+β=RH, -@ or LEV=DG+β・DI'? (β-0,1) . . . The combined outputs IEH', IEV', and LEV are output.

t-, 2 combined output IE from the mixer circuit (25) above
H' is 2fs obtained by multiplexing the filter output GH from the first comb filter (23) and the filter output RH from the second comb filter (24) at a Cronk rate of 2rs and adding them in equal amounts. The signal is supplied to the first digital filter circuit (26) as a Cronk rate horizontal detail signal.

In this way, even in this color television camera device in which the spatial pixel shifting method is adopted in the imaging section, the above A
In the detail signal generating section (11) to which the red data DIll and the green data D and distortion obtained by the /D converters (6R) and (6f;) are supplied, By adding equal amounts of the filter output GH and the filter output RH from the second comb filter (24) in the mixer circuit (25), 1
All the next carrier components are canceled and a wideband horizontal detail signal I EH is generated without aliasing distortion.
' can be formed.

Here, in this color television camera device that employs the spatial pixel shifting method in the imaging section, in addition to adding equal amounts of the green image imaging signal and the red image imaging signal, the green image imaging signal and the blue image 1st Even if the same amount of the image signal is added, or the composite signal of the red image signal and the blue image signal is added by the same amount to the green image signal, all the first-order carrier components are canceled. A wideband horizontal detail signal can be formed without aliasing distortion.

Further, the filter output G■ from the first comb filter (23) and the filter output RV from the second comb filter (24) are mixed by the mixer circuit (25) l:α
The above-mentioned composite output IF':V' added at the ratio of is sent to the second digital filter circuit (2
7).

Furthermore, the filter output GH or DC from the first comb filter (23) and the second:J comb filter 2
4) filter output]? + (or DH) added by mixer circuit (25) in 1-
The combined output LEV is supplied as a level signal to a level dependent signal generation circuit (28).

Then, the above-mentioned composite output I is output from the mixer circuit (25) marked -h.
The first digital filter circuit (which is supplied as a chronocratic horizontal detail signal with EH° of 2 fs)
26), [S has a bypass filter characteristic having at least two or more even number of zeros,
A horizontal detail signal of 2fs rate is formed.

This first digital filter circuit (26) has, for example, a geometric block configuration shown in FIG. l+
(z) = −(z−'+2z−” 1)
... ■The first filter block (41) shown by the transfer function H, (z) of 4, and ■Hz(z) = -(-z-"+2z-'-1)
A second filter block (42) with a transfer function H2(Z) of −−6, and ■ +1:1(Z) = (z−”42z−=+−1)
The third filter block (43) is i′ζ between the transfers of pH H:l (z), and H4(Z) = −(z−′+2z−”l−1)
・-(The fourth filter block represented by the transfer function H4(2) and the weighting coefficient ap, β1.H2,H
3 to ij, each coefficient circuit (45), (46),
(47), (48), and each of the above coefficient circuits (46)
, (47), and (48).

The first digital filter circuit (26) is 2Is
By providing bypass filter characteristics as shown in FIG. 7 to the output IEH' from the mixer circuit (25), × ( 6 ( ( 4 + 22 ■) ' + 2z-" 4-1 ) (2 2 to 2 Z to 1) + (2 Z + 22 + 1) + (Z + 22 1)) ・I E l ( ... ■ p A P −−−−−−−(−z−′+2z−”@−1)
6

Here, the composite output IE from the mixer circuit (25)
I+' is the filter output G11 subjected to vertical band limiting processing by the first comb filter (23), and the filter output RH subjected to vertical band limiting processing by the second comb filter (24). are synthesized by equal ¥ addition, and each of the above comb filters (23) and (24)
As a result, the band is limited in the vertical direction in the two-dimensional frequency space 1- shown in FIG.
As described in L, the first-order carrier component is canceled. The canceling effect of the first-order gear rear component by the above-mentioned equal addition is effective for the high-frequency components of the human-powered image that are only horizontal. By adding equal amounts of the applied filter output GII and the filter output R1+ subjected to vertical band limiting processing by the second comb filter (24), the color can be calculated on the two-dimensional frequency space shown in FIG. There is no unnecessary leakage component into the sub-figure j-wave frequency 5c (I's 1/4) region.

1- synthesis output tE11' from the mixer circuit (25)
When transmitting a composite color image, the color sub-wavelength is 13. The first digital filter circuit (
The horizontal detail signal IE1-1 obtained by band-limiting in the horizontal direction in 26) is not shown in FIG.
4) Unnecessary leakage components into the area are small, and horizontal ring enhancement processing for product 1☆ can be performed without cross color interference.

The filter output IEH from the first digital filter circuit (26) is supplied to the adder (29) as a horizontal detail signal, and the filter output AP is supplied to the first core circuit (30) that performs nonlinear processing. The signal is supplied to the adder (34) via the adder (34).

Further, the second digital filter circuit (27) is
For example, as shown in the 9th episode of the geometrical block configuration, the mixer circuit (25) generates the vertical tail signal IEV' by H+(z) =-(z-"+2z-'+1)
- Select the first filter block (51) that gives the transfer function H+ (z) of □, the filter output signal from this first filter block (51), and the vertical detail signal IEV". a first switching circuit block (52) that switches the filter characteristics by using the first switching circuit block (52); 1)
---A second filter block (53) that provides a transfer function Hz (z) of A second switching circuit block (54) that switches characteristics, a coefficient circuit (55) that multiplies the second selection output No. 18 by this second switching circuit block (54) by a weighting coefficient α, and this coefficient circuit (55).
) to the output signal from H3(Z) −1(1+z”)
- a third filter block (56) that provides a transfer function Hs(z) of @.

This second digital filter circuit (27) uses the above-mentioned comb filter (23), <24) to
= (z-"+2z-'+1) -@
For the above vertical detail signal IEV' at a clock rate of fs given a filter characteristic H(z) of
The filter characteristic H+(z) operates at a processing rate of S and has a zero point at fsc as shown by the dashed line in FIG.
Then, by giving a filter characteristic Hz (z) having a zero point to 2fsc, the transfer function 14° (z) as shown by the solid line during the same cycle is
) Ha(z) = -(z-'+2z-'+1)4 X(z-4+22-z±1) , supplies this vertical detail signal IEV to the adder circuit (29).

Here, the vertical detail signal I EV' is obtained by adding and combining the filter output Cv from the first comb filter (23) and the filter output RV from the second comb filter (24), Each of the above comb filters (2
3) and (24), the band is limited in the vertical direction on the two-dimensional frequency space shown in FIG. 8 above. the second digital filter circuit (27) having two or more zero points near the color subcarrier frequency fic of the composite color video signal;
The vertical detail signal IEV obtained by band-limiting horizontally in the two-dimensional frequency space shown in FIG. It is possible to perform high-quality vertical contour enhancement processing without causing cross-color interference.

The adder circuit (29) operates at a processing rate of 2fs and processes the horizontal detail signal IEH at a clock rate of 2fs supplied from the first digital filter circuit (26) and the second digital filter circuit (27). ) is added to the vertical detail signal IEV at a clock rate of fs supplied from 2 by this adder circuit (29)
The addition output signal at the fs clock rate is sent to the multiplication circuit (32) via the second core circuit (31) that performs nonlinear processing.
).

Further, the level dependent signal generation circuit (28) to which the composite output LE■ from the mixer circuit (25) is supplied as a level signal generates a level dependent signal LD according to the level signal LEV, A multiplication circuit (3
3) to the multiplication circuit (32).

The multiplier circuit (32) receives the level dependent signal LD multiplied by the weighting coefficient by the multiplier circuit (33), and then the adder circuit (29) which processes the level dependent signal LD by the second core circuit (31). The multiplication output signal is supplied to the addition circuit (34).

This addition circuit (34) is connected to the first core circuit (30).
The filter output AP from the first digital filter circuit 8 (25), which has been subjected to non-linear processing according to
Output as *.

The detail signal generator (11) having such a configuration generates the detail signal IE12m at the clock rate of 2 fs.
The above adders (14R) and (14G) to which m is supplied
.

(14B) is the interpolation processing unit (13R), (1
3G).

(13B) 2fs rate three primary color data D *111++ D G1. Image enhancement processing is performed by adding to D Hm*, and the adders (14R), (14G), (14B>
is image enhancement processed three primary color data D 11
m11. D Gm1il D@m* to the above gamma correction processing circuit (15R), (15G), (15B
).

The above gamma correction processing circuit <15R), (15G)
, (15B) is the adder (14R), (14
G), 3 primary color data D IlmmHD 6-, [) B Yu which has undergone image enhancement processing using (14B).

Gamma correction processing is applied to the gamma correction processed three primary color data D l * * + D G * jl + D
@1) Output *.

In this way, the signal processing unit (7) generates the three primary color data D114. at a clock rate of 2 fs which has been subjected to image enhancement processing and gamma correction processing. .

Output D Qm*l D @am. 3 of the above 2fs clock rate output from this signal processing section (7)
Primary color data D. *+ D Gj) $+ D la* is
In addition to being supplied to the color encoder (8), it is also supplied to digital-to-analog (D/A) converters (9R) and (9G).
, (9B).

And the above D/A converter (9R), (9G),
(9B) is the 2 signal supplied from the signal processing section (7).
The three primary color data D 1m1T+DG*Y, Do, which ensured high resolution at the clock rate of fs, are converted to analog to produce an analog three primary color image output signal Rout+Goua,
BO□ signal output terminal (101?), (IOC)
, output from (IOB).

Further, the color encoder (8) has a specific configuration shown in FIG.
) to the three primary color data D at the clock rate of 2 fs.
@**, D G11llll D mm* is supplied to the matrix circuit (81), and this matrix circuit (81
) and a delay circuit (82) to which the luminance signal data D yes formed by
Each color difference signal data D I4$+ formed by 1)
D+*, D@ formed by the respective low-pass filters (83) (84) (85), (86) to which D m-v*D(m, D@yu is supplied) and the matrix circuit (81)
* is supplied via each of the above-mentioned low-pass filters (85) and (86), and a modulation circuit (87), and this modulation circuit (
An interpolation processing circuit (88) is supplied with the modulated output data by the interpolation processing circuit (87), and an interpolation processing circuit (88) is supplied with the interpolation processing output data by the interpolation processing circuit (88) and
81) Luminance signal data D y * * formed by
is supplied via the delay circuit (82).
89).

The matrix circuit (81) receives the three primary color data D@+111, DG* at a clock rate of 2(s).
By performing matrix calculation processing on 11 g D l * *, luminance signal data D yes at a clock rate of 2 fs and color difference signal data D at a clock rate of fs are obtained.

Y'l+ D s-Y*+ D + O, D0. form.

This color encoder (8) receives the three primary color data D. Outputting the luminance signal data D y * * from the matrix circuit (81) via the delay circuit (82) as component color image data for 1110 Gm1il D 1116;
The color difference signal data DI-V*+[), -v are outputted from the matrix circuit (81) via the low-pass filters (83) and (84). Note that the delay circuit (82) is an F-signed low-pass filter (83).
, (84) is expressed as the luminance signal data D
1. give to

In addition, in this color encoder (8), the F modulation circuit (87) directly receives the DI- and Do signals supplied from the matrix circuit (81) via the respective low-pass filters (85) and (86). Performs modulation processing to perform two-phase modulation. The modulated output data from this modulation circuit (87) corresponds to a modulated color difference signal containing odd-numbered harmonics of the color subsystem frequency rsc.

Further, the interpolation processing circuit (88) includes the modulation circuit (
Regarding the modulated output data according to 87), f9c component and 7
Digital filtering processing is performed to extract the fsc component, and 8r5. The modulated color difference signal data corresponding to the clock rate of 2 fs is formed.

The color encoder (8) receives the luminance signal data Dv output from the matrix circuit (81) via the delay circuit (82), and the interpolation processing circuit (
By adding the 2 fs Cronkrate modulated color difference signal data formed by 88) by the adder FIP1 (89), a digital composite video signal D (g*Y) is formed.

That is, the color encoder (8) generates 2 fs Cronkrate three primary color data D R that has been subjected to image enhancement processing and gamma correction processing by the signal processing unit (7).
11111D G*#I D About I+111, 1
-Secured high resolution of Kroncrate of 2Is-
The luminance signal data DV Yuyu and the above color difference signal data Dll-v*, Ds- of the S black 7 crate are
It outputs component color image data composed of y* and a digital composite video signal DC5** ensuring a high Cronk rate resolution of -1-2fs.

The above component color image data outputted from this color encoder (8), that is, the ten-dimensional signal data DV, Yu, and each of the above color difference signal data DR-□+DB-V
Yuha is a digital to analog ([1/A) converter (9Y
), (9R-Y), (9B-Y).

The above D/A converter (9'l), (911-Y),
(9B-Y) is the luminance signal data D1. And by analogizing each of the above color difference signal data Dll-v*+DBY*, an analog component color video signal Yout, RY0IITIB You
Signal output terminal (IOY) (IOR-Y) as y,
Output from (IOB-Y).

Further, the digital composite video signal OCS outputted from the color encoder (8) is supplied to a digital to analog (1)/A) converter (9C5). The above D/A converter (9C5) has the above 2fs
By converting the above-mentioned digital composite video signal I) CS, which ensures a high resolution of 7 Crate, into analog, an analog composite video signal CSO is created.
It is output from the signal output terminal (IOC5) as uy.

H Effects of the Invention As described above, in the signal processing circuit of the solid-state imaging device according to the present invention, the image pickup output signal from the image sensor surface body image sensor that employs the spatial pixel shifting method is not digitized by the analog-to-digital conversion means. Synthesizing a plurality of outputs obtained through a first delay circuit having at least one equal digital delay circuit with a first synthesizing means;
By combining a plurality of outputs obtained through a second delay circuit having a second delay circuit with a second combining means, the vertical band of the red image imaging signal, the red image imaging signal, or a composite signal of both signals is limited. . Then, the output signals of the first and second combining means are added in equal amounts by the adding means, and the added output signal is outputted as a horizontal detail signal via the digital filter means.

In this way, by adding equal amounts of the green image pickup signal, the red image pickup signal, the red image pickup signal, or a composite signal of both signals among the digital output signals of the analog-to-digital conversion means, by the addition means, All first-order carrier components are canceled, and a wideband horizontal detail signal can be formed without aliasing distortion.

Each signal added in equal amounts by the above-mentioned adding means is subjected to vertical band-limiting processing by the first and second combining means described in -F. The resulting horizontal detail signal has few unnecessary leakage components in the color subcarrier frequency domain in the frequency space, and high-quality horizontal contour enhancement processing can be performed without cross-color interference.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a three-panel color television camera device to which the present invention is applied, FIG. 2 is a schematic diagram showing the arrangement of each CCD image sensor in the three-panel color television camera device, and FIG. 4 is a diagram showing the signal spectrum of each imaging output signal from the CCD image sensor in the above-mentioned color television camera device C, and FIG. FIG. 5 is a block diagram showing a specific example of the configuration of the detail signal generation section of the signal processing section, and FIG. 6 is an equalization block diagram of the first digital filter circuit of the detail signal generation section. 7 is a characteristic diagram showing the filter characteristics of the first digital filter circuit, and FIG. 8 is a two-dimensional frequency characteristic diagram showing the frequency characteristics of the detail signal generated by the detail signal generating section The schematic diagram shown in FIG.
FIG. 0 is a characteristic diagram showing the filter characteristics of the second digital filter circuit, and FIG. 11 is a block diagram showing the configuration of a color encoder constituting the three-panel color television camera apparatus. FIG. 12 is a schematic diagram showing a signal spectrum of an image output signal from a general solid-state image sensor having a discrete picture element structure.

Claims (1)

[Claims] An imaging unit in which a solid-state image sensor for green image sensing, and solid-state image sensors for red and blue images are spatially shifted by 1/2 of the repetition pitch of each pixel. The analog-to-digital conversion means for digitizing each imaging output signal read out from each of the solid-state image sensors, and at least one digital delay means whose delay time is approximately equal to one horizontal scanning period,
A first delay circuit to which a green image imaging signal is supplied among each digital output signal of the digital conversion means, and at least one digital delay circuit whose delay time is approximately equal to one horizontal scanning period, A plurality of outputs from the first delay circuit are combined with a second delay circuit to which a red image pickup signal, a blue image pickup signal, or a composite signal of both signals are supplied from among the digital output signals of the conversion means. , a first synthesizing means for limiting the vertical band of the input signal to the first delay circuit; a second combining means for limiting the vertical band of the signal; an adding means for adding equal amounts of the outputs of the first and second combining means; and a digital filter means to which the output of the adding means is supplied. A signal processing circuit for a solid-state imaging device, comprising: a signal processing circuit for a solid-state imaging device, characterized in that a horizontal detail signal is obtained from the output of the digital filter means.